Soft-Error-Tolerant Ultralow-Leakage 12T SRAM Bitcell Design

This paper proposes a novel soft-error-tolerant ultralow-leakage 12T bitcell. Compared with all the other considered bitcells, the proposed cell saves 90.76% leakage power and 18.43% write access time on average. Simulation results verify the basic functions and single event upset (SEU) tolerance of the proposed. Hence, it is an excellent choice for highly reliable ultralow-leakage applications like the Internet of Things (IoT).