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Herein, the integration of solution-processed polymer thin-film transistors (TFTs) that were fabricated using selective wettability through ultraviolet (UV) exposure into a reflective liquid crystal display is demonstrated. From the experimental results of energy-dispersive spectroscopy, the composition of carbon and fluorine enhancing the hydrophobicity in the polymer chains was found to play a critical role in the wetting selectivity upon UV exposure. The polymer TFTs fabricated through the wettability-patterning process exhibited long-term stability and reliability. This wetting-selectivity-based patterning technique will be useful for constructing different types of solution-processed electronic and optoelectronic devices.

In this paper an examination is presented of the effect of the gate dielectric materials and bilayer stack on the negative bias illumination stress (NBIS) instability of InGaZnO (IGZO) TFTs. The threshold voltage (V"t"h) movement by NBIS was greatly dependent on the valence band off-set and the effective vertical electrical field, suggesting that the trapping or injection of photo-generated hole carriers into the gate insulator plays an important role. The process of hole carrier creation by photon irradiation onto the IGZO channel layer is shown by independent experiments to involve the oxygen vacancy defects. The reduction in the oxygen vacancy of IGZO semiconductor by the high pressure O"2 annealing resulted in the strong increase in the V"t"h instability induced by NBIS, indicating that the generation of hole carriers can result from the photo-induced transition mechanism from [V"O] to [V"O^2^+].

The effects of high-pressure annealing were investigated using amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs). The fabricated device annealed at 5 atm in H2O ambient showed the best electrical characteristics and stability under positive bias temperature stress (PBTS). This was attributed to mainly a reduction in the band bending at the overlap between the source–drain (S/D) electrodes and the etch stop layer (ESL). This is originated from the recovery of charge-trapping sites at in- and bottom-ESLs due to defect passivation with the aid of high-pressure thermal annealing at 5 atm in H2O ambient.

A full-color 14-inch active matrix organic light emitting diode (AMOLED) TV, which does not suffer from the well-known pixel non-uniformity of luminance using a simple pixel circuit design consisting of 3 transistors and 1 capacitor, has been developed using amorphous hafnium-indium-zinc oxide (a-HIZO) thin-film transistors (TFTs) as an active-matrix backplane. The n-channel a-HIZO TFTs exhibit a field-effect mobility of 10 cm2/V-s, threshold voltage of 0.38V, on/off ratio of >108, and subthreshold gate swing of 0.21 V/decade. Notably, the long- and short-range standard deviations for the threshold voltage were less than 0.1V and 0.02V, respectively.

In this paper, we analyzed electrical characteristics of amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) with plasma-exposed source-drain (S/D) bulk region. The parasitic resistance and effective channel length characteristics exhibit similar behavior with that of crystalline silicon metal oxide-semiconductor field effect transistor (c-Si MOSFET) that has doped S/D bulk region. The transfer curves little changed with gate overlap variation, and the width-normalized parasitic resistance obtained from transmission line method was as low as 3 to 6 Omegamiddotcm. The effective channel length was shorter than the mask channel length and showed gate-to-source (VGS) voltage dependency that is frequently observed for lightly doped drain (LDD) MOSFET. Experimental and simulation results showed that the plasma exposure caused an LDD-like doping effect in the S/D bulk region by inducing oxygen vacancy in the a-IGZO layer.

We have developed the stereo-corresponding algorithm using edge information. The conventional stereo-corresponding algorithm, SAD (Sum of Absolute Difference), has a good quality in case of texture region, but it has a false matching in the non-texture region. In order to reduce the false matching in the non-texture region, the new cost function, which is defined as SED (Sum of Edge Difference) based on the global optimization, is added to the cost function of SAD. We evaluate our algorithm and benchmark Middlebury database. The experimental results show that our proposed algorithm successfully produces piecewise smooth disparity maps while reducing the false matching in the non-texture region. Moreover, our algorithm is faster in getting the best quality than SAD.

This brief reports a flexible active-matrix organic light-emitting diode display based on a poly-Si thin-film transistor (TFT) backplane. The p-channel poly-Si TFTs on metal foil exhibited a maximum field-effect mobility of 86.1 cm/sup 2//Vs, threshold voltage of 3.5 V, gate voltage swing of 0.8 V/dec, and the minimum off current of 10/sup -12/ A//spl mu/m at V/sub ds/=-0.1 V. A 4.1-in active-matrix backplane was fabricated with the poly-Si TFT with a conventional pixel circuit consisting of 2 TFTs and one capacitor. The scan driver circuits with PMOS were integrated on the flexible metal foil. The top emission, organic light emitting display having a brightness of 100 cd/m/sup 2/.

We have successfully fabricated a novel 3-D vertically stacked complementary metal-oxide-semiconductor hybrid inverter using a lower p-type poly-Si thin-film transistor (TFT) and an upper n-type amorphous Ga-In-Zn-O (a-GIZO) TFT. The device was fabricated step by step, starting from the fabrication of the lower poly-Si TFT via a high-temperature process to the fabrication of the upper a-GIZO TFT via a low-temperature process; this was done to prevent damage to the TFTs and to optimize their characteristics. The entire process was further simplified by the coplane gate structure that allows successive formation of the a-GIZO TFT on the poly-Si TFT. The transfer characteristics show clear inverter actions, indicating high performances of the TFTs.

An on-glass integrated scan driver is proposed for oxide thin film transistors TFTs with negative threshold voltage. A coupling capacitor and a TFT for setting the initial voltage to the gate of a TFT were added to minimize the off-state current. Simulated and measured results indicate that the proposed scan driver shows no ripple and fast rise time/fall time of scan outputs. Circuit operation was verified with a 14-inch AMOLED panel.

We extracted the effective channel length and parasitic series resistance in a-IGZO inverted-staggered etch-stop (ES) TFTs. When there is an overlap between the drain or source electrode and the FET channel, the resistance of the channel underneath the overlapping regions is very low compared with other channel region resistance. As a result, the effective channel length is smaller than the physical length. The aforementioned definition of effective channel length in terms of device geometric parameters seems to be specific for ES a-IGZO TFTs.

This letter examines the effect of the gate dielectric material on the light-induced bias-temperature instability of an In-Ga-Zn-O (IGZO) thin-film transistor (TFT). After applying positive and negative bias stresses, the SiNx-gated TFT exhibited inferior stability to the SiO2-gated TFT, which was explained by the charge trapping mechanism. However, light illumination under a negative bias stress accelerated the negative displacement of the threshold voltage (Vth) of the SiNx-gated IGZO TFT compared to that of the SiO2-gated TFT. This was attributed to the injection of photocreated hole carriers into the underlying gate dielectric bulk region as well as the hole trapping at the gate/channel interface.

Full-color active-matrix organic light-emitting diode panels, driven by poly-Si thin-film transistors (poly-Si TFTs), were successfully fabricated on thin metal foil substrates. The p-channel poly-Si TFTs on metal foil showed a field-effect mobility of 82.9 cm2/Vmiddots, subthreshold slope of 0.34 V/dec, threshold voltage of -1.67 V, and off-current of 6.6times10-14 A/mum. The 5.6-in panel had 160 times RGB times 350 pixels, each of which had a pixel circuit of two TFTs and one capacitor

We investigated the effect of gate dielectric structure on the light-induced bias-temperature instability of IGZO TFT. After the application of light-induced negative bias stress, the SiO 2 /SiN x bilayer gate dielectric TFT exhibited the superior stability than single layer gate dielectric TFTs. Total applied electric field to bilayer gate dielectric layer(Device C) is −1.91MV/cm. However, electric field applied bilayer gate dielectrics divided between SiN x (−0.76MV/cm) and SiO 2 (−1.15MV/cm). In case of SiO 2 single layer(Device A) effective electric field is −1.52MV/cm. This result indicates that bilayer gate dielectric structure has reducing electric field to gate dielectric. In addition, we observed different recovery behavior after negative bias temperature illumination stress. SiO 2 /SiN x bilayer TFT showed quickly recovery after stress as same as SiO 2 single layer gate dielectric. This results can be explained photo-created charge temporary trapping at the SiO 2 /active interface. On the other hand, photo-created charge deeply injection to SiN x gate dielectric as well as trapping at the gate dielectrics/active interface.

We have investigated the stability of short channel (1.5μm) p-Type polycrystalline silicon (poly-Si) Thin Film Transistors (TFTs) on the glass substrate under AC bias stress. The variation of threshold voltage in short channel poly-Si TFT was considerably higher than that of long channel poly-Si TFT. Threshold voltage of the short channel TFT was considerably moved to the positive direction during AC bias stress, whereas the threshold voltage of a long channel was rarely moved. The variation of threshold voltage in the short channel p-type TFT under AC bias stess was more compared to that under DC bias stress. The threshold voltage of short channel (L=1.5μm) poly-Si TFT was increased about -7.44V from -0.305V to -7.745V when VGS = 5 (base value) ~ -15V (peak value), VDS = -15V was applied for 3,000 seconds. This positive shift of threshold voltage and significantly degraded s-swing value in the short channel TFT under dynamic stress (AC) may be due to the increase of the stress-induced trap state density at gate insulator / channel interface region.

ZnO-based TFTs are shown to have the high device performance as well as good uniformity, which make it suitable as a next generation backplane technology for large area AMOLED display.

Zinc-based metal oxide semiconductors have attracted attention as an alternative to current silicon-based semiconductors for applications in transparent and fl exible electronics. Despite this, metal oxide transistors require signifi cant improvements in performance and electrical reliability before they can be applied widely in optoelectronics. Amorphous indium‐zinc‐tin oxide (a-IZTO) has been considered an alternative channel layer to a prototypical indium‐gallium‐zinc oxide (IGZO) with the aim of achieving a high mobility (>40 cm 2 Vs −1 ) transistors. The effects of the gate bias and light stress on the resulting a-IZTO fi eldeffect transistors are examined in detail. Hydrogen impurities in the a-IZTO semiconductor are found to play a direct role in determining the photo-bias stability of the resulting transistors. The Al 2 O 3 -inserted IZTO thin-fi lm transistors (TFTs) are hydrogen-poor, and consequently show better resistance to the external-bias-thermal stress and photo-bias-thermal stress than the hydrogenrich control IZTO TFTs. First-principles calculations show that even in the amorphous phase, hydrogen impurities including interstitial H and substitutional H can be bistable centers with an electronic deep-to-shallow transition through large lattice relaxation. The negative threshold voltage shift of the a-IZTO transistors under a negative-bias-thermal stress and negative-bias-illumination stress condition is attributed to the transition from the acceptor-like deep interstitial H i − (or substitutional H-DX − ) to the shallow H i + (or H O + ) with a high (low) activation energy barrier. Conclusively, the delicate controllability of hydrogen is a key factor to achieve the high performance and stability of the metal oxide transistors.

This study examined the effects of hydrogen incorporation in amorphous indium gallium zinc oxide (IGZO) on the performance and photo-bias stability of the resulting thin-film transistors (TFTs). It was found that the threshold voltage of IGZO TFTs was negatively shifted without significant loss of the field-effect mobility and ION/OFF ratio with increasing hydrogen concentration, suggesting that interstitial hydrogen can act as a shallow donor. The hydrogen-doped device, however, showed more negative bias illumination stress (NBIS) instability than the undoped device, which cannot be explained by the simple shallow donor model. This NBIS-induced degradation might be associated with the increased tailing state distribution, which may stem from a hydrogen-related complex defect or compensation.

We have investigated the stability of short-channel (1.5 µm) p-type polycrystalline silicon (poly-Si) thin film transistors (TFTs) under AC bias stress. The threshold voltage of the short-channel (L=1.5 µm) poly-Si TFT was increased by about -7.44 V after AC bias stress, whereas the threshold voltage of the long-channel poly-Si TFT was relatively stable. A two-step degradation process was also observed. In the first step, the threshold voltage of short-channel poly-Si TFTs underwent a consistent positive shift for 100 s. In contrast, the threshold voltage started to undergo a negative shift when accompanied by significant degradation in the subthreshold region. This negative shift of threshold voltage and the significantly degraded subthreshold swing value in the short-channel TFT under dynamic stress may be mainly due to the generation of stress-induced deep- and shallow-level trapping states near the drain junction.

We have investigated the reliability of short-channel (L = 1.5 µm) p-type excimer-laser-annealed (ELA) polycrystalline silicon (poly-Si) TFTs under hot-carrier related static bias stress. The threshold voltage (ΔV TH = 0.59 V) of short-channel TFTs (L = 1.5 µm) was significantly more shifted to the positive direction than that (ΔV TH = 0.02 V) of long-channel TFTs (L = 7 µm) under the same stress condition for 100 s. This positive shift of threshold voltage may be attributed to electron trapping at the interface between the poly-Si film and the gate oxide layer. In addition, we have extracted the length of the drain extension from an equation of the pseudo-lightly doped drain (LDD) model to verify the existence of free hole charges induced near the drain junction. The transfer characteristics of the normal and drain-source swapped modes as well as the capacitance–voltage (C–V) characteristics with variation in channel length after the bias stress indicate that the electron trapping at the gate insulator/channel interface mainly occurred near the drain junction region. Furthermore, the threshold voltage of the short-channel ELA poly-Si TFTs with L = 1.5 µm was largely increased as the stress temperature was increased from room temperature to 100 °C, which indicates that the impact ionization occurs more at higher temperature.

— Amorphous-oxide thin-film-transistor (TFT) arrays have been developed as TFT backplanes for large-sized active-matrix organic light-emitting-diode (AMOLED) displays. An amorphous-IGZO (indium gallium zinc oxide) bottom-gate TFT with an etch-stop layer (ESL) delivered excel lent electrical performance with a field-effect mobility of 21 cm2/V-sec, an on/off ratio of >108, and a subthreshold slope (SS) of 0.29 V/dec. Also, a new pixel circuit for AMOLED displays based on amorphous-oxide semiconductor TFTs is proposed. The circuit consists of four switching TFTs and one driving TFT. The circuit simulation results showed that the new pixel circuit has better performance than conventional threshold-voltage (VTH) compensation pixel circuits, especially in the negative state. A full-color 19-in. AMOLED display with the new pixel circuit was fabricated, and the pixel circuit operation was verified in a 19-in. AMOLED display. The AMOLED display with a-IGZO TFT array is promising for large-sized TV because a-IGZO TFTs can provide a large-sized backplane with excellent uniformity and device reliability.

We have investigated the electrical characteristics of short-channel p-type excimer laser annealed (ELA) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) under high gate and drain bias stress. We found that the threshold voltage of short-channel TFTs was significantly shifted in the negative direction owing to high gate and drain bias stress (ΔV TH = -2.08 V), whereas that of long-channel TFTs was rarely shifted in the negative direction (ΔV TH = -0.10 V). This negative shift of threshold voltage in the short-channel TFT may be attributed to interface state generation near the source junction and deep trap state creation near the drain junction between the poly-Si film and the gate insulator layer. It was also found that the gate-to-drain capacitance (C GD) characteristic of the stressed TFT severely stretched for the gate voltage below the flat band voltage V FB. The effects of high gate and drain bias stress are related to hot-hole-induced donor like interface state generation. The transfer characteristics of the forward and reverse modes after the high gate and drain bias stress also indicate that the interface state generation at the gate insulator/channel interface occurred near the source junction region.

The impact of a gate insulator (GI) material on the device instability of InGaZnO (IGZO) thin film transistors (TFTs) was investigated. The IGZO TFTs with SiO 2 GI showed consistently better stability against the applied temperature stress and positive/negative gate bias stress than their counterparts with SiN x GI. This superior stability of the SiO 2 -gated device was attributed to the reduced total density of states (DOS) including the interfacial and semiconductor bulk trap densities. Based on the Meyer-Neldel rule, the total DOS energy distribution for both devices was extracted and compared, which can explain the experimental observation.

Amorphous oxide thin film transistor (TFT) arrays have been developed as TFT backplanes for large size active-matrix organic light emitting diode (AMOLED) displays. An amorphous IGZO (Indium Gallium Zinc Oxide) bottom gate TFT with an etch-stop layer (ESL) delivered excellent electrical performance with field- effect mobility of 21 cm2/V-s, an on/off ratio of >108, and subthreshold slope (SS) of 0.29V/dec. A full color 19-inch AMOLED display has been developed using the amorphous IGZO TFT backplane.

We investigated the threshold voltage (Vth) instability for various gate dielectrics (SiNx and SiOx) in amorphous indium-gallium-zinc oxide (a-IGZO) thin film transistors (TFTs). The a-IGZO TFTs with SiNx 150 °C exhibited reasonable electrical performance (field-effect mobility of 8.1 cm2/V s and Ion/off ratio of >108) but showed huge Vth shift under positive gate bias. The TFTs with SiOx dielectrics exhibit smaller Vth instability than those of SiNx dielectrics. This behavior can be explained by using simple charge trapping into the gate insulators and the difference of Vth instability on various dielectrics may be originated from the hydrogen contents, providing high density of charge traps in gate dielectrics.

We have fabricated 6.5 in. flexible full-color top-emission active matrix organic light-emitting diode display on a polyimide (PI) substrate driven amorphous indium gallium zinc oxide thin-film transistors (a-IGZO TFTs). The a-IGZO TFTs exhibited field-effect mobility (μFE) of 15.1 cm2/V s, subthreshold slope of 0.25 V/dec, threshold voltage (VTH) of 0.9 V. The electrical characteristics of TFTs on PI substrate, including a bias-stress instability after 1 h long gate bias at 15 V, were indistinguishable from those on glass substrate and showed high degree of spatial uniformity. TFT samples on 10 μm thick PI substrate withstood bending down to R=3 mm under tension and compression without any performance degradation.

A high-performance p-type excimer laser annealed (ELA) polycrystalline silicon (poly-Si) thin-film transistor (TFT) was fabricated on a glass substrate. We have investigated the electrical characteristics of short-channel p-type ELA poly-Si TFTs under off-state bias stress. We have found that the threshold voltage of the short-channel TFT (L = 1.5 µm) significantly shifted in the positive direction under off-state bias stress (ΔVTH = 2.71 V), whereas the threshold voltage of long-channel TFT (L = 7 µm) barely moved in the positive direction (ΔVTH = 0.11 V). This positive shift of threshold voltage in the short-channel TFT may be attributed to electron trapping at an interface between the poly-Si film and the gate oxide layer. In addition, we have extracted the length of the drain extension from an equation of the pseudo-lightly doped drain (LDD) model to verify the existence of free hole charges induced near the drain junction. The transfer characteristics of the forward and reverse modes after the off-state bias stress indicate that the electron trapping at the gate insulator/channel interface occurred near the drain junction region. The leakage current of the ELA poly-Si TFT was also suppressed without reducing the on-current level under the off-state bias stress due to the creation of a pseudo-LDD region.

— A full-color 12.1-in.WXGA active-matrix organic-light-emitting-diode (AMOLED) display was, for the first time, demonstrated using indium-gallium-zinc oxide (IGZO) thin-film transistors (TFTs) as an active-matrix backplane. It was found that the fabricated AMOLED display did not suffer from the well-known pixel non-uniformity in luminance, even though the simple structure consisting of two transistors and one capacitor was adopted as the unit pixel circuit, which was attributed to the amorphous nature of IGZO semiconductors. The n-channel a-IGZO TFTs exhibited a field-effect mobility of 17 cm2/V-sec, threshold voltage of 1.1 V, on/off ratio >109, and subthreshold gate swing of 0.28 V/dec. The AMOLED display with a-IGZO TFT array is promising for large-sized applications such as notebook PCs and HDTVs because the a-IGZO semiconductor can be deposited on large glass substrates (larger than Gen 7) using the conventional sputtering system.

We investigated the effect of the high-k TiOx (k∼40) gate dielectric on the mobility (μFE) of indium-gallium-zinc oxide (IGZO) transistors. As the thickness of the TiOx layer at the interface of the IGZO channel and SiNx gate dielectric layer increased from 2 to 8 nm, the μFE value was monotonously reduced from 9.9 to 1.8 cm2/V s. The degradation of the mobility was attributed to the Coulomb scattering mechanism rather than the phonon scattering mechanism of the high-k TiOx layer based on the behavior of the temperature-dependent mobilities for all of the IGZO transistors.

The electrical instability in thin-film transistors (TFTs) based on amorphous indium-gallium-zinc oxide (a-IGZO) was investigated using constant bias and constant current stress. Stress conditions were chosen such that TFT is turned on, whereas the potential at the gate dielectric-a-IGZO interface is below the electron accumulation threshold. Drain current in this low bias regime is still sufficient for driving pixels in an organic light-emitting diode display (AMOLED). We found that the degradation is due to charge trapping near the a-IGZO-gate dielectric interface. The obtained results enabled a straightforward assessment of a-IGZO TFTs' instability for their application in AMOLEDs.

The world largest flexible full color 6.5-inch active matrix organic light emitting diode (AMOLED) display with top emission mode on plastic film is demonstrated. The active matrix backplanes were fabricated using metal oxide thin film transistors (TFTs). The n-channel metal oxide TFTs on plastic film exhibited field-effect mobility of 17.8 cm2/Vs, threshold voltage of 0.4 V, on/off ratio of 1.1× 108, and subthreshold slope of 0.34 V/dec. These TFT performance characteristics made it possible to integrate scan driver circuit, demux switching and compensation circuit on the panel. Bending tests were performed with TFT backplane samples to determine critical curvature radius to which the panel can be bent without TFT performance degradation. The results were compared with the calculations that took into account thicknesses and mechanical constants of flexible substrate and of thin-film layers in AMOLED device.

Embedded nonvolatile memory (NVM) devices with solid-phase crystallized polycrystalline silicon (poly-Si) films and an oxide-nitride-oxynitride (ONOn) stack structure on a glass panel were fabricated and investigated for system-on-panel applications. Memory-in-pixel and memory blocks are expected to be integrated in display panels as the integration of display systems progresses. Poly-Si thin-film transistor technology and a low temperature method to deposit an ultrathin tunneling layer using plasma-assisted oxynitridation were used to fabricate embedded poly-Si NVM devices on glass panels. A memory window from +2.4 to - 1.72 V was obtained at a low operating voltage with an erasing voltage of +11 V and a programming voltage of - 10 V. Moreover, an extrapolation of the performance of the fabricated poly-Si NVM device suggests that it retains a threshold voltage window of more than 80% between the programming and erasing states up to 10 years. The results demonstrate that the proposed devices with poly-Si layers using solid-phase crystallization and ONOn stack structures have suitable switching and retention characteristics for data storage applicable to real flat-panel display applications.

We investigated the impact of the passivation layer on the stability of indium-gallium-zinc oxide (IGZO) thin film transistors. While the device without any passivation layer showed a huge threshold voltage (Vth) shift under positive gate voltage stress, the suitably passivated device did not exhibit any Vth shift. The charge trapping model, which has been believed to be a plausible mechanism, cannot by itself explain this behavior. Instead, the Vth instability was attributed to the interaction between the exposed IGZO backsurface and oxygen and/or water in the ambient atmosphere during the gate voltage stress.

We investigated the feasibility of controlling the threshold voltage (Vth) by adjusting the thickness of the active layer (tactive) rather than by conventional chemical doping in indium-gallium-zinc oxide (IGZO) transistors with an inverted staggered structure. The value of Vth of the IGZO transistor was linearly modulated from −15.3±1.6to−0.1±0.21V by reducing tactive without any significant change in the field-effect mobility (μFE), subthreshold gate swing, or Ion∕off ratio. The free electron density extracted from the relationship between tactive and Vth was 1.9×1017cm−3, which was consistent with the value of 1.5×1017cm−3 obtained from the C-V measurement for the 30-nm-thick IGZO films. The slight increase in the μFE with increasing tactive, which was in contradiction with the behavior of the corresponding amorphous Si transistor, was explained by the anomalous behavior of the source/drain contact resistance.

The effect of water exposure on amorphous indium-gallium-zinc oxide (a-IGZO) semiconductors was reported. It was found that water can diffuse in and out of the a-IGZO film, reversibly affecting the transistor properties. Two competing mechanisms depending on the thickness of the active channel were clarified. The electron donation effect caused by water adsorption dominated for the thicker a-IGZO films (⩾100nm), which was manifested in the large negative shift (>14V) of the threshold voltage. However, in the case of the thinner a-IGZO films (⩽70nm), the dominance of the water-induced acceptorlike trap behavior was observed. The direct evidence for this behavior was that the subthreshold swing was greatly deteriorated from 0.18V/decade (before water exposure) to 4.4V/decade (after water exposure) for the thinnest a-IGZO films (30nm). These results can be well explained by the screening effect of the intrinsic bulk traps of the a-IGZO semiconductor.

We developed a 2 inch low temperature poly-Si active-matrix organic light-emitting diode (AMOLED) with an embedded p-i-n photodiode. The pixels for both OLED and photodiode are designed using poly-Si TFT and poly-Si p-i-n. The lateral p-i-n photodiode exhibited the photo response of ∼40 dB under 100 lux. We have demonstrated the display and sensors successfully on glass. This technology can be used for AMOLED integrated with touch sensor and brightness control sensor.

The effect of the channel deposition pressure on the device performance of amorphous indium-gallium-zinc oxide (a-IGZO) transistors was investigated in detail. The performance of the fabricated transistors improved monotonously with decreasing chamber pressure: at a pressure of 1 mTorr, the field-effect mobility (μ FE ) and subthreshold gate swing (S) of the a-IGZO thin-film transistors were dramatically improved to 21.8 cm 2 /Vs and 0.17 V/decade, respectively, compared to those (11.4 cm 2 /Vs and 0.87 V/decade) of the reference transistors prepared at 5 mTorr. This enhancement in the subthreshold characteristics was attributed to the reduction of the bulk defects of the a-IGZO channel, which might result from the greater densification of the a-IGZO films at the lower deposition pressure.

The current conduction mechanism in radio frequency sputtered amorphous indium gallium zinc oxide (a-IGZO) films was investigated using model devices designed to mimic the carrier injection from an electrode to an a-IGZO channel in thin-film transistors. Interface-limited mechanisms, such as thermionic emission and Fowler-Nordheim tunneling, clearly fail to fit the current-voltage (I-V) curves. Instead, the I-V characteristics of the a-IGZO devices fit well within the framework of space-charge-limited current, whereas the conduction is enhanced by the Frenkel effect at high field (>0.1 MV/cm).

In this work, we review the current technological challenges for large-Size AMOLED displays with an emphasis on the backplane technology. Then, it will be discussed how the new technology of oxide TFTs combines the advantages of LTPS and a-Si TFTs to make an optimal solution for large-Size backplanes. In particular, we reveal the technological challenges in oxide TFTs by comparing the device characteristics of conventional excimer laser annealing (ELA) LTPS and amorphous indium-gallium-zinc-oxide (a-IGZO) TFTs. Finally, we demonstrate a 12.1″ WXGA AMOLED prototype display fabricated by an a-IGZO TFT backplane.

The full color 12.1-inch WXGA active-matrix organic light emitting diode (AMOLED) display was, for the first time, demonstrated using indium-gallium-zinc oxide (IGZO) thin-film transistors (TFTs) as an active-matrix back plane. It was found that the fabricated AMOLED display did not suffer from the well-known pixel non-uniformity of luminance, even though the simple structure consisting of 2 transistors and 1 capacitor was adopted as a unit pixel circuit, which was attributed to the amorphous nature of IGZO semiconductor. The n-channel a-IGZO TFTs exhibited the field-effect mobility of 8.2 cm2/Vs, threshold voltage of 1.1 V, on/off ratio of > 108, and subthreshold gate swing of 0.58 V/decade. The AMOLED display with a-IGZO TFT array would be promising for large size applications such as note PC and HDTV because a-IGZO semiconductor can be deposited on large glass substrate (> Gen. 7) using conventional sputtering system.

High-performance thin-film transistors TFTs, in which the channel material consisted of amorphous indium-gallium-zinc oxide a-IGZO with a bottom gate architecture, were fabricated for array applications. It was found that the dependence of the field-effect mobility on the channel length was greatly affected by the value of the contact resistance RC. A high contact resistance RCW 200 cm resulted in a significant drop 22.3% in the normalized field-effect mobility for the short channel device 10 m, while contact-limited behavior was hardly seen for the device with a low contact resistance RCW 23 cm. The difference in the channel length dependence of the field-effect mobility was comprehensively investigated based on the conduction mechanism. The fabricated n-channel a-IGZO TFTs with W/L =1 0/10 m exhibited a field-effect mobility of 12.6 cm 2 /V s, threshold voltage of 4.7 V, on/off ratio of 10 8 , and subthreshold gate swing of 0.56 V/decade.

The authors report the fabrication of high performance thin film transistors (TFTs) with an amorphous indium gallium zinc oxide (a-IGZO) channel, which was deposited by cosputtering using a dual IGZO and indium zinc oxide (IZO) target. The effect of the indium content on the device performance of the a-IGZO TFTs was investigated. At a relatively low IZO power of 400W, the field-effect mobility (μFE) and subthreshold gate swing (S) of the a-IGZO TFTs were dramatically improved to 19.3cm2∕Vs and 0.35V/decade, respectively, compared to those (11.2cm2∕Vs and 1.11V/decade) for the TFTs with the a-IGZO channel (reference sample) prepared using only the IGZO target. The enhancement in the subthreshold IDS-VGS characteristics at an IZO power of 400W compared to those of the reference sample was attributed to the reduction of the interface trap density rather than the reduction of the bulk defects of the a-IGZO channel.

The effect of Ar plasma treatment on amorphous indium gallium zinc oxide (a-IGZO) thin films was investigated. The net electron carrier concentration (1020–1021cm−3) of the a-IGZO thin films dramatically increased upon their exposure to the Ar plasma compared to that (1014cm−3) of the as-deposited thin film. The authors attempted to reduce the contact resistance between the Pt∕Ti (source/drain electrode) and a-IGZO (channel) by using the Ar plasma treatment. Without the treatment, the a-IGZO thin film transistors (TFTs) with W∕L=50∕4μm exhibited a moderate field-effect mobility (μFE) of 3.3cm2∕Vs, subthreshold gate swing (S) of 0.25V∕decade, and Ion∕off ratio of 4×107. The device performance of the a-IGZO TFTs was significantly improved by the Ar plasma treatment. As a result, an excellent S value of 0.19V∕decade and high Ion∕off ratio of 1×108, as well as a high μFE of 9.1cm2∕Vs, were achieved for the treated a-IGZO TFTs.

The authors report on the fabrication of thin film transistors (TFTs), which use an amorphous indium gallium zinc oxide (a-IGZO) channel, by rf sputtering at room temperature and for which the channel length and width are patterned by photolithography and dry etching. To prevent plasma damage to the active channel, a 100-nm-thick SiOx layer deposited by plasma enhanced chemical vapor deposition was adopted as an etch stopper structure. The a-IGZO TFT (W∕L=10μm∕50μm) fabricated on glass exhibited a high field-effect mobility of 35.8cm2∕Vs, a subthreshold gate swing value of 0.59V∕decade, a thrseshold voltage of 5.9V, and an Ion∕off ratio of 4.9×106, which is acceptable for use as the switching transistor of an active-matrix TFT backplane.

We have developed a 4.0 inch pentacene organic thin-film transistors (OTFTs) based active matrix organic light-emitting diode (AMOLED) display. To achieve bright and uniform displays, we have investigated several process issues unique to OTFT-based OLEDs. A bottom contact structure was used to fabricate the pentacene TFT backplane. Fine metal masking (FMM), laser ablation technique (LAT), and polyvinyl alcohol based patterning method were used to isolate the pentacene active layer. The low processing temperature (maximum 150°C) may allow the use of polymeric substrates and lower cost processing. Uniform TFT performance is achieved with reasonably good mobility and on/off ratio. The initial OLED display performance is also presented.

The world first flexible full color 5.6-inch active matrix organic light emitting diode (AMOLED) display with top emission mode on stainless steel foil is demonstrated. The active matrix back planes were fabricated using low temperature poly-Si (LTPS). The p-channel poly-Si TFTs on the stainless steel foil exhibited the field-effect mobility of 71.2 cm2/Vs, threshold voltage of −2.7 V, off current of 6.7× 1013 A/um, and subthreshold slope of 0.63 V/dec. These TFT performances made it possible to integrate scan driver circuit on the panel. A low-cost planarization techniqe of stainless steel foil was developed to replace the expensive chemical mechanical planarization (CMP) method, which was the most critical barrier against mass production. The full color flexible AMOLED display on the stainless steel foil will be promising for mobile applications because of its thin, light, rugged, and design-free properties.

The use of a double-layer, plasma-enhanced chemical vapor deposited SiO2/SiN x film as a gate dielectric material for polysilicon thin-film transistors was investigated in order to reduce mobile ion contamination and to improve gate oxide integrity degradation. We observed that the interposed silicon nitride film between the gate electrode and the SiO2 gate insulator prevents the incorporation of mobile ions into the SiO2 film, and also increases the breakdown voltage of the gate-insulating film. The mobile ion densities for the double SiO2/SiN x and single SiO2 gate dielectrics (no interposed SiN x layer between the gate electrode and SiO2 gate insulator) were 1.3 ×1011 and 1.7 ×1012/cm2, respectively. The breakdown fields at the 50% failure points in the Weibull plots for the double and single dielectric cases were 8 and 5 MV/cm, respectively. We conclude that the silicon nitride layer of the double gate insulator film minimizes ion contamination, leading to the enhancement of breakdown characteristics.

A high-resolution 5.7″ VGA mono cholesteric reflective liquid crystal display was demonstrated using a STN driver. We have reduced the driving voltage of Ch-LCD by optimizing panel conditions and adding low molecular materials. The optimized driving voltage was enough to drive the display, necessary for using a commercial STN driver.