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A 12-bit partial segmented current steering digital to analog converter (DAC) with low glitch area, power consumption, and integral nonlinearity (INL) error is proposed in this work. The cause of the glitch area and its possible solutions are explored. A current-mode logic (CML) latch with reduced output swing (Vdd to slightly below threshold voltage) is used at the input to the differential switch which reduces the glitch area (also known as glitch energy) significantly to 0.25 pVs. Further, this latch is used in the digital block of the proposed DAC to reduce the area and power requirement of the overall design. A dummy switch is used at the output of the differential switch to diminish effect of charge feedthrough at the output node of a current steering DAC. It also helps in the reduction of minimum allowable voltage headroom as compared to conventional double cascode structure and reduction of total power consumption to 9.1 mW operating at 200 MHz. The design and simulation of current steering DAC are performed in a 0.18 μm standard CMOS technology library using Cadence Virtuoso tool with a supply voltage of 1.8 V.

The combination of better transport properties of III-V group semiconductors along with excellent electrostatic control of surrounding gate is a promising option for the future low power electronics. Accordingly in this brief, the major figures of merit (FOM) including output current, output conductance (gd), transconductance generation factor (TGF), intrinsic gain (dB), and dynamic power dissipation are computed for surrounding-gate field effect transistors (SG-FETs) considering III-V group semiconductors and Si channel material respectively with respect to different device parameters. It is noticed that the center potential is higher in AlGaN/GaN SG-FET than Si for different values of channel length (CL), channel height (H), oxide thickness (tox), and doping concentration (Nd). The AlGaN/GaN SG-FET provides lower gd than Si for different values of CL, H, tox, and Nd as required for MOS analog circuits to achieve higher gain. The peak value of TGF and intrinsic gain is higher in AlGaN/GaN than Si SG-FET for different values of CL, H, tox, and Nd. In this work, we have analyzed the MOSFET structure for normally off operation of AlGaN/GaN high electron mobility transistors (HEMTs) to reduce dynamic power dissipation (PD). The magnitude of PD is calculated to be lower in normally off AlGaN/GaN SG-FET than Si for different values of CL, H, and tox.

The ever-increasing demand for high-quality digital video requires efficient compression techniques and fast video codecs. It necessitates increased complexity of the video codec algorithms. So, there is a need for hardware accelerators to implement such complex algorithms. The latest video compression algorithms such as High-Efficiency Video Coding (HEVC) and Versatile Video Coding (VVC) have been adopted Context-based Adaptive Binary Arithmetic Coding (CABAC) as the entropy coding method. The CABAC has two main data processing paths: regular and bypass bin path, which can achieve good compression when used with Syntax Elements (SEs) statistics. However, it is highly intrinsic data dependence and has sequential coding characteristics. Thus, it is challenging to parallelize. In this work, a 6-core bypass bin path having high-throughput and low hardware area has been proposed. It is a parallel architecture capable of processing up to 6 bypass bins per clock cycle to improve throughput. Further, the resource-sharing techniques within the binarization and a common controller block have reduced the hardware area. The proposed architecture has been simulated, synthesized, and prototyped on 28 nm Artix 7 Field Programmable Gate Array (FPGA). The implementation of Application Specific Integrated Circuit (ASIC) has been done using 65 nm CMOS technology. The proposed design achieved a throughput of 1.26 Gbin/s at 210 MHz operating frequency with a low hardware area compared to existing architectures. This architecture also supports multi-standard (HEVC/VVC) encoders for Ultra High Definition (UHD) applications.

In this brief, the center potential based analysis of Si and AlGaN/GaN gate all around field effect transistors (GAA-FET) is presented. The center potential is calculated for different values of channel length, channel height, doping concentration, and thickness of oxide layer using numerical simulations and analytical modeling. The results obtained using numerical simulations through TCAD are validated and found in decent accord with the analytical modeling. The lower effective mass of the III-V channel material results in the lower density of states (DOS), so quantum capacitance reduces significantly in III-V GAA-FET as compared to Si. This small DOS of III-V directly results in a low sheet carrier concentration at a certain gate overdrive voltage for III-V GAA-FET. The analog and linearity/distortion parameters of III-V and Si GAA-FET are calculated and compared. The utility of the III-V GAA-FET extends in high speed and low power digital logic applications, RF design applications including low noise and very high frequency due to better electron transport properties than Si.

A small-signal radio-frequency (RF) parameters extraction model along with analog/RF and linearity distortion performance analysis are realized for virtually doped (VD) recessed source/drain dopingless junctionless transistor (Re S/D DLJLT) via 3-D device simulations. A simple and accurate RF non-quasi-static (NQS) model is developed to directly extract the extrinsic and intrinsic parasitic components through Y-parameters in OFF and ON-state respectively. Furthermore, direct comparison of DC, analog/RF, linearity figure of merits (FOMs), and Y-parameter extractions are made with recessed source/drain junction transistor (Re S/D JT) with identical threshold voltage (Vth) and device dimensions at GHz frequency range. Virtual doping, due to charge-plasma (CP) concept, provides N+ source/drain (S/D) regions by choosing a most convenient metal work function (WF = 3.9 eV; Hafnium) at S/D. Re S/D provides reduced series resistance without an increase in gate-drain Miller capacitance leading to improved drive current. In addition, the present device uses an intrinsic channel and does not require to be doped at S/D resulting in dopingless junctionless transistor (DLJLT). For both devices, gate length (L) is taken as 30 nm, which separated into control gate (L1) and screen gate (L2) and 3-D simulations are carried out by varying control to screen gate length ratios (CSLR) to obtain optimum results. Obtained results disclose that Re S/D DLJLT provides considerably improved performances in terms of DC, analog/RF, linearity, transient, and small-signal admittance parameters over Re S/D JT due to improved drive current and reduced short channel effects (SCEs). Accordingly, for high-performance RF applications, Re S/D DLJLT may be preferred over Re S/D JT due to significantly enhanced cut-off frequency (up to 0.399 THz) and maximum oscillation frequency (up to 1.226 THz).

A distinctive charge plasma approach is used to propose a novel dual-metal-gate (DMG) recessed-source/drain dopingless junctionless transistor (Re S/D DLJLT) in which the source/drain (S/D) series resistance is reduced without any increment of the gate-to-drain Miller capacitance. In this device, the charge plasma approach is applied to induce an N+ (virtually doped) S/D region by using metals with appropriate work functions for the electrodes. The direct-current (DC) and analog/radio frequency (RF) figures of merit (FOMs) of the proposed device are analyzed using two-dimensional (2-D) numerical calculations and compared with those for a DMG recessed-source/drain junction transistor (Re S/D JT) of identical dimensions. The results reveal that the DMG-Re S/D DLJLT exhibits enhanced DC and analog/RF performance compared with the DMG-Re S/D JT. The total gate length (L) is divided between the control gate (L1) and screen gate (L2), and the numerical investigations are carried out with different ratios of the control gate to screen gate lengths (L1:L2) to determine the optimized gate length for the DMG. A subthreshold slope of 61.32 mV/dec is obtained for the proposed device with L1:L2 = 1:1. An improvement in the ON-state current (ION) is observed due to the introduction of the charge plasma concept, which also reduces the OFF-state leakage current (IOFF) and causes a net enhancement in the ION/IOFF ratio. The device proposed herein also solves the problems of random doping fluctuation, doping activation, and threshold voltage variation and may thus be preferred over DMG-Re S/D JTs for use in analog/RF and digital applications due to its improved performance.

Poisoning is a major global health problem and one of the leading causes of morbidity and mortality in the developing world including Nepal. The scenario of poisoning can vary among demographics and geography within the country. This study aims to find out the scenario of poisoning cases in Devdaha Medical College Teaching Hospital (DMCTH), Rupandehi, Nepal. It is a hospital-based retrospective study that was carried out in the Emergency Department of DMCTH from August 2013 to July 2015. Out of the total 107 cases, more of the poisoning cases were found in the third decade of life (21-30 yrs) followed by the second decade (11-20 yrs). The minimum cases of poisoning were observed among females aged above 60 years and males aged 51-60 yrs. Most of the patients recovered and were discharged within three days of admission. Five fatal cases were found. Pesticides and insecticides were the common poisoning agents used. The incidence of poisoning was prevalent among the young adult (15-29 yrs) patients admitted to DMCTH. A higher incidence of intentional poisoning was found in this study. Implementation of effective prevention strategies can minimize the incidences of poisoning while early detection and effective management of poisoning can minimize mortality.

Linearity and intermodulation distortion (IMD) analysis examined major reliability issues that arise due to the non-linear behavior of the devices in analog/RF circuit applications. In this paper, by means of virtually doped (dopingless), a distinctive influence of charge-plasma (CP) is proposed on novel dual metal gate (DMG; control and screen gate) recessed source/drain (Re S/D) transistor; envisaged as recessed source/drain dopingless junctionless transistor (Re S/D DLJLT). Re S/D structure diminishes series resistance without any accretion of the gate-drain Miller capacitance resulting in a better drive current (ION). DC and analog characteristics have been further improved by adopting CP conception for induction of N+ S/D region owing to favorably well-chosen metal work function electrodes. The main intent of this paper is to appraise the linearity and IMD performance characteristics of the Re S/D DLJLT using 2-D numerical calculations and scrutinize the distinction with recessed source/drain junction transistor (Re S/D JT) with identical dimensions. Device linearity parameters comprise of transconductance (Gm1) and its higher order coefficients (Gm2 and Gm3), second and third order voltage and input intercept point (VIP2, VIP3, and IIP3) third order IMD, and 1 − dB compression point (1 − dBCP) which are based on possible structural and control to screen gate length ratios (CSLR) variations in both devices. The influences of parametric modifications on linearity Figure of merits (FOMs) explore optimum bias point by investigating optimum structural with CSLR variations. The detailed investigation of linearity FOMs of the impact on different device engineering has been carried out. The obtained outcomes divulge that proposed device delivers appreciably enhanced linearity FOMs as compared to Re S/D JT.

In this study, the authors propose a novel MgZnO/CdZnO Quadruple-Gate Field Effect Transistor (QG-FET). The analog/RF and linearity distortion performance of the proposed QG-FET has been analysed and compared with conventional AlGaN/GaN QG-FET having identical physical dimensions. The performance parameters including drain current (IDS), gate capacitance (Cgs), output-conductance (gd), transconductance (gm1), transconductance generation factor (TGF), intrinsic-gain (dB), cut-off frequency (fT), transconductance frequency product (TFP), first and second order derivatives of gm1 (i.e., gm2 and gm3), third order intermodulation distortion (IMD3), third order input intercept point (IIP3), and extrapolated input voltages (VIP2 and VIP3) have been calculated. The consequences of variations in physical parameters of proposed QG-FET viz., thickness of oxide layer (tox), channel length (CL), and doping concentration (Nd) on the analog/RF and linearity distortion parameters are analyzed and compared with conventional AlGaN/GaN QG-FET. It has been revealed that MgZnO/CdZnO QG-FET yields higher IDS, gm1, TGF, intrinsic gain (dB), fT, and TFP than conventional AlGaN/GaN QG-FET with respect to different values of tox, CL, and Nd.

In this work, analog and linearity distortion performance of a III–V AlGaN/GaN quadruple gate field effect transistor (III–V QG-FET) has been analyzed and compared with conventional Si QG-FET having identical physical dimensions. Specifically, we investigate the linearity by numerically computing transconductance (gm1), its second and third order derivatives (gm2 and gm3), along-with linearity metrics comprising of third order intermodulation distortion (IMD3), third order input intercept point (IIP3), and extrapolated input voltages (VIP2 and VIP3). The consequences of variations in physical parameters of III–V QG-FET, i.e., channel length, channel height, the thickness of oxide layer, doping concentration, along-with temperature on the linearity metrics parameters, drain current, and threshold voltage are analyzed and compared with Si QG-FET. The gate capacitance and dynamic power dissipation is calculated numerically and compared by performing small signal AC analysis at 1 MHz frequency for III–V and Si QG-FETs. The influence of variations in above mentioned physical parameters is also analyzed on dynamic power dissipation and gate capacitance considering the effects of quantum capacitance in the nanometer regime. The present analysis reveals that in III–V QG-FET, the dynamic power dissipation is considerably reduced than its contender Si QG-FET due to its reduced threshold voltage, and thus it is a more promising candidate for analog and low power dissipation applications.

Background: The present study was conducted to assess predictive factors for difficult laparoscopic cholecystectomy. Materials & Methods: 84 patients having symptomatic gallstone disease were included. After the surgery, patients were group into 2 groups those who had a successful laparoscopic cholecystectomy and those cases who had conversion to open cholecystectomy. Results: Total 6 cases underwent conversion. Out of 15 patients with age >50 years, 3 underwent conversion and out of 69 patients with age 50 years were predictive factors for conversion.

Tremendous explosion of population has led to about 200% increment of total energy consumptions in last twenty-five years. Apart from conventional fossil fuel as limited energy source, alternative non-conventional sources are being explored worldwide to cater the energy requirement. Lignocellulosic biomass conversion for biofuel production is an important alternative energy source due to its abundance in nature and creating less harmful impacts on the environment in comparison to the coal or petroleum-based sources. However, lignocellulose biopolymer, the building block of plants, is a recalcitrant substance and difficult to break into desirable products. Commonly used chemical and physical methods for pretreating the substrate are having several limitations. Whereas, utilizing microbial potential to hydrolyse the biomass is an interesting area of research. Because of the complexity of substrate, several enzymes are required that can act synergistically to hydrolyse the biopolymer producing components like bioethanol or other energy substances. Exploring a range of microorganisms, like bacteria, fungi, yeast etc. that utilizes lignocelluloses for their energy through enzymatic breaking down the biomass, is one of the options. Scientists are working upon designing organisms through genetic engineering tools to integrate desired enzymes into a single organism (like bacterial cell). Studies on designer cellulosomes and bacteria consortia development relating consolidated bioprocessing are exciting to overcome the issue of appropriate lignocellulose digestions. This review encompasses up to date information on recent developments for effective microbial degradation processes of lignocelluloses for improved utilization to produce biofuel (bioethanol in particular) from the most plentiful substances of our planet.

In this article, a distinctive charge plasma (CP) technique is employed to design two doping-less dual gate tunnel field effect transistors (DL-DG-TFETs) with Si0.5Ge0.5 and Si as source material. The CP methodology resolves the issues of random doping fluctuation and doping activation. The analog and RF performance has been investigated for both the proposed devices i.e. Si0.5Ge0.5 source DL-DG-TFET and Si-source DL-DG-TFET in terms of drive current, transconductance, cut-off frequency. In addition, the linearity and distortion analysis has been carried out for both the proposed devices with respect to higher order transconductance (gm2 and gm3), VIP2, IMD3, and HD2. The Si0.5Ge0.5 source DL-DG-TFET has better performance characteristics and reliability in compare to Si-source DL-DG-TFET owing to low energy bandgap material and higher mobility. The switching ratio obtained for Si0.5Ge0.5 source DL-DG-TFET is order of 5×1014 that makes it a suitable contender for low power applications.

Cardiac arrhythmia is a condition of irregular heartbeat, which causes sudden loss of life, which insists the necessity for the continuous monitoring of the arrhythmia patients so that an appropriate medical procedure is provided, for which the smart healthcare plays a major role. Cardiac arrhythmia is one among a type of cardiovascular diseases (CVDs), which reports 12% of total deaths all-over the world. Even though there is a lot of growth in IoT-health monitoring, the manual method suffers from a lot of drawbacks. Hence, there is a need for an automatic method in health-care specifically, for classification of arrhythmia. In this research, we analyze various automatic methods used for classifying arrhythmia in IoT network. This research presents the detailed review of 25 research papers suggesting the methodologies based on various Machine Learning Methods, Deep learning method, nature-inspired methodologies, and so on, for the automatic prediction of Arrhythmia. The collected papers are classified based on different prediction and clustering classification techniques. The research gaps and the challenges faced by the existing techniques are listed and elaborated, which helps the researchers to upgrade the future works. The works utilize various datasets, software tools, performance evaluation measures, prediction techniques, which are analyzed and the performance attained by different techniques are discussed and the research gaps for further contributions are identified in such a way that it enables the researcher to contribute much for the benefit of the society.

A low power 12-bit current steering DAC is designed using SCL 180-nm-technology. Various methodologies are considered to reduce the power consumption in current steering DAC. The current mode logic (CML)-based latch is incorporated to design latch cum-level shifters to reduce digital power consumption. A dummy switch compensation technique is also used at the output of switch to counter the effect of charge feedthrough from switch to the output of DAC. In addition, it also reduces the minimum allowable voltage headroom, thus reducing power consumption of analog block. The power consumption obtained is 12 mW for 12-bit design operating at 200 MHz frequency.

Adiabatic logic has been found to be effective in achieving low power in VLSI circuits. In subthreshold region, the circuit conducts a small current and consumes lesser power. In this paper, the dual rail power supply with 0 and 180° phase difference has been used for subthreshold adiabatic logic (SAL). A priority encoder is designed using SAL with dual rail power supply. All the circuit simulations are done using HSPICE simulator at 22 nm PTM technology. In-phase dual supply offers low power consumption, whereas out-phase dual power supply offers an improved noise margin.

In this paper, detailed gate-induced drain leakage (GIDL) mechanism is analyzed in conventional nano-wire. It has been seen that conventional nano-wire suffers from both lateral and transversal band-to-band tunneling. The lateral component tunneling is more severe and active when device is in OFF condition. It is one of the contributors of leakage current in nano-wire transistors. SiO2 as core–shell material is proposed for effectively controlling both lateral and transverse band-to-band tunneling (BTBT) current. The impact of core–shell on short channel parameters like Ion, Ioff, Ion/Ioff ratio, subthreshold swing and drain-induced barrier lowering (DIBL) are also analyzed. From the calibrated simulation, it has been found that the use core–shell significantly reduces Ioff with only a minor reduction in Ion. On increasing core–shell radius, drain-induced barrier lowering (DIBL), Ioff and subthreshold swing are also significantly and almost linearly decreases.

In this chapter, the performance analysis of AlGaN/GaN heterostructure field-effect transistor (AlGaN/GaN HFET) is performed. The AlGaN/GaN HFET provides several merits over Si and AlGaAs/GaAs material devices including higher inversion charge at the heterointerface. The performance analysis of AlGaN/GaN HFET is further extended for different device geometries and parametric variations. This chapter is further extended to derive the voltage transfer characteristics of the invertor circuit, highlighting the utility of the model.

It is known that due to several current injection mechanisms, tunnel FETs can attain a subthreshold swing less than 60 mV/dec at normal temperature, which makes it alternative for MOSFETs, particularly in low power applications. This work investigates the electrical and analog performance of dual metal double gate hetero dielectric source pocket TFETs in contrast to dual metal double gate high-k dielectric source pocket TFETs. Numerical calculations were carried out to find the characteristics of both the devices. It is observed that for hetero-dielectric structure, the OFF current decreases significantly while having the marginal effect on the ON state current in contrast to double gate high-k dielectric structure.

Present work introduces a Dual Material Gate Extra Insulator Layer (DMG EIL) FinFET for high-performance nanoscale applications. The Dual Material Gate screens the minimum channel potential from the drain voltage variations which reduce the short channel effects (SCEs). The EIL (high-k dielectric) injected in silicon active layer reduces the critical electric field near the drain region which reduces the hot carrier effects. The present device also offers low standby mode current useful for low power applications along with reduced SCEs and hot carrier effects (HCEs). The performance of the proposed device is compared with EIL-FinFET by investigating the output characteristics, electric field, carrier temperature and surface potential. The DMG EIL-FinFET is found to perform better compared to both—conventional FinFET and EIL-FinFET.

In this paper, junctionless quadruple gate (JLQG) MOSFET is analyzed for its temperature-dependent characteristics. The junctionless MOSFET makes manufacturing simpler because it has no p-n junction as the doping of the channel is same as source/drain (S/D) region. Various performance parameters for short channel effects (SCEs), analog/RF, and linearity distortion of the JLQG MOSFET such as drain current (ID), transconductance (gm1), transconductance generation factor (TGF), output conductance (gd), early voltage (VEA), intrinsic gain (gm/gd), cut-off frequency (fT), gain frequency product (GFP), transconductance frequency product (TFP), gain trans-conductance frequency product (GTFP), second order derivative (gm2), third order derivative (gm3), second order voltage intercept point (VIP2), third order voltage intercept point (VIP3), third order input intercept point (IIP3), and third order intermodulation distortion (IMD3) with respect to temperature variations are presented and discussed. The study reveals the different zero-crossing points for temperature-dependent characteristics leading to guidelines for temperature-insensitive designs using JLQG MOSFETs.

In this paper, the proposed configuration is realizing High-Pass, Band-Pass, Low-Pass, and Notch filters simultaneously using a single Differential Difference Current Conveyor (DDCC) as an active block. First, the circuit is implemented using passive resistors and then, in proposed configuration, passive resistors are replaced by active resistors. Proposed configuration occupied less area, provide better noise immunity, and offer programmability at the cost of slight increase in Total Harmonic Distortion. The circuit is simulated in cadence virtuoso 180 nm technology and checked for programmability. It is found that cutoff frequency varied from 13.9 to 28.34 MHz by varying the gate voltage from 1.1 to 1.5 V of the active resistance.

In this paper, we propose and develop an analytical model of a Triple material double gate Tunnel Field Effect Transistor (TM-DG TFET) with hetero-dielectric gate oxide stack comprising of SiO2 and HfO2. The two-dimensional Poisson’s equation has been solved using parabolic-approximation method to model the channel potential and electric field. Analytical model of drain current is developed by integrating the band-to-band tunneling generation rate over the channel thickness (tsi) and shortest tunneling path ($L_{\min }$). A Transconductance model is also developed using this drain current model. The proposed TM-DG TFET also provides better result with reference to input-output characteristics, subthreshold swing, ION/IOFF current ratio and ambipolar effect compared to the dual material double gate (DM-DG) TFET. The analytical model has been validated with the numerical data obtained from commercial TCAD software.

This paper examines a Junctionless quadruple gate (JLQG) MOSFET for analog and linearity distortion performance by numerically calculating transconductance and its higher order derivatives (gm1, gm2and gm3), VIP2, VIP3, IIP3 and IMD3. Influence of various physical device parameters: channel length, height (or width), gate oxide thickness, and channel doping concentration on the linearity distortion parameters are analyzed. From the numerical calculations it has been shown that the desirable characteristics for analog application at a given technology node are obtained for higher values of tSi, tox, and Nd. The present analysis also reveals the guidelines for the design of JLQG MOSFETs with least linearity distortion.

The electronic industry using silicon complementary metal-oxide-semiconductor (CMOS) technology is the leading contender in the market since five decades. Nowadays, silicon CMOS technology is reached to its fundamental limits (physical and geometrical), which is the major roadblock for upcoming technological nodes. As an alternative solution, two-dimensional (2D) materials are in great demand. Graphene is the first 2D material being studied and it is also known as “miracle-material” due to its incredible physical properties. This paper explores the current status of graphene transistor as a potential supplement to the silicon CMOS technology. The absence of an energy bandgap in graphene results in severe shortcomings for logic applications. Various techniques to engineer the bandgap in graphene field-effect transistors (FETs) have been discussed. The use of dopant atoms in graphene and its effect on drain current is studied. The current-voltage characteristics of prototype devices are determined by the first-principles quantum transport calculations. The graphene nanoribbon (GNR) FET and dual-gate (DG) FET structures have been designed and simulated using QuantumWise ATK. A bandgap opening technique in bilayer graphene is proposed and analysed for FET applications as a potential replacement for silicon transistors.

In this work, the impact of temperature is investigated on the electrical characteristics of charge plasma-based doping-less double gate tunnel FET (DL-DG-TFET) with a low bandgap source material i.e., Si0.5Ge0.5. The influence of temperature (from 250 K to 450 K) is analysed on several performance parameters of the device such as bandgap, threshold voltage, SS, switching current ratio, ID-VGS, ID-VDS, gate current. The small change in energy bandgap with temperature reflects that device is minimally dependent on temperature. Temperature impact is significant on the sub-threshold region of transfer characteristics due to SRH recombination and trap-assisted tunnelling current. Insignificant variation of gate current with temperature signifies the better reliability of the device. Further, temperature effect is observed on analog parameters such as cut-off frequency, gate capacitance, trans-conductance, output conductance, power delay product (PDP). The minimal variation of analog parameters with temperature assures application of device in high-temperatures.

In this paper, a quasi-3-D analytical model for Junction-less quadruple MOSFET is presented. The model is developed based on an equivalent number of gates by solving two 2-D Poisson's equations instead of solving complex full 3-D Poisson's equation considering it as two double gate MOSFETs. The model is verified for different channel length, height (or width), oxide thickness, doping concentration, and bias voltages. The presented device is then analysed for digital, analog and RF performance parameters using numerical computations. It has been shown in the paper that the JLQG provides improved gain and SCEs with increase of channel length and decrease in height (or width), oxide thickness and doping concentration whereas a higher cut-off frequency is obtained by decreasing channel length and increase in height (or width), oxide thickness and doping concentration. The doping affects the device performance parameters the most.

In this paper we present electrostatic model of 3D Triple Metal Quadruple Gate (TMQG) MOSFET of rectangular cross-section based on quasi-3D method. The analytical equations for channel potential and characteristic length have been derived by decomposing TMQG into two 2D perpendicular cross-sections (triple metal double gate, TMDG) and the effective characteristic length of TMQG is found using equivalent number of gates (ENG) method. For each of the TMDG, 2D Poisson's equation is solved by parabolic approximation and proper boundary conditions to calculate channel potential. The threshold voltage expression is developed using inversion carrier charge sheet density method. The developed models for channel potential and threshold voltage are validated using numerical simulations of TMQG. The developed model provides the design guidelines for TMQG with improved HCEs and SCEs.

Biochemical markers are agents directly involved in bone growth and remodeling and can be quantitatively evaluated from various biologic fluids. The aim of this study was to assess the changes in the levels of insulin-like growth factor-1 (IGF-1) in serum and urine as a growth maturity indicator and to compare them with the cervical vertebral maturation radiographic stages.The study was conducted with 72 female subjects aged 8 to 20 years. Cervical vertebral maturation stages, and serum and urine IGF-1 levels were recorded for all subjects, and the subjects were equally divided into the 6 cervical vertebral maturation groups. Median values of IGF-1 for each stage of cervical vertebral maturation were calculated and statistically compared with those of the other stages.The levels of serum and urine IGF-1 at stage 4 of cervical vertebral maturation were significantly higher than those from the other stages (P 0.01). Stage 4 corresponded to a mean age of 13.67 years. A significant correlation was observed between serum and urine IGF-1 (P 0.001).Urine IGF-1 follows the growth curve similar to serum IGF-1. Thus, urine IGF-1 may be regarded as a promising noninvasive tool for growth assessment. Further research is necessary to validate these results in a different population and with a larger sample.

This work examines the device behavior of ferroelectric dual material gate all around tunnel field effect transistor (FE-DMGAA-TFET). The ferroelectric material manifests the negative capacitance that increases the drain current by developing an internal positive feedback on the gate terminal. The enhanced electrical characteristics of FE-DMGAA-TFETs is observed in contrast to DMGAA-TFETs. The device performance is examined by varying the thickness of ferroelectric layer and ferroelectric material. It is observed that on increasing the thickness of ferroelectric layer, improved device characteristics are acquired. Moreover, the results depict that FE-DMGAA-TFETs is a better contender for future generation and low power applications.

In this brief, a thorough investigation is performed to analyze the effect of ionizing radiation and temperature on SiGe HBT. The effect of 1 Mrad (Si) gamma total dose is analyzed on device performance parameters: base transit time, cut-off frequency, and maximum oscillation frequency. Also, the effects of both intrinsic and extrinsic reliability issues i.e., radiation rich environment, temperature, and self heating are analyzed on SiGe HBT and SiGe BiCMOS HBT using TCAD.

The two-dimensional electron gas (2DEG) at the heterointerface of AlGaN and GaN is a complicated transcendental function of gate voltage, so an analytical charge control model for AlGaN/GaN high electron mobility transistor (HEMT) is presented accounting for all the three regions of operation (i.e., sub-threshold, moderate, and strong-inversion region). In addition to it, the performance of AlGaN/GaN HEMT is highly dependent on the device geometry. Therefore, to get the optimum performance of the device it is advisable to optimize the parameters governing the device geometry. Accordingly, the output and transfer characteristics, threshold voltage, ON current, OFF current, and transconductance are calculated using numerical computations. The present design is tested to calculate the voltage transfer characteristics (VTC) and transient characteristics of the invertor circuit, after the optimization of the device parameters.

2D Analytical model of the body center potential (BCP) in short channel junctionless Cylindrical Surrounding Gate (JLCSG) MOSFETs is developed using evanescent mode analysis (EMA). This model also incorporates the gate bias dependent inner and outer fringing capacitances due to the gate–source/drain fringing fields. The developed model provides results in good agreement with simulated results for variations of different physical parameters of JLCSG MOSFET viz. gate length, channel radius, doping concentration, and oxide thickness. Using the BCP, an analytical model for the threshold voltage has been derived and validated against results obtained from 3D device simulator.

Background: This study aimed to evaluate the risk markers of Coronary Artery Disease (CAD), so that appropriate lifestyle changes can be instituted early to prevent or delay development of the disease.. Objectives: This study aimed to evaluate the risk markers of CAD based on inflammation and arterial morphology; i.e., high sensitivity C-Reactive Protein (hs-CRP) and carotid artery Intima Media Thickness (IMT), in children of patients with premature CAD.. Patients and Methods: This was a case-control study with predetermined end points. It was conducted on 40 subjects randomly selected from the children of premature CAD patients and 40 age- and sex-matched healthy controls. Blood levels of hs-CRP, lipid profile, and carotid IMT were assessed for all the subjects. The relationship among these parameters was evaluated by univariate and multivariate analyses using the SPSS statistical software, version 22.0 and P < 0.05 was considered as statistically significant.. Results: The mean values of Total Cholesterol (TC, 139.8 ± 24 vs. 111.3 ± 14.7, P < 0.05), Triglycerides (TG, 81.8 ± 15.3 vs. 63.4 ± 10.8, P < 0.05), Low Density Lipoprotein (LDL, 85.2 ± 22.2 vs. 57.5 ± 14.1, P < 0.05), hs-CRP (1.2 ± 0.77 vs. 0.79 ± 0.27, P < 0.05) and carotid artery IMT (0.49 ± 0.09 vs. 0.422 ± 0.03, P < 0.05) were significantly higher in the cases compared to the controls. Also, both LDL/High Density Lipoprotein (HDL) and TC/HDL ratios were significantly higher in the cases compared to the controls. Moreover, a significant positive correlation was found between carotid IMT and hs-CRP.. Conclusions: Children of patients with premature CAD showed a significantly higher incidence of dyslipidemia as well as significantly increased levels of the inflammation marker, hs- CRP, compared to the age- and sex-matched controls. This indicates that atherosclerosis is not only a disease of lipid deposition, but also an inflammatory process. This was further confirmed by demonstration of a significantly raised IMT..

The reliability issues of SiGe HBT are classified as: intrinsic and extrinsic. In this paper the impact of extrinsic reliability issues i.e., radiation and temperature effects on SiGe HBT are analyzed. Accordingly, high frequency behavior and the power capability in SiGeHBTs at cryogenic temperature are also analyzed at high speed, standard, and breakdown.

In this brief, the analysis of high electron mobility transistor is performed. Structure of high electron mobility transistor is designed and simulated to study its characteristics. The device parameters are calculated using simulation technique and it has been verified that the device satisfies all reliability criteria and can be used successfully for commercial circuit applications.

This paper presents the study of Gallium and Aluminum doped Nitrogen terminated zigzag Graphene Nano Ribbon (GNR) FET with high-k dielectric. The GNR FET structure has been designed and simulated using Quantumwise Atomistix Toolkit software package. The presented GNR FET with n-type (Nitrogen doped) electrodes and p-type (Gallium or Aluminum doped) scattering region are simulated and analyzed using Density Functional Theory combined with NEGF formalism and Device Density of States (DDOS). The device shows a negative differential resistance phenomenon which can be controlled by the gate of the zigzag GNR FET. It is found that doping of Gallium and Aluminum in scattering region provides higher drain current, higher I ON / I OFF and I P / I V ratios as compared to that of Boron doped zigzag GNR FET. The potential applications of the device are in logical, high frequency, and memory devices.

Introduction: Vitamin D deficiency has been shown to cause expression of insulin gene resulting in high insulin synthesis and secretion. It also decreases insulin resistance, thus affecting abnormal glucose metabolism and diabetes. Aim: To estimate total 25-hydroxy vitamin D levels in pregnant women and to find its association with Gestational Diabetes Mellitus (GDM). Materials and Methods: Fifty-four antenatal women were randomly enrolled at 24-28 weeks gestation after conforming to exclusion criteria. Serum vitamin D, two-hour 75 grams glucose and postprandial plasma glucose levels were estimated in all women at the time of enrollment. GDM was diagnosed with plasma glucose level >140 mg/dL (Group A). Rest of the women constituted Group B or control group. They were followed up till delivery. Vitamin D status and fetomaternal outcome was evaluated. Results: Hypovitaminosis D was found in 93% of women. There were 38.8% women (n=21) in GDM group compared to 61.2% (n=33) in control group. Vitamin D was significantly low in Group A than B (p-value 0.004). None of the women in Group A had vitamin D levels of 10 ng/mL and above compared to 37.2% in Group B. Severe vitamin D deficient women (levels

Background Determination of skeletal maturation and remaining growth potential is an essential part of treatment planning in orthodontics. The aim of our study was to determine the relationship between IGF-1 levels, IGFBP-3 levels with CVM staging to track the pre pubertal and pubertal growth spurts in female patients in North Indian population. Methods This cross-sectional study was conducted on ninety female subjects in the age group of 8-20 years. Blood samples were collected and centrifuged and serum samples were then analysed by Human IGF-1 and IGFBP-3 enzyme-linked immunosorbent assay kits, specific for IGF-1 and IGFBP-3, respectively. CVM staging on lateral cephalometric radiograph was determined for all patients. Analysis of variance test followed by a post hoc test was used to compare mean IGF-1 and IGFBP-3 corresponding to six stages of cervical vertebrae maturation stages. Linear Pearson’s correlations were performed to determine the trends of IGF-1, IGFBP-3, and its ratio relating to CVM stage. The kappa statistic was used to measure inter and intra examiner reliability. P value

In this paper, analytical and simulation based analysis to verify the inherent properties of SiGe HBT is done. The major performance parameters of SiGe HBT are cut-off freuency f T , maximum oscillation frequency f max , base transit time τ b , current gain β and electron mobility μ n of SiGe base. These performance parameters are responsible for the reliability of SiGe HBT. Temperature is one of the major reliability issues. The impact of temperature variation on these performance parameters is analyzed using Silvaco Atlas Device Simulator along with analytical modeling.

Leakage power is a major issue of concern in Deep Sub-Micron (DSM) and Ultra Deep Sub-micron technology (UDSM) in CMOS circuit design. LECTOR-EP (LECTOR technique with extra PMOS), LECTOR-EN (LECTOR technique with extra NMOS) and Double LECTOR techniques have been proposed in this paper to reduce the leakage. Due to increase in resistance for the path from Vdd to ground, substantial reduction in leakage is obtained in comparison to CMOS circuits. Leakage performance for NAND gate with CMOS, LECTOR and proposed configurations have been performed and compared. The proposed circuits offer improved leakage performance than LECTOR technique. Simulation has been done using Synopsys HSPICE tool for 32 nm technology at 25° C and 110° C.

Junctionless (JL) transistors have recently been reported as strong candidate for the future technology nodes because of ease of manufacturing and improved performance over conventional MOSFETs. In this paper, the analog and RF performances of a JL transistor have been evaluated with metal gate structure having higher work function in the middle with two side gates of lower work function (electrically induced source/drain junctions, EJ). This triple metal gate JLEJ cylindrical surrounding gate (CSG) MOSFET provides better response in terms of intrinsic gain, transconductance generation factor, early voltage, unity gain transition frequency, maximum frequency of oscillation, etc. over single metal junctionless cylindrical surrounding gate (JLSM) transistors. However, the analog and RF performance metrics have been observed to be degraded because of quantum mechanical effects. The ION/IOFF ratio is improved by more than 105 times.

In this paper a comprehensive study of Junctionless Single Metal cylindrical surround gate (JLSM CSG) metal-oxide–semiconductor field-effect transistor (MOSFET) characteristics have been presented and compared with a conventional CSG MOSFET of identical dimensions. The variations of different analog and radio frequency performance parameters have been studied by varying the gate length, channel diameter, and metal gate workfunction using three-dimensional numerical simulations in terms of transconductance, transconductance generation factor, early voltage, unity gain cutoff frequency, maximum frequency of oscillation, etc. The JLSM CSG MOSFETs are found to exhibit superior characteristics compared to the conventional CSG MOSFETs.

Rhizoctonia solani is an important necrotrophic fungal pathogen which causes disease on diverse plant species. It has been classified into 14 genetically distinct anastomosis groups (AGs), however, very little is known about their genomic diversity. AG1-IA causes sheath blight disease in rice and controlling this disease remains a challenge for sustainable rice cultivation. Recently the draft genome sequences of AG1-IA (rice isolate) and AG1-IB (lettuce isolate) had become publicly available. In this study, using comparative genomics, we report identification of 3,942 R. solani genes that are uniquely present in AG1-IA. Many of these genes encode important biological, molecular functions and exhibit dynamic expression during in-planta growth of the pathogen in rice. Based upon sequence similarity with genes that are required for plant and human/zoonotic diseases, we identified several putative virulence/pathogenicity determinants amongst AG1-IA specific genes. While studying the expression of 19 randomly selected genes, we identified three genes highly up-regulated during in-planta growth. The detailed in silico characterization of these genes and extent of their up-regulation in different rice genotypes, having variable degree of disease susceptibility, suggests their importance in rice-Rhizoctonia interactions. In summary, the present study reports identification, functional characterization of AG1-IA specific genes and predicts important virulence determinants that might enable the pathogen to grow inside hostile plant environment. Further characterization of these genes would shed useful insights about the pathogenicity mechanism of AG1-IA on rice.

Important of health in the process of economic and social development and improving the quality of life of our citizens, the Government of India has launched the National Rural Health Mission. District level Household and Facility survey DLHS-3 and DLHS-4 conducted by Ministry of Health and family Welfare of New Delhi and International Institute for Population Science of Mumbai in 2007-08 and 2012-13 for Rajasthan. These surveys provide effective health care to rural population in the state, which has poorer health outcomes and inadequate public health infrastructure and manpower. The primary focus of the mission is the improve access of rural people, especially women and children, to equitable and affordable primary health care. In this paper the infrastructure facility in SHC, PHC and CHC has been increased from 2007-08 to 2012-13 NRHM DLHS is assesses through statistical analysis. Facility survey is carried out for the central and state government in evaluation monitoring and planning strategies.