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All materials and devices tend to degrade with time. For this reason, reliability physics is of great theoretical and practical importance. Reliability investigations generally start with measuring the degradation rate for a material/device under stress and then a modeling of the time-to-failure versus the applied stress. The term stress, as used here, is very general: stress will refer to any external agent (electrical, mechanical, chemical, thermal, electrochemical, etc.) that is capable of producing material/device degradation. Time-to-failure occurs when the amount of degradation reaches some critical threshold level. Since devices often require different levels of degradation to induce failure, time-to-failure becomes statistical in nature and two common failure distributions are discussed: Weibull and Lognormal. Time-to-failure (TF) modeling generally assumes either a power law or exponential stress-dependence with either an Arrhenius or Eyring-like activation energy. From these TF models, acceleration factors can be deduced and these tend to serve as the foundation for accelerated testing. During this presentation, several semiconductor failure mechanisms will be reviewed: Electromigration (EM), Stress Migration (SM), Time-Dependent Dielectric Breakdown (TDDB), Hot-Carrier Injection (HCI), Negative-Biased Temperature Instability (NBTI), Plasma-Induced Damage (PID), Single-Event Upsets (SEU), Surface Inversion, Thermal Cycling Fatigue, and Corrosion. This tutorial should provide the attendee with a solid foundation for a better understanding of the papers presented at the IRPS.

We report on the reliability properties of ferroelectric capacitors and memory arrays embedded in a 130-nm CMOS logic process with 5LM Cu/FSG. Low voltage (

Advanced microelectronics interconnect systems can have metal leads several hundred meters long with minimum metal to metal spacing of

Time-dependent dielectric breakdown (TDDB) of low-k dielectrics is reported for fully integrated carbon-doped silica dielectric (SiOC, keff=2.9) at wafer level over a wide range of area and electric-field test conditions at 105degC. In addition, long-term package level TDDB data were taken at 105degC for over 2 years on integrated comb-serpent test structures. The field acceleration parameter (gamma=4.5 plusmn 0.5 cm/MV) was found to be approximately independent of area (over 4 decades of area) and over a wide range of field (1.5-6.0 MV/cm), respectively. TDDB data, taken over long periods, agree well with predictions based on more rapid wafer-level TDDB testing. The low-k TDDB data suggest that, while the time-to-failure is a strong function of area and field, the time-to-failure physics does not vary greatly for fully integrated SiOC films as both the area and field are scaled. Furthermore, the fact that gamma is approximately constant (independent of area and applied E-field) indicates that silica-based low-k dielectric TDDB follows closely a thermochemical E-model for all areas and fields examined.

Future CMOS technology generations may implement multi-gate architectures according to S. M. Kim et al. (2004), D Ha et al. (2004), S.-Y. Kim et al. (2005), W.-S. Liao et al. (2005), S. Maeda et al. (2004), N. Collaert et al. (2005),and C. Jahan et al. (2005), together with a change from SiO2-based to high-k gate dielectrics and a change from poly-silicon to metal gate. The purpose of this work is to identify the influences of multi-gate architecture and metal gate on gate dielectric reliability and to demonstrate the dielectric reliability trend along the road map towards a CMOS process using triple gate architecture, metal gate, and HfSiON gate dielectric

The shrinking of line-to-line spacing in interconnect systems for advanced IC technology and the use of new lower dielectric constant materials create the need for tools to evaluate the interconnect dielectric reliability. A multi-temperature, dual ramp-rate voltage-ramp to breakdown methodology is presented and used here to extract important dielectric breakdown parameters accurately for minimum spaced metal-lines. It is demonstrated that correction for the true minimum line-to-line spacing distributions become critically important and that the minimum spacing can be extracted electrically and compares favorably to electron microscopy cross sections. The spacing-corrected breakdown field distributions, at various temperatures, for the organo-silicate materials tested, indicated a very low apparent zero-field activation energy (0.14/spl plusmn/0.02 eV) and an apparent field acceleration parameter /spl gamma/ = 4.1/spl plusmn/0.3 cm/MV that has little or no temperature dependence. Constant-voltage time-dependent-dielectric-breakdown (TDDB) measurements were found to agree well with these observations.

Charge trapping in HfSiON and HfO/sub 2/ gate dielectrics was studied using both DC and pulsed I/sub D/-V/sub G/ characterization techniques. The data shows a significant amount of hysteresis in HfO/sub 2/ but negligible instability in HfSiON. Constant voltage stress measurements of HfO/sub 2/ and HfSiON films show that the threshold voltage shift in HfO/sub 2/ films is as much as 10 times higher than that of HfSiON. Further, modeling of the time dependence of the threshold voltage shows that the trap capture cross section responsible for the instability of HfO/sub 2/ films is 10 times higher than the trap capture cross section of HfSiON. Our data indicate that amorphous HfSiON has better electrical stability than HfO/sub 2/.

Electrical instability due to charge trapping in high-k materials is a primary concern for the usefulness of these films in future CMOS devices. This paper reports the effect of charge trapping on the threshold voltage and transistor drive current of devices made with HfSiON gate dielectric. Our results show that the physics of the charge trapping in HfSiON is unique and follows logarithmic dependence with time rather than usual exponential dependence. NMOS devices fabricated with HfSiON films show acceptable electrical stability for 10 years without substantial degradation of either the threshold voltage or the drive current.

Dielectrics with high dielectric constant k will likely be required for future replacement of conventional SiO/sub 2/ gate dielectric. Physical models are needed which describe the reliability tradeoffs associated with the high-k material selection. In this paper we report on a fundamental relationship existing between the dielectric breakdown E/sub bd/ and dielectric constant k. An approximate E/sub bd/ /spl sim/ (k )/sup -1/2/ relation is found and seems to be universal, i.e., the relation holds over nearly two decades of dielectric constant. A physics-based model has been developed to understand this critically important relationship. The good fit of the physical model (with no adjustable parameters) to the experimental data suggests that the local electric field (Lorentz-relation/Mossotti-field) in these high-k materials plays a very important role in the observed E/sub bd/ /spl sim/ (k)/sup -1/2/ behavior. The very high local electric field (in high-k materials) tends to distort/weaken polar molecular-bonds thereby lowering the enthalpy of activation required for bond breakage by standard Boltzmann processes.

Alternate gate-dielectric films are required for future replacement of conventional SiO/sub 2/. Replacement is needed to reduce gate-leakage while still maintaining good reliability and a high-level of transistor performance. One such candidate is HfSiON dielectric film. In this paper we report for the first time, IV and CV characteristics, stability and reliability results for amorphous HfSiON dielectric films scaled below 13 /spl Aring/. Our results show that leakage current through this material is reduced by two orders of magnitude versus an equivalent SiO/sub 2/ film, while the interface and TDDB stability remains good. The positive leakage, stability and reliability results indicate that HfSiON may be a suitable candidate for gate-oxide replacement in CMOS applications where an effective hyper-thin gate-oxide is required for performance reasons and a reduced gate-leakage for low-power applications.

Leakage and breakdown characteristics of low-k dielectrics are becoming increasingly important reliability issues for interconnects as they are scaled to 0.18 um and below. Several of the low-k dielectrics, integrated into a dual-damascene Cu process flow, are quite leaky and have difficulty in meeting a leakage spec of 1E-8 A/cm/sup 2/ at 25/spl deg/C. Time-dependent dielectric breakdown (TDDB) for some of the low-k candidate films is also an issue because of generally low breakdown strengths

The shrinking line-to-line spacing in interconnect systems for advanced integrated circuit technology and the use of lower dielectric constant materials create the need for tools to evaluate the interconnect dielectric reliability. A multi-temperature, dual-ramp-rate voltage-ramp-to-breakdown methodology is presented and used here to extract important dielectric-breakdown parameters accurately for minimum-spaced metal lines. It is demonstrated that correction for the true minimum line-to-line spacing distributions become critically important and that the minimum spacing can be extracted electrically and compares favorably to electron microscopy cross sections. The spacing-corrected breakdown field distributions, at various temperatures, for the organosilicate material tested, indicated a very low apparent zero-field activation energy (0.14±0.02eV) and an apparent field-acceleration parameter γ=4.1±0.3cm∕MV that has little or no temperature dependence. Constant-voltage time-dependent-dielectric-breakdown m...

Analyse de donnees de disruption electrique en fonction du temps concernant des couches minces SiO 2 de 100 A d'epaisseur, en utilisant un modele d'Eyring

Time dependent dielectric breakdown (TDDB) data for 100A of thermally grown SiO2 has been analyzed using an Eyring model based on thermodynamic free energy considerations. The model describes well the following features of the data: (1) an apparent activation energy which is a function of the stressing electric field and (2) a field acceleration parameter that is a function of temperature. Quantitatively, the model suggests the proper field dependence for the activation energy and the observed temperature dependence of the field acceleration in the 100A oxide material. The apparent activation energy is found to decrease from > leV at low field stressing (Eb(50%) - Es > 5 MV/cm) to

The failure kinetics for both titanium silicided and non-silicided contacts are discussed for Al-Si (1%) metallization. The activation energies for accumulation of silicon in silicided and non-silicided contacts as well as the depletion of silicon from non-silicided contacts were found to correspond to diffusion of silicon in aluminum, 0.8 to 0.9 eV. The dependence of the reaction rate on current was found to vary with the level of applied stress. Depletion related leakage failures for TiSi2 contacts proceed at a much slower rate than the depletion of silicon from contacts to silicon and an activation energy of 1.5 eV was observed.

The laser blowing of MoSi2/Poly-n + fuse links is reported. The polycide links were successfully blown under 10K A of PSG (phospho silicate glass used for isolation between the link and the aluminum) at laser power levels comparable to those used for standard poly link vaporization. Also, the size of the crater in the PSG, produced by the expanding gases associated with link vaporization, was found to be less than that for standard poly links. Laser power levels were found which gave both a near unity blowing probability and produced no substrate damage when the link was located on top of 7-10K A of field oxide. The successful blowing of silicide links is very important with respect to the use of both laser redundancy and silicides in VLSI technology.© (1983) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

We report on the reliability properties of a high-density ferroelectric memory based on a 70nm thick MOCVD PZT process technology. We observe that the polycrystalline texture plays an important role in the electrical and reliability properties of these thin films. Data retention loss is primarily due to the imprint effect, which shows a 1.5eV "Time-to-Fail" activation energy. Good correlation is observed between stand alone test capacitors and memory arrays integrated into a 130nm, 5LM, Cu/FSG logic CMOS process. Excellent bit endurance properties are observed on fully packaged memory arrays, with no degradation up to 10/sup 13/ read/write cycles.