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Fanout Wafer Level Packaging (FoWLP) is a very attractive solution for microelectronics applications requiring optimized performance, smaller form factor, and low cost. By utilizing such an approach where system integration is done to multiple chips on a single package frame, the need to ensure much higher levels of process integrity, quality, and reliability becomes absolutely critical, especially if the total product volume lies in the range of tens of millions of units. A single defect type may negate the benefits of such an approach because the cost of losing one FoWLP unit results in the loss of multiple devices. Thus, yield, quality, and reliability optimization using such a package solution is critical for successful large scale manufacturing. In this talk, the issue of defectivity and its impact on quality and reliability on Wafer-Level (WL) devices with regards to the issue of Die Edge Delamination (DED) and Chip Mechanical Integrity (CMI) is discussed. Through this discussion and the resulting solutions found to improve WL quality and reliability, better understanding on how to assess the quality and reliability of a given FoWLP solution for large scale production will be demonstrated.

SRAM physical unclonable function (PUF) provides a low-cost security key to address hardware attacks such as cloning as well as for reliability tracking of ICs in the field. In this work the quality and aging reliability of 28 nm high-K metal gate planar and 16 nm FinFET based SRAMs are discussed in detail with regards to their use in PUF. Data indicates that 16 nm FinFET process has a better SRAM PUF quality without any design modifications compared to the 28 nm planar process. In addition, the aging-induced bit instability is shown to be a reasonably small percentage of the overall bit counts.

Back-end-of-Line (BeoL) Reliability has been a major concern at least since electromigration (EM) was first identified in the late 1960s as a critical failure mechanism within integrated circuits. Typically, reliability concerns arose because simple technology scaling placed larger current density demands on the metallization system. To slow down the erosion of reliability margin with scaling, Cumetallization using Dual-Damascene (DD) integration was introduced around the 180/130nm node. In addition, low-kdielectrics (2.5

Electromigration results have provided clear evidence of a short or “Blech” length effect in dual- damascene, Cu/oxide, multilinked interconnects. The test structure incorporates a repeated chain of Blech-type line elements and is amenable to failure analysis tools such as focused ion beam imaging. This large interconnect ensemble provides a statistical representation of electromigrationinduced damage in the regime where steady-state interconnect stress is manifest. Statistical analysis yields a critical length of 90 μm for interconnects with line width 0.5 μm at j=1.0×106 A/cm2 and T=325 °C.

On April 15-19, 2012, the 50th Annual IEEE International Reliability Physics Symposium was held in Garden Grove, CA, USA, commemorating a significant milestone for IRPS as the preeminent conference in the area of microelectronics reliability. The technical program included 29 invited talks, in addition to 75 contributed talks and 70 posters, and was witnessed by 408 attendees. Unique to this conference, all prior 49 years of symposium materials were shared with the attendees in a newly digitized format. The papers at The Symposium showcased a range topics, covering fundamental reliability of transistors, interconnects, back-end dielectrics, and packaging. State-of-the-art developments in reliability of memory devices, circuits (including but not limited to BTI, ESD, and latchup and soft errors), product qualification, failure analysis, process and integration impact on reliability, compound semiconductors, high voltage, and thin-film devices used in commercial, industrial, and harsh or unusual environmental conditions were shown. Applications of reliability assessment pertinent to those found in space, automobiles, renewable energy sources, and medical applications were also highlighted. While it is difficult to properly sample such a wide variety of technical contents, this Special Issue features four extended papers based on the original Symposium submission. In each case, the impact of intrinsic reliability failure mechanism(s) on device or circuit reliability is described, topics that should be of ongoing and lasting interest to the reliability community. An overview of the technical articles is given.

An electromigration study has determined the lifetime characteristics and failure mode of dual-damascene Cu/oxide interconnects at temperatures ranging between 200 and 325 °C at a current density of 1.0 MA/cm2. A novel test structure design is used which incorporates a repeated chain of “Blech-type” line elements. The large interconnect ensemble permits a statistical approach to addressing interconnect reliability issues using typical failure analysis tools such as focused ion beam imaging. The larger sample size of the test structure thus enables efficient identification of “early failure” or extrinsic modes of interconnect failure associated with process development. The analysis so far indicates that two major damage modes are observable: (1) via-voiding and (2) voiding within the damascene trench.

The shrinking line-to-line spacing in interconnect systems for advanced integrated circuit technology and the use of lower dielectric constant materials create the need for tools to evaluate the interconnect dielectric reliability. A multi-temperature, dual-ramp-rate voltage-ramp-to-breakdown methodology is presented and used here to extract important dielectric-breakdown parameters accurately for minimum-spaced metal lines. It is demonstrated that correction for the true minimum line-to-line spacing distributions become critically important and that the minimum spacing can be extracted electrically and compares favorably to electron microscopy cross sections. The spacing-corrected breakdown field distributions, at various temperatures, for the organosilicate material tested, indicated a very low apparent zero-field activation energy (0.14±0.02eV) and an apparent field-acceleration parameter γ=4.1±0.3cm∕MV that has little or no temperature dependence. Constant-voltage time-dependent-dielectric-breakdown m...