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This article investigates the fin- and finger-number dependence of the total ionizing dose (TID) degradation in 16-nm bulk Si FinFETs at ultrahigh doses. n- and p-FinFETs designed with different numbers of fins and fingers are irradiated up to 500 Mrad(SiO2) and then annealed for 24 h at 100 degrees C. The TID responses of nFinFETs are insensitive to the fin number, as dominated by border and interface trap generation in shallow trench isolation (STI) and/or gate oxide. However, pFinFETs show a visible fin-number dependence with worst tolerance of transistors with the smallest number of fins. The fin number dependence may be related to a larger charge trapping in STI located at the opposite lateral sides of the first and last fins. In addition, both n- and p-FinFETs exhibit an almost TID insensitivity to the finger number. During the design of integrated circuits, the TID tolerance of electronic systems can be enhanced by preferably using transistors with a higher number of fins than fingers.

This article deals with the characterization of charge trapping dynamics in a novel 100-nm double-heterojunction AlN/GaN/AlGaN-on-Si radio frequency (RF) HEMT process. In order to study the detrapping mechanisms, we perform the wideband acquisitions of the transient behavior by sweeping the pulsed voltages to cover the entire device operating area. The fast acquisition also enables the characterization of the charge capture behavior, a key aspect for RF performance. From the analysis of the drain current transients, time constants are extracted, showing a fundamental release time constant in the order of 0.1-1 ms, and more than one capture constants, the fastest being in the order of 300 ns. To the best of authors' knowledge, this is the first time that trapping dynamics under large-signal regime are characterized for this type of process.

Made available in DSpace on 2022-04-28T19:44:02Z (GMT). No. of bitstreams: 0 Previous issue date: 2021-08-23 Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES) Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq) — In this work, the influence of the underlap region on the electrical behavior of a SOI-nFinFET transistor has been studied by numerical simulation with the purpose of radiation sensing. The analysis has been performed by evaluating the impact of spacer length, width and spacer oxide material of the underlap region on the On-state current and by studying its sensitivity. The impact of the underlap region on the drain current and, consequently, on the devices’ sensitivity was explained by the analysis of series resistance, the fringing field and electron density. Considering the main impact of radiation in these devices, the study of sensitivity has been also performed taking into consideration the variation of oxide trapped charges den-sity. When applying the transistor to a harsh environment, the underlapped FinFET showed to be a quite respectable radiation sensor, since the results performed with very good sensitiv-ities when using long and narrow spacer oxide with low permit-tivity oxide. With thicker spacer oxide in the underlap region, the charge concentration makes the spreading field high enough to overcome the series resistance effect, which results in a less sensible device. Since underlapped FinFETs have high sensitivity in the On-state current, reaching 200% for SiO2 spacer oxide material and VDS=1V, these devices show to be promising to work as charged based radiation sensor. Two dif-ferent proposals for radiation sensing are presented. Sao Paulo State University (UNESP) Sao Paulo State University (UNESP)

As a reflective display technology, electrowetting displays (EWDs) have the advantages of paper-like display, low power consumption, fast response, and full color, but the aperture ratio of EWDs is seriously affected by oil dispersion and charge trapping. In order to improve the aperture ratio and optimize the display performance of EWDs, a combined pulse driving waveform with rising gradient design was proposed. First, an initial driving voltage was established by the threshold voltage of oil film rupture (Vth). And then, a rising gradient was designed to prevent oil from dispersing. At last, the oil splitting and movement were controlled to achieve the target aperture combined with the pulse waveform. Experimental results showed that the oil dispersion of EWDs can be effectively improved by using the proposed driving waveform, the aperture ratio of EWDs was increased by 3.16%, and the stability was increased by 71.43%.

The radiation response of Al2O3 on silicon substrate under gamma-rays is studied in this article. The atomic layer deposited Al2O3 based metal-oxide-semiconductor structures were irradiated under gamma-ray with the total dose of 1.2 Mrad(Si)/2.5 Mrad(Si)/4 Mrad(Si). The generation, transportation and trapping characteristics of radiation induced charges were studied by using electronic, physical and chemical methods. Firstly, the radiation induced trapped charge density in Al2O3 is up to 1012 cm−2, with the effective trapping efficiency of 7–20% under irradiation. Secondly, the leakage current through Al2O3 changes little with the increase of radiation total dose. Thirdly, oxygen vacancy in Al2O3 and O dangling bonds and Al-Si metallic bonds at Al2O3/Si interface are dominant radiation induced defects in Al2O3/Si system, and the valence band offset between Al2O3 and Si is found to decrease after irradiation. From the results we can see that Al2O3 is radiation resistant from the aspect of leakage current and crystallization characteristics, but the radiation induced charge trapping and new defects in Al2O3/Si structure cannot be ignored. This paper provides a reference for the space application of Al2O3 based MOS devices.

Electrowetting display (EWD) device is a new type of reflective optoelectronic equipment with paper-like display performance. Due to the oil backflow phenomenon, it is difficult for pixels to be maintained a stable aperture ratio, so the grayscale of EWDs cannot be stabilized. To reduce the oil backflow in EWDs, a driving waveform composed of a driving signal and a periodic reset signal was proposed in this paper. A direct current (DC) signal was designed as the driving signal for driving pixels. The aperture ratio of pixels was determined by the amplitude of the DC signal. The periodic reset signal was divided into a charge release phase and a driving recovery phase. During the charge release phase, the driving voltage was abruptly dropped to 0 V for a period to release trapped charges. In the driving recovery phase, the driving voltage was rapidly increased from 0 V to a maximum value. To reach the same grayscale of EWDs, the driving waveform was returned to the driving signal at the end of the driving recovery phase. Experimental results showed that the aperture ratio of EWDs was unchanged when the driving waveform was applied. However, the aperture ratio of pixels was gradually decreased with the conventional driving waveform. It was indicated that the charge trapping effect and the oil backflow phenomenon can be effectively inhibited by the proposed driving waveform. Compared with the conventional driving waveform, the speed of oil backflow was reduced by 90.4%. The results demonstrated that the proposed driving waveform is beneficial for the achievement of stable grayscale in EWDs.

In this paper, we review the operating principles of hydrogen-terminated diamond MESFETs for high power and high frequency applications. Thanks to the transfer of electrons from the diamond valence band to the hydrogen termination a mobile hole channel is formed, leading to p-MOS operation. The resulting transistor shows good static performance, when the low technology readiness level of these devices is taken into account, owing to the excellent properties of diamond as a semiconductor. The dynamic performance is analyzed by means of quick ID-VD and ID-VG measurements carried out during a filling phase in off-state and on-state, and the corresponding recovery is monitored by the same measurements at different ambient temperatures. This measurement procedure allows for the extraction of the emission time constant and for the creation of the Arrhenius plot of the deep level involved, showing an activation energy of 0.30 eV. The short-term reliability of the devices is investigated by means of step-stress experiments in on-state condition. The degradation causes an increase in the on-resistance, a negative shift in the threshold voltage and a decrease in the peak transconductance value. The correlation between the variation in the electrical parameters and in the results of the dynamic characterization suggests that the degradation is caused by an increase in concentration of the aforementioned deep level, taking place both in the region below the gate and in the access region. A reduction in hole transfer efficiency can also be present, taking place at very high stress voltage.

Donor–acceptor-type organic semiconductor molecules are of great interest for potential organic field-effect transistor applications with ambipolar characteristics and non-volatile memory applications. Here, we synthesized an organic semiconductor, PDPPT-TT, and directly utilized it in both field-effect transistor and non-volatile memory applications. As-synthesized PDPPT-TT was simply spin-coated on a substrate for the device fabrications. The PDPPT-TT based field-effect transistor showed ambipolar electrical transfer characteristics. Furthermore, a gold nanoparticle-embedded dielectric layer was used as a charge trapping layer for the non-volatile memory device applications. The non-volatile memory device showed clear memory window formation as applied gate voltage increases, and electrical stability was evaluated by performing retention and cycling tests. In summary, we demonstrate that a donor–acceptor-type organic semiconductor molecule shows great potential for ambipolar field-effect transistors and non-volatile memory device applications as an important class of materials.

On-wafer robustness and short-term reliability of 0.15 μm AlGaN/GaN HEMTs, fabricated on AlGaN buffer with and without a thin AlGaN “spike” layer between channel and buffer layers, have been compared. Results of DC characterization showed that devices with AlGaN “spike” have better subthreshold behaviour, reduced on-resistance and leakage current, together with a slightly lower current and transconductance. Electroluminescence measurements suggested an increase of electric field in the ‘with Spike’ devices. Observed failure modes are the following: (a) during off-state stress, threshold voltage shifts towards more negative values; (b) for semi-on and on-state tests, a non-monotonic threshold voltage instability, which initially becomes negative and then recovers is common to both types of devices; (c) during semi-on and on-state tests, a significant increase of RON occurs, which seems to be faster in devices without spike, despite the lower electric field suggested by EL measurements. Degradation of electrical characteristics has been attributed to the instability of charge on Carbon-related acceptor levels, enhanced by hot-electron effects.

This article investigates the total ionizing dose (TID) degradation mechanisms of 16-nm bulk Si FinFETs at ultrahigh doses. n- and p-FinFETs with several channel lengths are irradiated up to 1 Grad(SiO2) and then annealed for 24 h at 100 degrees C. Irradiated devices show significant degradation in transconductance and OFF-state leakage currents with slight subthreshold stretch-out and negligible threshold voltage shifts. At doses up to 10 Mrad(SiO2), the TID response is dominated by positive trapped charges in the shallow trench isolation (STI). At ultrahigh doses approaching 1 Grad(SiO2), dc static measurements suggest generation of trapped charge at the STI/Si interface and/or at the corner between the STI and the gate dielectric. The TID sensitivity depends on the bias condition and channel length. Halo implantations fortuitously increase the radiation tolerance of short-channel FinFETs due to the increased channel doping caused by the overlap of the source and the drain halos. The worst degradation is found when a high electric field is applied to the gate during irradiation.

Atomic defects in high-k materials affect the performance, reliability, variability, and scaling potential of electronic devices. Their characterization is thus of paramount importance, and methods exploiting electrical measurements are highly demanded. In this work we present a novel method for extracting the defect properties from I-V curve hysteresis measured at low electric field in thick metal-insulator-metal (MIM) stacks. The I-V curve hysteresis allows detecting the defects located near the electrode-insulator interfaces and aligned with the stack Fermi level, and extracting their properties. The defects are profiled cross-correlating the information provided by the low-field current hysteresis and the high-field steady-state current. This technique can be applied to MIM stacks fabricated in Back-End-of-Line for capacitors, embedded memories and thin film transistors.

In this paper, we analyze the threshold voltage stability of beta-Ga2O3 FinFETs for power applications using Al2O3 as gate insulator. In dynamic characterization measurements, when the filling bias condition is moved from off-state to on-state a positive threshold voltage shift is induced, caused by the trapping of electrons in the insulator or at the insulator interface with the semiconductor. The threshold voltage variation was found to be stable in rest condition, but illumination by 280 nm UV light was able to slowly recover the threshold voltage even below its value before the filling condition was applied, suggesting the presence of natively trapped charge into the oxide even in the as-grown device. In order to obtain more information on the role of the external illumination, monochromatic excitation in the range from 1.5 eV to 5 eV was applied to the device before a transfer characteristic measurement. Results show that photon energies lower than 2.2 eV cause a positive threshold voltage shift, caused by charge trapping during the measurement phase and not related to illumination. Photon energies between 2.2 eV and 3.5 eV promote electron detrapping, leading to a partial recovery in the threshold voltage. Finally, energies above 3.5 eV cause an additional charge trapping process. The physical origin of the photon energy difference was investigated by monochromatic light-induced current transients, and a suitable model considering the conduction band discontinuities between the gate metal and the oxide and between the oxide and the semiconductor was developed to explain the experimental data.

As one of the successful approaches to GaAs surface passivation, wet-chemical nitridation is applied here to relate the effect of surface passivation to carrier recombination processes in bulk GaAs. By combining time-resolved photoluminescence and optical pump-THz probe measurements, we found that surface hole trapping dominates the decay of photoluminescence, while photoconductivity dynamics is limited by surface electron trapping. Compared to untreated sample dynamics, the optimized nitridation reduces hole- and electron-trapping rate by at least 2.6 and 3 times, respectively. Our results indicate that under ambient conditions, recovery of the fast hole trapping due to the oxide regrowth at the deoxidized GaAs surface takes tens of hours, while it is effectively inhibited by surface nitridation. Our study demonstrates that surface nitridation stabilizes the GaAs surface via reduction of both electron- and hole-trapping rates, which results in chemical and electronical passivation of the bulk GaAs surface.

Gallium oxide (Ga2O3) is an emerging material for power electronics. The final penetration in the market is limited by several issues, including a stable and effective isolation between different devices and between different regions of the same device. In this work, we analyze lateral and vertical isolation structures, obtained by Mg implantation and annealing at 1000°C in Halide Vapor Phase Epitaxy β-Ga2O3. By means of repeated current-voltage characterization, it is possible to detect a severe current collapse, which can be completely recovered by white light illumination. When a constant bias is applied, the current collapse increases in magnitude at higher bias, showing a stronger filling of the deep levels. The transients closely follow the stretched-exponential model, an indication that the charge trapping is originated by extended defects, mini-bands or surface states. From the recovery transients carried out at various temperatures, it is possible to extrapolate a dominant thermal activation energy of 0.34 eV. The results of the recovery transients under monochromatic illumination show gradual variation in a broad energy range, consistent with the presence of extended defects. Temperature-dependent current-voltage characterization highlights the good performance of the bulk isolation and the presence of a significant surface leakage. Long-term stability tests show that the lateral structure is able to withstand a higher voltage level before catastrophic failure, but is less stable and is affected by a time-dependent degradation process. Charge trapping at the surface may act as a field-limiting element and partially explain the experimental findings.

Charge trapping is a long-standing problem in electrowetting on dielectric, causing reliability reduction and restricting its practical applications. Although this phenomenon is investigated macroscopically, the microscopic investigations are still lacking. In this work, the trapped charges are proven to be localized at the three-phase contact line (TPCL) region by using three detecting methods-local contact angle measurements, electrowetting (EW) probe, and Kelvin probe force microscopy. Moreover, it is demonstrated that this EW-assisted charge injection (EWCI) process can be utilized as a simple and low-cost method to deposit charges on fluoropolymer surfaces. Charge densities near the TPCL up to 0.46 mC m-2 and line widths of the deposited charge ranging from 20 to 300 µm are achieved by the proposed EWCI method. Particularly, negative charge densities do not degrade even after a "harsh" testing with a water droplet on top of the sample surfaces for 12 h, as well as after being treated by water vapor for 3 h. These findings provide an approach for applications which desire stable and controllable surface charges.

We fabricated the transparent non-volatile memory (NVM) of a bottom gate thin film transistor (TFT) for the integrated logic devices of display applications. The NVM TFT utilized indium&ndash, tin&ndash, zinc&ndash, oxide (ITZO) as an active channel layer and multi-oxide structure of SiO2 (blocking layer)/Si-rich SiOX (charge trapping layer)/SiOXNY (tunneling layer) as a gate insulator. The insulators were deposited using inductive coupled plasma chemical vapor deposition, and during the deposition, the trap states of the Si-rich SiOx charge trapping layer could be controlled to widen the memory window with the gas ratio (GR) of SiH4:N2O, which was confirmed by fourier transform infrared spectroscopy (FT-IR). We fabricated the metal&ndash, insulator&ndash, silicon (MIS) capacitors of the insulator structures on n-type Si substrate and demonstrated that the hysteresis capacitive curves of the MIS capacitors were a function of sweep voltage and trap density (or GR). At the GR6 (SiH4:N2O = 30:5), the MIS capacitor exhibited the widest memory window, the flat band voltage (&Delta, VFB) shifts of 4.45 V was obtained at the sweep voltage of &plusmn, 11 V for 10 s, and it was expected to maintain ~71% of the initial value after 10 years. Using the Si-rich SiOX charge trapping layer deposited at the GR6 condition, we fabricated a bottom gate ITZO NVM TFT showing excellent drain current to gate voltage transfer characteristics. The field-effect mobility of 27.2 cm2/Vs, threshold voltage of 0.15 V, subthreshold swing of 0.17 V/dec, and on/off current ratio of 7.57 &times, 107 were obtained at the initial sweep of the devices. As an NVM, &Delta, VFB was shifted by 2.08 V in the programing mode with a positive gate voltage pulse of 11 V and 1 &mu, s. The &Delta, VFB was returned to the pristine condition with a negative voltage pulse of &minus, 1 V and 1 &mu, s under a 400&ndash, 700 nm light illumination of ~10 mWcm&minus, 2 in erasing mode, when the light excites the electrons to escape from the charge trapping layer. Using this operation condition, ~90% (1.87 V) of initial &Delta, VFB (2.08 V) was expected to be retained over 10 years. The developed transparent NVM using Si-rich SiOx and ITZO can be a promising candidate for future display devices integrating logic devices on panels.

A hydrogenated amorphous silicon thin-film transistor with an engineered charge-trapping interface between the gate dielectric and the channel layer is fabricated to realize non-volatile memory. The memory devices possessed a large memory window and good endurance with an estimated 5-year lifetime. The charge retention lifetime under persistent read bias conditions was found to be ~50% less compared to floating conditions. Measured results indicate the importance of continuous read cycles for estimating the device lifetime and the need for a larger memory window to extend memory operation lifetime.

We present a detailed characterization and modeling of the charge persistence effect that impacts InGaAs/InP single-photon avalanche diodes. Such phenomenon is due to holes that pile-up at the heterointerface outside the active area and has two main consequences: 1) higher noise (equivalent to higher dark count rate), not decreasing as expected at low temperature and 2) possible distortion of the acquired time-resolved waveforms (due to such signal-correlated noise). We propose a model that describes: 1) the generation of holes at the detector periphery in the InGaAs layer; 2) their accumulation at the heterointerface; 3) their subsequent diffusion toward the active area within the InGaAs layer; and 4) their resulting drift to the high field depleted InP region, where the unwelcome spurious avalanche is eventually triggered. We support our model by detailed experimental measurements and simulations. Finally, we propose simple approaches for designing detectors less sensitive to this type of noise.

In this paper, the total ionizing dose (TID) response of a commercial 28-nm high-k CMOS technology at ultrahigh doses is measured and discussed. The degradation of pMOSFETs depends not only on the channel width but also on the channel length. Short-channel pMOSFETs exhibit a higher TID tolerance compared to long ones. We attributed this effect to the presence of the halo implantations. For short-channel lengths, the drain halo can overlap the source one, increasing the average bulk doping along the channel. The higher bulk doping attenuates the radiation-induced degradation, improving the TID tolerance of short-channel transistors. The results are finally compared and discussed through technology computer-aided design simulations.

International audience; Nowadays, the study of physical mechanisms that occur during Flash memory cell life is mandatory when reaching the 40nm and beyond nodes in terms of reliability. In this paper we carry out a complete experimental method to extract the floating gate potential evolution during the cell aging. The dynamic current consumption during a Channel Hot Electron operation for a NOR Flash is a proper quantitative marker of the cell degradation. Here both drain and bulk currents are measured and monitored throughout the endurance tests. We coupled these characteristics with quasi-static measurements to correlate the cell degradation with an equivalent transistor. The final goal is to be able to split the physical effects of repetitive hot carrier and Fowler-Nordheim operations, typical of Flash memories, to extract the electrical parameters evolution on a simple equivalent transistor.

The purpose of this paper is to show that the charge induced by radiation in a dielectric on which a sigma–delta control of dielectric charge is implemented, can be seen as a disturbance in a sliding mode controller. Preliminary experimental results are presented in which a MEMS device is irradiated with X-rays, while the dielectric charge control is continuously being monitored. The charge induced by radiation generates a change in the control bitstream, which is associated with the presence of an external disturbance on the governing control equations.

Long-term degradation of MOS devices has to be avoided in different harsh irradiated environments, especially for aerospace or military applications. In this paper, an overview of the irradiation experiments recently performed on 4H-SiC MOSFETs having an oxynitrided gate oxide is given, with a special focus on the threshold voltage and the effective channel mobility drifts. The general mechanisms taking place during irradiation and post-annealing treatments are described. Finally, new open issues recently observed by performing the temperature measurement on irradiated MOSFETs will be introduced and discussed.

GaN-based transistors are promising devices for power switching applications, but their unique properties require careful design of the circuit in order to achieve the best performance and reliability. The first part will focus on the characterisation of deep-level effects in enhancement- and depletion-mode HEMTs, which limit the performance of the transistor. Threshold voltage instabilities in MIS-HEMT structures, caused by charge trapping under the gate, and their dependence on SiN acting as the gate dielectric will be reviewed. ON-resistance increase, caused by charge trapping in the gate-drain access region, will then be discussed in normally off gate injection transistors, as well as the effect of the switching frequency on the trapping-de-trapping equilibrium condition. The second part of the paper will discuss possible failure modes related to operating conditions, starting with the oxidation of the surface and the inverse piezoelectric effect at high gate-drain voltage. To have a complete picture of high-field effects, the gate dielectric and passivation robustness will be investigated. Time-dependent degradation will then be analysed in both gate reverse and forward-bias conditions. Finally, failures related to off-state stress and to power dissipation and electric field during an ESD event in AlGaN/GaN-HEMTs will be discussed.

The manipulation of matter at the nanoscale enables the generation of properties in a material that would otherwise be challenging or impossible to realize in the bulk state. Here, we demonstrate growth of zirconia nano-islands using atomic layer deposition on different substrate terminations. Transmission electron microscopy and Raman measurements indicate that the nano-islands consist of nano-crystallites of the cubic-crystalline phase, which results in a higher dielectric constant (κ ∼ 35) than the amorphous phase case (κ ∼ 20). X-ray photoelectron spectroscopy measurements show that a deep quantum well is formed in the Al2O3/ZrO2/Al2O3 system, which is substantially different to that in the bulk state of zirconia and is more favorable for memory application. Finally, a memory device with a ZrO2 nano-island charge-trapping layer is fabricated, and a wide memory window of 4.5 V is obtained at a low programming voltage of 5 V due to the large dielectric constant of the islands in addition to excellent endurance and retention characteristics.

Solution-processed semiconductors such as conjugated polymers have great potential in large-area electronics. While extremely appealing due to their low-temperature and high-throughput deposition methods, their integration in high-performance circuits has been difficult. An important remaining challenge is the achievement of low-voltage circuit operation. The present study focuses on state-of-the-art polymer thin-film transistors based on poly(indacenodithiophene-benzothiadiazole) and shows that the general paradigm for low-voltage operation via an enhanced gate-to-channel capacitive coupling is unable to deliver high-performance device behavior. The order-of-magnitude longitudinal-field reduction demanded by low-voltage operation plays a fundamental role, enabling bulk trapping and leading to compromised contact properties. A trap-reduction technique based on small molecule additives, however, is capable of overcoming this effect, allowing low-voltage high-mobility operation. This approach is readily applicable to low-voltage circuit integration, as this work exemplifies by demonstrating high-performance analog differential amplifiers operating at a battery-compatible power supply voltage of 5 V with power dissipation of 11 µW, and attaining a voltage gain above 60 dB at a power supply voltage below 8 V. These findings constitute an important milestone in realizing low-voltage polymer transistors for solution-based analog electronics that meets performance and power-dissipation requirements for a range of battery-powered smart-sensing applications.

Silicon nitride thin film dielectrics are used in capacitive radio frequency micro-electromechanical systems (MEMS) switches since they provide a low insertion loss, good isolation, and low return loss. The lifetime of these switches is believed to be adversely affected by charge trapping in the silicon nitride. The goal of this research was to characterize Si 3 N 4 -based MIM (Metal–Insulator–Metal) capacitors to describe the mechanisms responsible for the conduction and trapping behaviour in MEMS switches. The silicon nitride films were deposited by ICP chemical vapour deposition at room temperatures. The upper Si 3 N 4 layer was removed by the reactive ion etching process (RIE) in order to provide contact paths to the bottom electrode. In the near-stoichiometric films, different electrical characterizations were performed to study dependence of the leakage current on different electrical parameters. It was concluded that the Poole–Frenkel mechanism dominated the conduction in the silicon nitride films at high fields.

In this work we analyzed the effect of different stress configurations on p- and n-type organic thin-film-transistors, to emulate the various operating conditions in a real application. Devices showed the largest degradation when they are stressed in the ON condition, because of the uniform charge injection and defect generation in the whole channel area. Charge trapping kinetics and mobility degradation was also strongly dependent on the semiconductor type, suggesting a key-role of the semiconductor on the device reliability.

The 4H-SiC MOSFET electrical response to 180 keV proton radiations at three different fluences has been evaluated. For a certain dose, the devices show an apparent improvement of their electrical characteristics likely due to the N and/or H atoms diffusion inside the oxide layer. This work complete our previous studies on high energy proton irradiation, showing that the 4H-SiC MOSFET is also robust to the low energy proton radiation, when the proton implanted range is located near the MOS interface.

In this work, we present a novel method to reduce the subthreshold swing of field-effect transistors below 60 mV/dec. Through modeling, we directly relate trap charge movement between the gate electrode and the gate dielectric to subthreshold swing reduction. We experimentally investigate the impact of charge exchange between a Cu gate electrode and a 5 nm thick amorphous Al2O3 gate dielectric in an InGaZnO4 thin-film transistor. Positive trap charges are generated inside the gate dielectric while the semiconductor is in accumulation. During the subsequent de-trapping, the subthreshold swing diminishes to a minimum value of 46 mV/dec at room temperature. Furthermore, we relate the charge trapping/de-trapping effects to a negative capacitance behavior of the Cu/Al2O3 metal-insulator structure.

This paper investigates the radiation tolerance of 28-nm bulk ${n}$ and ${p}$ MOSFETs up to 1 Grad of total ionizing dose (TID). The radiation effects on this commercial 28-nm bulk CMOS process demonstrate a strong geometry dependence as a result of the complex interplay of oxide and interface charge trapping relevant to the gate-related dielectrics and the shallow trench isolation. The narrowest/longest channel devices have the most serious performance degradation. In addition, ${n}$ MOSFETs present a limited on-current variation and a significant off-current increase, while ${p}$ MOSFETs show a negligible off-current change and a substantial on-current degradation. The postirradiation annealing annihilates or neutralizes oxide trapped positive charges and tends to partly recover the degraded device performance. To quantify the effects of TID and postirradiation annealing, parameters including the threshold voltage, the free carrier mobility, the subthreshold swing, and the drain-induced barrier lowering are extracted.

This work presents a defect charging mechanism in 5-nm-thick amorphous Al2O3 thin-films fabricated on plastic, which leads to multistate memory effects, and thus the realization of synaptic thin-film transistors (TFTs) for neuromorphic applications. First, the Al2O3 thin-films are characterized in metal–insulator–metal stacks. These devices exhibit ferroelectric-like behavior, which is visible in the small-signal capacitance and the surface charge density. Furthermore, the quantum-mechanical simulation of the current–voltage characteristic leads to a physical model with trap charges close to the anode interface where deep-level traps are identified by fitting the experimentally obtained resonant tunneling peaks. The trap charge lifetime and frequency behavior is evaluated in InGaZnO4 TFTs, where the 5-nm-thick Al2O3 layer is employed as gate dielectric. At an operating voltage as low as ±2 V, a charge trapping retention up to ≈3 h and a discernable ON/OFF read-out with a factor >3 at 2 kHz are achieved. When subjected to a train of gate–source voltage pulses, the TFTs show charge integration properties which emulate facilitating and depressing behaviors of biological synapses. These results indicate that thin low-temperature defect-rich metal-oxide dielectrics may be candidates for low-voltage memory applications and neuromorphic circuits on unconventional substrates.

This paper presents the circuit topology of a second order sigma-delta control of charge trapping for MOS capacitors. With this new topology it is possible to avoid the presence of plateaus that can be found in first-order sigma-delta modulators. Plateaus are unwanted phenomena in which the control is locked for a certain time interval (of unknown duration). In this case the control output is constant and therefore the controlled device is in fact in open-loop configuration. It is shown that the presence of plateaus is avoided in MOS capacitors using the proposed approach.

The purpose of this paper is to show that sigma-delta controllers of dielectric charge can be analyzed using the tools of sliding-mode controllers, in the infinite sampling frequency approximation. This allows to study the dynamics of the hidden state variables related to the charge in the dielectric, as well as the reachability and stability of the control method. Furthermore, it is also possible to explain the response of the control bitstream as a function of the dynamical model of the system. This approach not only provides insight into the dynamics of the charge controllers, understood as hybrid systems, it also simplifies the modeling and simulations of the system.

金沢大学設計製造技術研究所 / 金沢大学理工研究域電子情報通信学系, A thin-film structure comprising Al2O3/Al-rich Al2O3/SiO2 was fabricated on Si substrate. We used radio-frequency magnetron co-sputtering with Al metal plates set on an Al2O3 target to fabricate the Al-rich Al2O 3 thin film, which is used as a charge storage layer for nonvolatile Al2O3 memory. We investigated the charge trapping characteristics of the film. When the applied voltage between the gate and the substrate is increased, the hysteresis window of capacitance-voltage (C-V) characteristics becomes larger, which is caused by the charge trapping in the film. For a fabricated Al-O capacitor structure, we clarified experimentally that the maximum capacitance in the C-V hysteresis agrees well with the series capacitance of insulators and that the minimum capacitance agrees well with the series capacitance of the semiconductor depletion layer and stacked insulator. When the Al content in the Al-rich Al2O3 is increased, a large charge trap density is obtained. When the Al content in the Al-O is changed from 40 to 58%, the charge trap density increases from 0 to 18 × 1018 cm-3, which is 2.6 times larger than that of the trap memory using SiN as the charge storage layer. The device structure would be promising for low-cost nonvolatile memory. © 2011 Elsevier B.V. All rights reserved.

Detection of nitrogen dioxide, NO2, is required to monitor the air-quality for human health and safety. Commercial sensors are typically chemiresistors, however field-effect transistors are being investigated. Although numerous investigations have been reported, the NO2 sensing mechanism is not clear. Here, the detection mechanism using ZnO field-effect transistors is investigated. The current gradually decreases upon NO2 exposure and application of a positive gate bias. The current decrease originates from the trapping of electrons, yielding a shift of the threshold voltage towards the applied gate bias. The shift is observed for extremely low NO2 concentrations down to 10 ppb and can phenomenologically be described by a stretched-exponential time relaxation. NO2 detection has been demonstrated with n-type, p-type, and ambipolar semiconductors. In all cases, the threshold voltage shifts due to gate bias induced electron trapping. The description of the NO2 detection with field-effect transistors is generic for all semiconductors and can be used to improve future NO2 sensors. The mechanism of NO2 detection is investigated using ZnO field-effect transistors. The transistor current gradually decreases upon NO2 exposure. The decrease originates from the trapping of electrons, which causes a shift of the threshold voltage towards the applied gate bias. The shift can be described by a stretched-exponential time relaxation and is observed for extremely low NO2 concentrations. Copyright © 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Pulse behavior of insulated-gate double-field-plate power AlGaN/GaN HEMTs with C-doped buffers showing small current-collapse effects and dynamic RDS,on increase can accurately be reproduced by numerical device simulations that assume the CN-CGa autocompensation model as carbon doping mechanism. Current-collapse effects much larger than experimentally observed are instead predicted by simulations if C doping is accounted by dominant acceptor states. This suggests that buffer growth conditions favoring CN-CGa autocompensation can allow for the fabrication of power AlGaN/GaN HEMTs with reduced current-collapse effects. The drain-source capacitance of these devices is found to be a sensitive function of the C doping model, suggesting that its monitoring can be adopted as a fast technique to assess buffer compensation properties.

The effect of constant voltage stress (CVS) on Pt/La(2)O(3)/n-Ge MOS devices biased at accumulation is investigated and reported. It is found that the stress induced leakage current (SILC) initially increases due to electron charge trapping on pre-existing bulk oxide defects. After 10 s approximately, a clear decay of SILC commences which follows a t(-n) power law, with n lying between 0.56 and 0.75. This decay of SILC is not changed or reversed when the stressing voltage stops for short time intervals. The effect is attributed to the creation of new positively charged defects in the oxide because of the applied stressing voltage, while other mechanism such as dielectric relaxation proposed in the past is proved insufficient to explain the experimental data. Also high frequency capacitance vs. gate voltage (C-V(g)) curves measured under different CVS conditions divulge the creation of defects and charge trapping characteristics of La(2)O(3) preciously. At low CVS exemplify the generation positively charged defects, however at higher CVS charge trapping obeys a model that was previously proposed and is a continuous distribution of traps. (C) 2010 Elsevier Ltd. All rights reserved. Solid-State Electronics

The physical mechanisms underlying RF current- collapse effects in AlGaN-GaN high-electron-mobility transistors are investigated by means of measurements and numerical device simulations. This paper suggests the following conditions: 1) both surface and buffer traps can contribute to RF current collapse through a similar physical mechanism involving capture and emission of electrons tunneling from the gate; 2) surface passivation strongly mitigates RF current collapse by reducing the surface electric field and inhibiting electron injection into traps; 3) for surface-trap densities lower than 9 x 1012 cm-2, surface-potential barriers in the 1-2-eV range can coexist with surface traps having much a shallower energy and, therefore, inducing RF current-collapse effects characterized by relatively short time constants.

Charge-trapping memories such as SONOS and MONOS have attracted considerable attention as promising alternatives for next-generation flash memories due to dielectric layer’s scalability, process simplicity, power economy, operation versatility. Nevertheless, the continued miniaturization of the devices forces an application of high-k dielectrics. In this work high-k stacked dielectric structures based on the combination of Hf-based and SiNx materials were fabricated. Their structural and electrical properties versus deposition conditions are studied by means of FTIR-ATR and high-resolution TEM techniques. All samples demonstrated smooth surface (roughness below 1 nm) and abrupt interfaces between the different stacked layers. No crystallization of Hf-based layers was observed after annealing at 800°C for 30 min, demonstrating their amorphous nature and phase stability upon annealing. Electrical characterization was carried out for all samples through capacitance-voltage (C-V) measurements of MIS capacitors. Uniform C-V characteristics were measured along the samples for all stacks. Besides, significant flat-band hysteresis due to charging of the stacks caused by carrier injection from the substrate was observed for the structures with pure HfO2 layers.

In this work, the influence of elevated temperatures on charge trapping in Si nanoclusters located in oxide layer of MOS structure has been comprehensively studied. The samples with one layer of nanocrystals in the oxide have been studied using the modular data acquisition setup for capacitance-voltage measurements. The memory window formation and memory window retention experimental methods were used with the aim to study the trapping/emission processes inside the dielectric layer of MOS capacitor memory within the defined range of elevated temperatures. The trap activation energy and charge localization were determined from measured temperature dependences of charge retention. The electric field dependence of the activation energy with subsequent charge emission law have been determined.

The overall radiation response to X-ray exposure of metal-oxide-semiconductor (MOS) capacitors, subjected to two different post-deposition-annealing (PDA) processes in N2O or POCl3 atmospheres, was investigated by capacitance-voltage (C-V) analyses. The production rate and saturation density of electrically active defects, different for the two oxides, demonstrated an additional contribution to the defects formation coming from the annealing treatements. The higher susceptibility of the POCl3-annealed oxide respect to the N2O annealed is discussed.

Traps are characterized in AlGaN–GaN HEMTs by means of DLTS techniques and the associated charge/discharge behavior is interpreted with the aid of numerical device simulations. Under specific bias conditions, buffer traps can produce “false” surface-trap signals, i.e. the same type of current-mode DLTS (I-DLTS) or ICTS signals that are generally attributed to surface traps. Clarifying this aspect is important for both reliability testing and device optimization, as it can lead to erroneous identification of the degradation mechanism, thus resulting in wrong correction actions on the technological process.

There is a common need in astroparticle experiments such as direct dark matter detection, 0{\nu}\b{eta}\b{eta} (double beta decay without emission of neutrinos) and Coherent Neutrino Nucleus Scattering experiments for light detectors with a very low energy threshold. By employing the Neganov-Luke Effect, the thermal signal of particle interactions in a semiconductor absorber operated at cryogenic temperatures, can be amplified by drifting the photogenerated electrons and holes in an electric field. This technology is not used in current experiments, in particular because of a reduction of the signal amplitude with time which is due to trapping of the charges within the absorber. We present here the first results of a novel type of Neganov-Luke Effect detector with an electric field configuration designed to improve the charge collection within the semiconductor., Comment: 6 pages, 5 figures, submitted to Journal of Low Temperature Physics

In this work, we demonstrate a non-volatile metal-oxide semiconductor (MOS) memory with Quattro-layer graphene nanoplatelets as charge storage layer with asymmetric Al2O3/HfO2 tunnel oxide and we compare it to the same memory structure with 2.85-nm Si nanoparticles charge trapping layer. The results show that graphene nanoplatelets with Al2O3/HfO2 tunnel oxide allow for larger memory windows at the same operating voltages, enhanced retention, and endurance characteristics. The measurements are further confirmed by plotting the energy band diagram of the structures, calculating the quantum tunneling probabilities, and analyzing the charge transport mechanism. Also, the required program time of the memory with ultra-thin asymmetric Al2O3/HfO2 tunnel oxide with graphene nanoplatelets storage layer is calculated under Fowler-Nordheim tunneling regime and found to be 4.1 ns making it the fastest fully programmed MOS memory due to the observed pure electrons storage in the graphene nanoplatelets. With Si nanoparticles, however, the program time is larger due to the mixed charge storage. The results confirm that band-engineering of both tunnel oxide and charge trapping layer is required to enhance the current non-volatile memory characteristics. Electronic supplementary material The online version of this article (doi:10.1186/s11671-015-0957-5) contains supplementary material, which is available to authorized users.

Combined measurements of charge trapping and electroluminescence intensity as a function of injected charge and current have been carried out with the aim of clarifying the mechanisms of electroluminescence (EL) quenching in Ge-implanted ITO-SiO2-Si light-emitting silicon diodes. Good correlation between the negative charge capture in traps of small effective capture cross-sections (sigmat1 e=1.7x10-19 cm2 and sigmat2 e=4.8x10-20 cm2) located in SiO2, and the quenching of the asymmetrical EL line with a maximum intensity at 400 nm has been observed. Similar correlation between the electron capture in traps with extremely small effective capture cross-section (sigmat3 e=5x10-21 cm2) and the quenching of the EL line at 637 nm has been established. A quantitative model for the EL quenching has been developed, which takes into account the modification of the luminescent centers with subsequent electron capture at the newly generated trap! s. The model shows good agreement between simulation and experimental data. It also demonstrates that small effective capture cross-sections for electron charging during the EL quenching are determined by the probability of the luminescence centers (LCs) being disrupted, and enables one to estimate the Ge concentration associated with the EL at 400 nm.

This letter describes an extensive analysis of the time- and field-dependent trapping processes that occur in GaN-based gate injection transistors exposed to high drain voltage levels. Results indicate that-even if the devices do not suffer from current collapse-continuous exposure to high drain voltages can induce a remarkable increase in the on-resistance (Ron). The increase in Ron can be recovered by leaving the device in rest conditions: Temperature-dependent analysis indicates that the activation energy of the detrapping process is equal to 0.47 eV. By time-resolved electroluminescence characterization, we show that this effect is related to the capture of electrons in the gate-drain access region. Finally, we show that charge emission can be significantly accelerated through the injection of holes from the gate.

A nonlinear multi-bias model oriented to accurately predict the effects of charge-trapping in Gallium Nitride (GaN) HEMTs is proposed. As a case study, we considered a 0.25-µm 8×75-µm GaN HEMT. The model is identified by using CW low-frequency time-domain data and validated through high-frequency vector nonlinear measurements.

Date of Conference: 18-21 Aug. 2014 In this work, the effect of embedding Silicon Nanoparticles (Si-NPs) in ZnO based charge trapping memory devices is studied. Si-NPs are fabricated by laser ablation of a silicon wafer in deionized water followed by sonication and filtration. The active layer of the memory was deposited by Atomic Layer Deposition (ALD) and spin coating technique was used to deliver the Si-NPs across the sample. The nanoparticles provided a good retention of charges (>10 years) in the memory cells and allowed for a large threshold voltage (Vt) shift (3.4 V) at reduced programming voltages (1 V). The addition of ZnO to the charge trapping media enhanced the electric field across the tunnel oxide and allowed for larger memory window at lower operating voltages. © 2014 IEEE.

This paper presents an extensive investigation of the properties of the trap with activation energy equal to 0.6 eV, which has been demonstrated to be responsible for current collapse (CC) in AlGaN/GaN HEMTs. The study was carried out on AlGaN/GaN HEMTs with increasing concentration of iron doping in the buffer. Based on pulsed characterization and drain current transient measurements, we demonstrate that for the samples under investigation: 1) increasing concentrations of Fe-doping in the buffer may induce a strong CC, which is related to the existence of a trap level located 0.63 eV below the conduction band energy and 2) this trap is physically located in the buffer layer, and is not related to the iron atoms but—more likely—to an intrinsic defect whose concentration depends on buffer doping. Moreover, we demonstrate that this level can be filled both under OFF-state conditions (by gate-leakage current) and under ON-state operation (when hot electrons can be injected to the buffer): for these reasons, it can significantly affect the switching properties of AlGaN/GaN HEMTs.

A low power zinc-oxide (ZnO) charge trapping memory with embedded silicon (Si) nanoparticles is demonstrated. The charge trapping layer is formed by spin coating 2 nm silicon nanoparticles between Atomic Layer Deposited ZnO steps. The threshold voltage shift (Lambda V-t) vs. programming voltage is studied with and without the silicon nanoparticles. Applying -1 V for 5 s at the gate of the memory with nanoparticles results in a Lambda V-t of 3.4 V, and the memory window can be up to 8 V with an excellent retention characteristic (> 10 yr). Without nanoparticles, at -1 V programming voltage, the Lambda V-t is negligible. In order to get Lambda V-t of 3.4 V without nanoparticles, programming voltage in excess of 10 V is required. The negative voltage on the gate programs the memory indicating that holes are being trapped in the charge trapping layer. In addition, at 1 V the electric field across the 3.6 nm tunnel oxide is calculated to be 0.36 MV/cm, which is too small for significant tunneling. Moreover, the Lambda V-t vs. electric field across the tunnel oxide shows square root dependence at low fields (E < 1 MV/cm) and a square dependence at higher fields (E > 2.7 MV/cm). This indicates that Poole-Frenkel Effect is the main mechanism for holes emission at low fields and Phonon Assisted Tunneling at higher fields. (C) 2014 AIP Publishing LLC.