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High-Voltage power Integrated Circuits (HVICs) are widely used to realize high-efficiency power conversions (e.g., AC/DC conversion), gate drivers for power devices and LED lighting, and so on. The Bipolar-CMOS-DMOS (BCD) process is proposed to fabricate devices with bipolar, CMOS, and DMOS modes, and thereby realize the single-chip integration of HVICs. The basic integrated technologies of HVICs include High-Voltage (HV) integrated device technology, HV interconnection technology, and isolation technology. The HV integrated device is the core of HVICs. The basic requirements of the HV integrated device are high breakdown voltage, low specific on-resistance, and process compatibility with low-voltage circuits. The REduced SURFace field (RESURF) technology and junction termination technology are developed to optimize the surface field of integration power devices and breakdown voltage. Furthermore, the ENhanced DIelectric layer Field (ENDIF) and REduced BULk Field (REBULF) technologies are proposed to optimize bulk fields. The double/triple RESURF technologies are further developed, and the superjunction concept is introduced to integrated power devices and to reduce the specific on-resistance. This work presents a comprehensive review of these technologies, including the innovation technologies of the authors' group, such as ENDIF and REBULF, substrate termination technology prospective integrated technologies and HVICs in wide band gap semiconductor materials are also discussed.

This article proposes a novel ultralow specific ON-resistance ( ${R}_{ \mathrm{\scriptscriptstyle {ON},sp}}$ ) triple reduced surface field (RESURF) lateral double-diffused MOSFET (LDMOS) with sandwich n-p-n layer. Compared with the conventional triple RESURF LDMOS with n-type top layer (NTTR LDMOS), the new structure is characterized by an additional N-buried layer below the P-buried layer. Due to the introduction of N-buried layer, the concentration of N-top layer will decrease to ensure charge balance, thus making the surface electric field distribution better and the higher additional doping introduced by N-top and N-buried layers can be achieved. The dose and implantation energy of n-p-n layers were simulated and optimized. Furthermore, in order to eliminate the premature avalanche breakdown occurring in the source-centered termination region, substrate termination technology (STT) is applied to avoid the high electric field peaks generated in the curved source region with small curvature radius. But the use of STT makes it easy to breakdown in the transitional region compared with the straight region. Therefore, the transitional region is studied and the crucial parameter $\Delta {L}$ in the layout of transitional region is also optimized. The fabricated device experimentally demonstrated improved performance with low ${R}_{ \mathrm{\scriptscriptstyle {ON},sp}}$ of 78.3 $\text{m}\Omega \cdot $ cm2 and high breakdown voltage (BV) of 795 V, and the experimental ${R}_{ \mathrm{\scriptscriptstyle {ON},sp}}$ is 26.8% lower than that of the conventional triple RESURF LDMOS (CTR LDMOS) and 10% lower than that of the NTTR LDMOS based on ${L}_{d} = 67 \mu \text{m}$ , which can break the silicon limit of CTR and NTTR LDMOS and meet the demand of 700-V high-voltage integrated circuit applications.

Recently, Shu et al. published “Numerical and Experimental Investigation of TID Radiation Effect on the Breakdown Voltage of 400 V SOI NLDMOS.” This short article is an extension of that earlier article. The breakdown voltage of 400-V silicon-on-insulator n-channel laterally diffused metal–oxide semiconductor field-effect transistors with different drift region lengths are examined after exposure to total ionizing dose. The variation observed is analyzed using technology computer-aided design simulation.

A novel Homogenization Field Technology (HOFT) in lateral power devices is proposed and experimentally proved in this letter. By introducing the periodically discrete metal insulator semiconductor (MIS) structure, which realizes periodic equal potential and self-charge balance, the HOFT obtains almost uniform surface and bulk electric field distributions in the voltage sustaining layer. Therefore, the new device harvests both higher breakdown voltage V B and lower specific on-resistance R on,sp than those of the conventional reduced surface field (RESURF) technology in much higher and wider doping dose range. The experiment of the HOFT device realized a V B of 672 V and a R on,sp of 56.7 $\text{m}\Omega ~\cdot $ cm2 under a high doping dose of $5.6\times 10^{{12}}$ cm−2, which represents a reduction of 33.8% when compared with the theoretical value of the triple RESURF technology.

A novel self-modulated superjunction lateral double-diffused MOSFET (SM-SJ LDMOS) is proposed and experimentally realized in this letter. When a SJ is introduced into a lightly doped N-drift region, the 3-D depletion regions appear surrounding the P-pillars. This 3-D junction field effect transistor (JFET) effect decreases the current paths in both N-pillars and N-drift, causing a largely increased specific on-resistance ${R} _{\text {on,sp}}$ especially for the SJ with a narrow cell pitch. To suppress the inherent 3-D JFET effect, the SM-SJ structure is proposed by replacing the P-pillars with a series of P-islands. These P-islands with linearly reduced lengths modulate the surface electric field to increase the breakdown voltage ${V} _{{\text {B}}}$ while the N-drift areas between P-islands weaken the 3-D JFET effect to reduce ${R} _{\text {on,sp}}$ . Compared with the conventional SJ device, the measured ${V} _{\text {B}}$ of the SM-SJ LDMOS is increased by 53.1% from 260 V to 398 V with ${R} _{on,sp}$ reduced by 22.3% from 35.4 $\text{m}\Omega ~\cdot $ cm2 to 27.5 $\text{m}\Omega ~\cdot $ cm2.

In this article, the total ionizing dose (TID) effect is investigated in the 30-V split-gate trench (SGT) Vertical double diffused MOSFET (VDMOS). The complex trench structure, including gate oxide, split-gate oxide, and isolation oxide, is carefully studied to reveal the degradation mechanisms. Due to the multioxidation and annealing processes, the trench structure suffers serious oxide defeats. The analytical result shows a larger trapping efficiency ( ${f}_{{\text {ot}}}$ ) compared to the planar gate technology, leading to significant ${V}_{{\text {th}}}$ shifts and subthreshold leakage. Meanwhile, irradiation-induced trapped charges in the split-gate oxide have a great influence on the electric field profile in bulk, which gives rise to breakdown voltage (BV) degradation. The experimental result shows that BV presents a gradient descent and drops to as low as 14 V at 100 krad(Si). Through TCAD simulation and analytical calculation, these TID responses are evaluated, and three approaches have been proposed for the radiation hardness of SGT VDMOS.

A depletion MOS controlled (DMC) current regulator diode (CRD) based on bipolar carrier transport mechanism is proposed and experimentally demonstrated in this paper. Compared with the conventional CRD based on unipolar junction field effect transistor, DMC CRD features a highly doped p-type substrate. On the one hand, the P+ substrate provides hole injection, which makes the output characteristics of DMC CRD resemble a PIN rectifier when operating in the linear region with a small anode voltage. Accordingly, DMC CRD gets a large slope of output characteristic to realize a lower knee voltage (VK) in comparison to the conventional CRD for a same anode current. On the other hand, the P+ substrate and N-type epitaxial layer can form a reverse PN junction to withstand a high reverse breakdown voltage, which allows DMC CRD to be applied in AC circuit. The initial experimental result demonstrates that a low VK of 1.2 V and a high reverse breakdown voltage (BVR) above 250 V are achieved in a 30-mA-level DMC CRD.

In this work, a high-voltage (HV) junction field effect transistor (JFET) with voltage class extended to 800 V is proposed, which obtains a satisfactory on-state breakdown voltage (ON-BV) performance. For the traditional HV JFET, ON-BV is much lower than OFF-BV, which cannot meet the requirement for the application of high voltage start-up circuit. In pursuit of a high ON-BV and making it close to OFF-BV, a dilute-doped resistance region is introduced in the HV JFET to mitigate space-charge-modulation (SCM) effect without additional mask and area. By appropriately increasing the dose of Deep N-Well (DNW), ON-BV can be further increased without degrading OFF-BV. At last, the proposed JFET obtains a high OFF-BV of 900 V and a high ON-BV of 965 V without sacrificing the competitive current capacity above 0.11 mA/μm. Besides, the mechanism of power loss (P LOSS ) induced by substrate current (I SUB ) and gate current (I Gate ) during charging process is also revealed, which is associated with SCM. Benefit by the mitigation of SCM, I SUB +I Gate is reduced significantly in the proposed structure.

A novel high voltage ultra-thin silicon on insulator (SOI) lateral double diffused metal oxide semiconductor field effect transistor (LDMOS) with a sectional linearly doped drift region is proposed and experimentally realized in this letter. The new device features a sectional linear doping (SLD) in a $0.17~ {\mu }\text{m}$ SOI layer with a source field plate covering the full drift region. Low specific on-resistance ${R} _{\text {on,sp}}$ is obtained by increasing the local doping concentration of the high resistance region. An analytical model is developed to provide the design guidance for the thin SOI devices with the field plate. The experimental results of the SOI SLD-LDMOS demonstrate that the new device shows a high breakdown voltage ${V} _{\text {B}}$ of 960 V with a superior figure of merit (FOM $= {V} _{\text {B}}{^{\text {2}}} / {R} _{\text {on,sp}}$ ) of 5.98 MW/cm2 when comparing with other reported thin SOI devices. Good agreements are observed between the model and the experimental results.

Breakdown voltage (BV) shifting behavior induced by total-ionizing-dose (TID) irradiation is investigated for high-voltage SOI LDMOS, in this letter. The BV increase caused by irradiation is present for the first time, and the degradation mechanism is revealed by modeling and simulation. Irradiation-induced electric field modulation exerts an impact on the competition between the lateral BV and vertical BV and results in BV shifting. The dielectric field is enhanced by irradiation-induced positive oxide trapped charges in the BOX layer, which is responsible for the BV increasing after irradiation. A TID radiation hardening approach is proposed so that the lateral BV is required to be properly higher than vertical BV instead of pursuing equality.

The minimum specific ON-resistance $\text{R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ of the semisuperjunction (semi-SJ) device is realized in this paper. Based on the similar SJ optimization method in our previous works, the minimum $\text{R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ of the semi-SJ is searched by optimizing both the semi-SJ and the N-buffer regions. The proposed design formulas give the optimized doping concentration $\text{N}_{\textsf {SJ}}$ of the semi-SJ region, doping concentration $\text{N}_{\textsf {B}}$ , and length $\text{L}_{\textsf {B}}$ of the N-buffer region, respectively. As examples, 1000- and 1500-V semi-SJ devices are designed with the formulas. The calculated results are in a good agreement with the simulations. The comparisons between the simulations and the existing experiments demonstrate that the optimization in this paper realizes lower $\text{R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ under the same breakdown voltage $\text{V}_{\textsf {B}}$ even with a shorter SJ length.

SiC MOSFET with three-section edge termination is investigated in this paper. The edge termination for SiC MOSFET is divided into three sections with different field limited rings and the space between rings, which benefits to achieve uniform electric field and high breakdown voltage (BV). The degradation mechanism of BV and on-resistance during high temperature reverse bias (HTRB) and high temperature gate bias (HTGB) experiment are revealed. For HTRB, positive oxide trapped charge generation on SiC/SiO2 surface enhances the electric field peak at breakdown point, which is responsible for BV decreasing. For HTGB, negative oxide trapped charge generation on SiC/SiO2 surface is responsible for the increase of threshold voltage and on-resistance.

The distribution of radiation induced positive oxide trapped charges (N ot ) in buried oxide (BOX) with different applied electric fields for high-voltage (HV) SOI LDMOS is investigated. In contrast to the traditional model which depends upon N ot buildup near the interface that the field line points to, the verified experimental results in this work indicated that there are still a non-negligible set of N ot generated in SOI/BOX interface even if the electric field plays a negative role (field line perpendicular to the SOI/BOX interface pointing from the top to the bottom of the BOX). The improved model on BOX damage induced by TID considering this set of N ot and its saturation effect is proposed and adopted in accurate simulated analysis to predict the post-irradiation device behavior. The mechanism of HV SOI LDMOS degradation during irradiation is also revealed. The radiation hardening LDMOS in this work keeps breakdown voltage above 120 V at D=500 krad(Si).

Hot-hole induced burnout phenomenon in a high-voltage triple reduced surface field (RESURF) LDMOS with sandwich N-P-N layer is investigated in this work. The sandwich N-P-N structure is employed in the drift region of LDMOS to obtain a further optimized trade-off between specific on-resistance (R$_{on,sp}$) and breakdown voltage (BV). However, experimental results show that the BV drops in the off-state with a period time of 2.7 s and the device burns out. To solve this problem, the corresponding burnout mechanism is analyzed and its countermeasure is proposed and demonstrated by simulation and experiment. As a result, a competitive performance with a low R$_{on,sp}$ of $32.38 \mathrm{m}\Omega \cdot cm^{2}$ and a high BV of 535 V without burnout is achieved for the triple RESURF LDMOS with sandwich N-P-N layer.

An ultra-low specific on-resistance 700 V lateral double-diffused MOSFET (LDMOS) with a buried super junction (BSJ) layer is proposed. [1–9] Buried P-pillars in the LDMOS can be depleted by neighboring N-pillars, overlying and underlying N-drift regions simultaneously, thus allowing a higher doping concentration. Consequently, the doping concentration of either the N-drift regions or N-pillars, or both, may also be increased therewith to compensate the surplus charges in the P-pillars. Compared with conventional surface super junction (SSJ) LDMOS, in which the super junction layer is implemented at the upper surface of the drift region, and P-pillars can only be depleted by the adjacent N-pillars and the N-drift regions beneath, the proposed novel LDMOS structure may have a lower specific on-resistance (Ron,sp) while maintain the same breakdown voltage (BV). Simulation results indicate that the Ron,sp of the novel structure is only 80.5 mΩ cm2 with a high BV of 750 V, which is reduced by 17% in comparison with the Ron,sp of a conventional SSJ LDMOS.

The global optimization of the balanced symmetric vertical superjunction (VSJ) device is proposed based on the R-well model for the first time to realize the unique minimum specific on-resistance $R_{{\mathrm{\scriptscriptstyle ON},\mathrm {min}}}$ . The R-well model, which is originated from our previous VSJ mode theory, shows the relationship between $R_{{\mathrm{\scriptscriptstyle ON}}}$ and the doping concentration N under the given pillar width W and breakdown voltage $V_{B}$ . The global $R_{{\mathrm{\scriptscriptstyle ON}}}$ optimization is realized to obtain the design formulas of N and the pillar length $L_{d}$ . The calculated results are in good agreement with the simulations. It is demonstrated from the comparisons with the simulations and the existing experiments that the optimization in this paper realizes the unique $R_{{on,\mathrm {min}}}$ with a relationship of $R_{{\mathrm{\scriptscriptstyle ON}}}\propto V_{B}^{1.03}$ . The R-well model is also universal for other $R_{on}$ optimizations.

A novel lateral double-diffused metal–oxide semiconductor (LDMOS) with three-dimensional floating vertical field plate (3-D F-VFP) is proposed in this paper. The 3-D F-VFP LDMOS features a discrete pillar-type VFP array through the N-type drift region and the VFP pillars with the same distance from the source are connected to each other to realize the equal potential. In the off-state, the potential along the drift region are pinned by the series of equal-potential F-VFP rings and a new full-region depletion mode is introduced into the bulk of the device. Therefore, the highly doped drift region is depleted by the 3-D F-VFP, establishing a self-adaptive charge balance inside the drift region. In the on-state, the current flows through the gaps among all the F-VFP pillars, preventing the long current path and reducing the on resistance $\boldsymbol{R}_{\mathbf{on}}$ . A 3-D F-VFP LDMOS is experimentally implemented, which obtains a breakdown voltage $\boldsymbol{V}_{\mathbf{B}}$ of 630 V and a $\boldsymbol{R}_{\mathbf{on}}$ of $344.8\ \mathbf{\Omega}$ compared with 550 V and $722.5\ \mathbf{\Omega}$ of the device without the F-VFP. The measured saturation current of the 3-D F-VFP LDMOS is more than 4.5 times of that of the device without F-VFP.

An ultra-low specific on-resistance (R on,sp) lateral double-diffused metal-oxide-semiconductor transistor (LDMOS) with enhanced dual-gate and partial P-buried layer is proposed and investigated in this paper. On-resistance analytical model for the proposed LDMOS is built to provide an in-depth insight into the relationship between the drift region resistance and the channel region resistance. N-buried layer is introduced under P-well to provide a low-resistance conduction path and reduce the resistance of the channel region significantly. Enhanced dual-gate structure is formed by N-buried layer while avoiding the vertical punch-through breakdown in off-state. Partial P-buried layer with optimized length is adopted under the N-drift region to extend vertical depletion region and relax the electric field peak in off-state, which enhances breakdown voltage (BV) with low drift region resistance. For the LDMOS with enhanced dual-gate and partial P-buried layer, the result shows that R on,sp is 8.5 mΩ·mm2 while BV is 43 V.

A novel triple reduced surface field (RESURF) lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS) with partial linear variable doping (LVD) N-type top (N-top) layer is proposed in this paper. Compared with the conventional triple RESURF LDMOS, a partial LVD N-top layer is introduced in the surface of N-well, providing a low on-resistance conduction path and leading to an optimized surface electric field, which alleviates the inherent tradeoff between the breakdown voltage (BV) and specific on-resistance (Ron,sp). With the n-drift region length of 70 μm, the novel triple RESURF LDMOS obtains a high BV of 847 V and a low Ron,sp of 79 mΩ cm2 which are 76 V higher and 46 mΩ cm2 lower than those of the conventional triple RESURF LDMOS. Therefore, the novel triple RESURF LDMOS can greatly improve the tradeoff between BV and Ron,sp. Furthermore, compared with the other existing technologies in the high BV level, the novel triple RESURF LDMOS can achieve a highest figure of merit (FOM, defined as BV2/Ron,sp) of 9.08 MW/cm2 and the conventional RESURF silicon limits are broken.

The optimization methodology of the minimum specific ON-resistance $R_{\mathrm{\scriptscriptstyle ON},\textrm {min}}$ for the lateral superjunction device is proposed based on the concepts of charge and potential electric fields in this paper. From the $R_{\mathrm{\scriptscriptstyle ON},\textrm {min}}$ method, a new relationship between $R_{\mathrm{\scriptscriptstyle ON}}$ and breakdown voltage $V_{B}$ is developed, and the analytical formulas are obtained to directly give the doping concentration $N$ and the drift length $L_{d}$ . The calculated results, including the 800 and 1600 V examples, are in good agreement with the simulations. The optimized designs are also compared with the existing experimental and simulated data. It is shown that $R_{\mathrm{\scriptscriptstyle ON}}$ from the proposed optimization method is minimum, and the methodology of $R_{\mathrm{\scriptscriptstyle ON},\textrm {min}}$ is universal.

A high-voltage thick layer SOI field p-channel LDMOS (pLDMOS) with multiple field plates based on 11-μm-thick silicon layer and 1-μm-thick buried oxide layer is presented in this paper. The thick gate oxide layer is formed by field oxide process to endure the high voltage between the source and gate electrodes. The field implant (FI) technology is adopted to eliminate channel discontinuity at the bird's beak region. Multiple field plates constructed by polysilicon and metal layer are adopted to modulate electric field distribution of the depleted drift region. The SOI field pLDMOS with off-state breakdown voltage (BV) of −240 V is experimentally realized, which can be widely used for simplifying the design of level shifting.

The back gate (BG) induced breakdown mechanisms for thin layer SOI Field P-channel LDMOS (FPLDMOS) are investigated in this paper. Surface breakdown, bulk breakdown and punch-through breakdown are discussed, revealing that the block capability depends on not drain voltage (Vd), but also BG voltage (VBG). For surface breakdown, the breakdown voltage (BVs) increases linearly with VBG increasing. An expression of BVs on VBG is given, providing a good fitting to measured and simulated results. Bulk breakdown with a low breakdown voltage is attributed to high VBG. VBG induces depletion in n-well, giving rise to punch-through breakdown. A design requirement for the thin layer SOI FPLDMOS is proposed that breakdown voltages for the three breakdown mechanisms are compelled to be higher than the supply voltage of switching IC.

A 700 V dual-buried-layer n-channel lateral double-diffused MOSFET (DB-nLDMOS) based on substrate termination technology (STT) is presented and experimentally demonstrated in this paper. The termination region is well analyzed and designed to avoid the premature avalanche breakdown caused by the curved junction. The 2-D and 3-D numerical simulations have been performed to optimize the three key parameters of $\Delta L_{1,}\Delta L_{2,}$ and $\Delta L_{3}$ which impact on breakdown voltage (BV) greatly in the termination region. The simulation results show that the electric field peak is reduced and premature avalanche breakdown is avoided at the curved abrupt p-well/n-well junction with the STT. The experimental results demonstrate that low $R_{{\mathrm{\scriptscriptstyle ON},\mathrm {sp}}}$ of 105.6 $\text{m}\Omega \cdot {\mathrm{ cm}}^{2}$ based on $L_{d}$ and high BV of 788 V are achieved by the DB-nLDMOS.

A new relationship between the specific ON-resistance $R_{\mathrm{\scriptscriptstyle ON}}$ and breakdown voltage $V_{B}$ for the balanced symmetric superjunction (SJ) device is presented to produce the lowest $R_{\mathrm{\scriptscriptstyle ON}}$ for a given $V_{B}$ . The design formulas, including the doping density NW and the drift length $L_{d}$ , are given for both the nonfull depletion (NFD) and the full depletion SJ devices with an introduction of the normalized $V_{B}$ factor $\eta $ . For the NFD SJ MOSFET, an $R_{\mathrm{\scriptscriptstyle ON}} \propto V_{B}^{1.03}$ relationship is obtained. The analytical results show good agreement with the numerical results.

To realize the minimum specific on-resistance R on, sp of the lateral superjunction (SJ) devices, the low resistance characteristic of the SJ should be adequately used and the adverse influence of substrate-assisted depletion (SAD) effect on the breakdown voltage V B should be eliminated. From our previous equivalent substrate (ES) model, the SAD effect is completely suppressed if the ES is optimized. In this paper, the balanced symmetric SJ satisfying the optimized ES condition is defined as the ES-SJ. Based on the ES-SJ concept, the non-full depletion (NFD) mode of the lateral SJ is proposed and experimentally realized for the first time. In the experiments, the optimized ES is obtained by a linearly doped charge compensation layer (CCL) with a field plate covering the full drift region and the NFD SJ is implemented with a narrow width of 0.8 μm by implanting the SJ region thrice. The measured results exhibit a R on, sp of 30.9 mΩ·cm2 with a V B of 477 V, which obtains a reduction in R on, sp by 67.8% when compared with other SJ devices under the similar V B .

Total-ionizing-dose radiation response for 600V ultra-thin layer SOI LDMOS transistor is investigated. Radiation conduction modulation model is proposed to reveal the degradation mechanism of conduction current and breakdown voltage. Multi-interface irradiation damage cause positive net trapped charge, which reduces on-resistance equivalently and enhance conduction current. Meanwhile, they suppress the depletion in the drift region at off-state and then decrease breakdown voltage. Based on the model, irradiation induced net trapped charge density are extracted to evaluate the irradiation damage in drift region.

The Backgate (BG) effect on specific ON-resistance ( $R_{{{\mathrm{{\scriptscriptstyle ON}},\rm sp}}})$ and breakdown voltage (BV) for the thin layer Silicon On Insulator (SOI) field p-channel lateral diffusion MOS (pLDMOS) are investigated in this paper. BG-induced dual conduction mode for the thin layer SOI field pLDMOS is revealed, which includes drift and accumulation conduction. Hole accumulation layer induced by BG voltage ( $V_{\rm BG})$ provides extra charges, resulting in a $R_{{{\mathrm{{\scriptscriptstyle ON}},{\rm sp}}}}$ reduction. An expression of equivalent $R_{{{\mathrm{{\scriptscriptstyle ON}},{\rm sp}}}}$ is given to describe the dependence of $R_{{{\mathrm{{\scriptscriptstyle ON}},{\rm sp}}}}$ on $V_{\rm BG}$ . Simultaneously, $V_{\rm BG}$ impacts strongly on BV, inducing three breakdown mechanisms: surface breakdown, bulk breakdown, and punchthrough breakdown. For surface breakdown, a positive linear dependence of BVs on $V_{\rm BG}$ is given with consideration to multiple $_{_{}}$ field plates (MFP). BV of −366 V and $R_{{{\mathrm{{\scriptscriptstyle ON}},{\rm sp}}}}$ of $7.5~\Omega \cdot $ mm $^{2}$ for the thin layer SOI field pLDMOS are achieved experimentally at $V_{\rm BG} = -200$ V.

A novel simulation approach for the breakdown characteristics of SOI high-voltage (HV) PMOS in a fixed power supply application is proposed. The different optimized parameters for the SOI HV PMOS can be achieved by the conventional and proposed simulation approaches. A SOI variation of lateral doping (VLD) field PMOS, which is widely used in the level-shift circuit is investigated by the conventional and novel simulation approaches. For the level-shift circuit with power supply of 400 V, the breakdown voltage (BV) of the optimized SOI VLD field PMOS increases from 520 V with the conventional simulation approach to 646 V with the proposed simulation approach. Moreover, the corresponding optimized doping concentration of p-drift region with the proposed approach is higher than that with the conventional approach, thus greatly reducing the specific on-resistance ( R on,sp ). The SOI VLD field PMOS actually has a more robust breakdown voltage and lower R on,sp in the fixed power supply. The BV and R on,sp of SOI HV PMOS can be truly reflected and the effect of reduced bulk field (REBULF) is revealed in the fixed HV power supply by employing the novel simulation approach.

The reduction of breakdown voltage (BV) influenced by high voltage interconnection (HVI) is a key problem in power integrated circuit, which essentially is that the modulation of electric field distribution at the device surface caused by HVI. In this paper, we review the developments of the methods to shield HVI including thick insulating film technology, field reduction layer technology, field plate technology and self-shielding technology. The four kinds of HVI technologies prevent BV degradation from the introduced adverse charge induced by interconnections in different ways. Thick insulting film technology increases the distance between the HVI and surface of silicon. Field reduction layer technology uses additional doping layers with optimized impurity concentration to enhance the depletion of the drift region under HVI. Field plate technology shields the influence of HVI with various field plate structures. Self-shielding technology makes HVI avoid crossing over high voltage junction terminal (HVJT), thus no additional shielding structure is needed. The divided reduced surface field (RESURF) technology solves the leakage current in the self-shielding structure.

This paper proposes a 700 V narrow channel region triple-RESURF (reduced surface field) n-type junction field-effect transistor (NCT-nJFET). Compared to traditional structures, low pinch-off voltage ( V P ) with unobvious drain-induced barrier lowering (DIBL) effect and large saturated current ( I Dsat ) are achieved. This is because p-type buried layer (Pbury) and PWELL are introduced to shape narrow n-type channel in JFET channel region. DIBL sensitivity ( S DIBL ) is firstly introduced in this paper to analyze the DIBL effect of high-voltage long-channel JFET. Ultra-high breakdown voltage is obtained by triple RESURF technology. Experimental results show that proposed NCT-nJFET achieves 24-V V P , 3.5% S DIBL , 2.3-mA I Dsat , 800-V OFF-state breakdown voltage (OFF-BV) and 650-V ON-state breakdown voltage when V GS equals 0 V (ON-BV).

A novel 1200-V ultra-thin partial silicon-on-insulator (PSOI) lateral double-diffusion metal oxide semiconductor (LDMOS) with n-type buried (n-buried) layer (NBL PSOI LDMOS) is proposed in this paper. The new PSOI LDMOS features an n-buried layer underneath the n-type drift (n-drift) region close to the source side, providing a large conduction region for majority carriers and a silicon window to improve self-heating effect (SHE). A combination of uniform and linear variable doping (ULVD) profile is utilized in the n-drift region, which alleviates the inherent tradeoff between specific on-resistance ( R on,sp ) and breakdown voltage (BV). With the n-drift region length of 80 μm, the NBL PSOI LDMOS obtains a high BV of 1243 V which is improved by around 105 V in comparison to the conventional SOI LDMOS with linear variable doping (LVD) profile for the n-drift region (LVD SOI LDMOS). Besides, the 1200-V NBL PSOI LDMOS has a lower maximum temperature ( T max ) of 333 K at a power ( P ) of 1 mW/μm which is reduced by around 61 K. Meanwhile, R on,sp and T max of the NBL PSOI LDMOS are lower than those of the conventional LVD SOI LDMOS for a wide range of BV.

A novel vertical field plate (VFP) lateral device with ultralow specific on-resistance (RON,sp) is proposed in this paper. The VFP surrounded by oxide is inserted in the bulk of the drift region. Compared to the surface local depletion of the conventional lateral field plate (LFP), the depletion layer of the VFP expands to the bulk of the drift region, which enhances the bulk electric field. Therefore, ultralow RON,sp is realized in the VFP device due to high drift-region doping (Nd) and short cell pitch. An analytical FP model is developed to describe the behavior of the VFP, in which the breakdown voltage (BV) and Nd are found to be proportional to the FP factor k. Then the uniform-doped VFP laterally diffused MOSs and the step-doped VFP laterally diffused MOS are proposed. The optimized device exhibits a BV of 945 V and a RON,sp of 34 mΩ·cm2 which are superior to those of similar devices and the silicon limit.

The equivalent substrate (ES) model and the accordant optimized structure for the lateral super junction (LSJ) device are proposed in this paper. The ES, defined as the combination of the depleted substrate under the reverse voltage and the charge compensation layer (CCL) in the substrate, is treated as a whole to analyze the modulation impact of the compensation electric field ΔE on the total electric field of the LSJ. The analytical formulas for the surface electric field profiles of the LSJ are deduced from the 3-D Poisson equation and the Green function. The ES model reveals the essence and the suppression of the substrate-assisted depletion effect in the LSJ, from which the optimized substrate conditions are achieved. The optimized substrate condition allows the LSJ device featuring a similar breakdown voltage to that of the vertical super junction. Then four typical doping concentrations of the CCLs with four different compensation electric field strengths ΔEs are compared. The developed novel device with optimized CCL delivers a breakdown voltage of 301 V, realizing 157% improvement compared with the conventional LSJ with Ld=15 μm, which shows a superior performance to the LSJ devices reported. It is noteworthy that the ES model can also be used to analyze other LSJs.

In this paper, ESD protection devices for power rails in a PDP scan IC are studied. By numerical simulation, current flow distribution of LIGBT under ESD stress is analyzed. The proposed latchup free LIGBT has additional discharge mechanism to optimize the discharge path, and much smaller discharge resistance can be obtained. As demonstrated by TLP test, optimized LIGBT has 33% larger It2 than HV diode, and its Vt2 is only 27 V higher than its breakdown voltage.

NBTI of BOX layer induced degradation for thin layer SOI field p-channel LDMOS is investigated by experiment, modeling and simulation. Decrease in drain current (Id) under high negative BG voltage (VBG) stressing is observed, which is ascribed to the positive fixed oxide charge and interface charge in BOX layer induced by NBTI. The NBTI conduction modulation model is proposed to elevate the positive charge density (ΔQp) generation in the BOX layer. The total on-resistance is enhanced because of hole concentration in the accumulation layer reduced by the positive charges. Simulated Id shift with applying the corresponding ΔQp in the BOX layer shows a good fitting with the measured result. Meanwhile, ΔQp in the BOX layer relaxes the electric field peak at the p-drift/n-well junction on the SOI/BOX interface, which is responsible for breakdown voltage (BV) increasing.

A 200-V SOI p-channel pLDMOS with thick gate oxide layer is presented in this paper. The thick gate oxide layer is formed by field oxide process to endure the high voltage between the source and gate electrodes. The field implant (FI) technology is adopted to eliminate channel discontinuity at the bird's beak region. The influences of key parameters on on-state breakdown voltage (BV ON ) and off-state breakdown voltage (BV off ) of the SOI pLDMOS are discussed. The SOI pLDMOS with BVoff of −240 V is experimentally realized, and is successfully applied to HV driving IC.

A novel high-voltage (HV) thick layer silicon-on-insulator (SOI) field p-channel lateral double-diffused metal-oxide semiconductor (pLDMOS) with single trench isolation is developed for HV switching IC based on 11-µm-thick silicon layer and 1-µm-thick buried oxide layer. The thick gate oxide layer is formed by field oxide process to endure the high voltage between the source and gate electrodes. The deep trench is adopted to realize the compatibility between HV pLDMOS and LV CMOS. The device parameters T, Y for the HV SOI field pLDMOS are optimized to reduce the device size and satisfy the off-state breakdown voltage (BV). The HV SOI field pLDMOS with a BV over 200V is experimentally realized and successfully applied to a 96-bit output driver integrated circuit (IC).

In this paper, the effect of field implantation (FI) on off-and on-state characteristics for thin layer SOI field P-channel LDMOS (FPLDMOS) is investigated. FI effect mechanisms are revealed by modeling, simulating, verifying experimentally. The channel discontinuity gives rise to current step in output curve due to strong electric field and impact ionized generation. Back gate (BG) punch-through breakdown weakens severely block capability. Process parameters for FI technology are optimized to avoid channel discontinuity and BG punch-through breakdown. The rugged thin layer SOI FPLDMOS with channel continuity and punch-through breakdown voltage of −329 V is realized experimentally, and successfully applied in 200-V switching IC.

A junction-isolated triple RESURF (JITR) LDMOS with high breakdown voltage (BV) and low specific on-resistance (R on,sp ) is proposed in this letter. Compared with the conventional triple RESURF (CTR) LDMOS, the new structure features a highly doped n-type top (N-top) layer at the surface of N-well, providing a low on-resistance surface conduction path in the on-state. The experimental result demonstrates that low R on,sp and high BV of above 730 V are achieved by the JITR LDMOS. R on,sp of the JITR LDMOS is about 15%-24.3% lower than that of the CTR LDMOS. The JITR LDMOS with horizontal N-top layer and P-buried layer resembles a super junction (SJ) LDMOS. Compared with the reported SJ LDMOS, the SJ layer of JITR LDMOS is formed in the longitudinal direction instead of the width direction, and the proposed JITR LDMOS exhibits almost the highest BV and high power figure of merit (FOM, defined as BV 2 /R on,sp ) in comparison to the published SJ LDMOS.

A novel ultra-thin partial silicon-on-insulator (PSOI) LDMOS with n-type buried (n-buried) layer (NBL PSOI LDMOS) is proposed. The new PSOI LDMOS features an n-buried layer underneath the n-type drift (n-drift) region close to the source side, providing a large conductivity region for majority carriers to significantly improve the self-heating effect. A combination of uniform and linear variable doping (LVD) profile with highly initial concentration is utilised in the n-drift region, which alleviates the inherent tradeoff between specific on-resistance (R on,sp) and breakdown voltage (BV), as well as achieving low power dissipation. With a 60-µm n-drift region length, the NBL PSOI LDMOS obtains a high BV of 940 V with a low maximum temperature (T max) of 327 K at a power (P) of 1 mW/μm, which is reduced by around 56 K in comparison to the conventional SOI LDMOS using an LVD profile for the n-drift region (LVD SOI LDMOS). Moreover, R on,sp of the NBL PSOI LDMOS is lower than that of the LVD SOI LDMOS for a wide range of BV from 400 to 900 V.

A vertical current regulator diode (CRD) with trench cathode based on double epitaxial layers is proposed and experimentally demonstrated. Double epitaxial layers structure is induced not only to achieve high breakdown voltage (V B ) but also to improve the saturation characteristics. Long-channel is realized by implanting boron after trench etching, which further improves the IV characteristics. Experimental results show that the proposed CRD presents well IV characteristics and a high V B above 200 V. What's more, the CRDs of different regulating current levels are achieved in the smallest device size of 470 × 470 μm2 among all the reported CRDs with the same application voltage for LED lighting.

A novel 300-V high-side thin-layer-SOI field pLDMOS adopting field implant (FI) technology and multiple field plates (MFPs) has been developed. Breakdown mechanisms of back gate (BG) punchthrough and avalanche breakdown for highside thin-layer-SOI field pLDMOS are investigated by setting up an analytic model, simulating, and verifying experimentally. Shallow junction depth of p-field achieved by the proposed FI technology attenuates BG punchthrough effect; premature surface avalanche breakdown can be avoided by using MFPs. High-side field pLDMOS with a breakdown voltage (BV) of 340 V is experimentally realized on a 1.5-μm -thick SOI layer and successfully applied in a 200-V high-voltage switching IC.

An ultralow specific on-resistance (Ron,sp) integrable silicon-on-insulator (SOI) power lateral MOSFET is proposed. The MOSFET features double trenches: an oxide trench in the drift region and a trench gate extended to the buried oxide (BOX) (SOI DT MOSFET). First, the oxide trench causes multiple-directional depletion, which leads to electric field reshaping and an enhanced reduced surface field effect in the SOI layer. The electric field distributions in the SOI and BOX are thus improved. The oxide trench also increases the electric field strength in the x-direction due to the lower permittivity of oxide than that of Si. Both increase breakdown voltage (BV). Second, the trench makes the drift region folded in the y -direction, resulting in reduced cell pitch and Ron,sp. Third, the trench gate extended to the BOX further reduces Ron,sp by widening the vertical conduction area. The BV of the DT MOSFET increases from 91 V of the conventional SOI LDMOS to 233 V at a half-cell pitch of 6.5 μm, and the Ron,sp decreases from 5.1 to 3.3 mΩ·cm2.

Super junction (SJ) concept is attractive for power devices because of its advantage for improving the tradeoff between the breakdown voltage (BV) and the on resistance (R on ). It is an acknowledged wish to apply the SJ concept to LDMOS for the power integrated circuits (PICs). However, the conventional SJ LDMOS is no practical due to the influence of the fabrication process, charge imbalance, and junction termination, etc. This paper introduces the key technologies for the SJ LDMOS based on our researched SJ device named SLOP (Surface Low On-resistance Path) LDMOS, aiming to offer applicable lateral SJ device for the PICs.

Lateral Double Diffusion MOSFET is widely used due to its excellent properties. However, the contradictory between on-resistance and breakdown voltage (BV) is proved to be the technical bottleneck of optimizing power devices. On one hand, technologies such as REduce SURface Filed (RESURF), Field Plate and Variation of Lateral Doping are applied to enhance the breakdown characteristics of power devices. On the other hand, due to the limits of silicon material, to reach a higher breakdown voltage, the on-resistance must be set higher. The proposed structure, comparing with conventional structure, exhibits a higher breakdown voltage property while keeping the on-resistance invariant.

A 300 V thin layer SOI nLDMOS based on reduced surface electric field (RESURF) and multiple field plates (MFP) is proposed in this paper. RESURF principle and MFP technology are adopted to modulate the electric field distribution and improve the breakdown voltage (BV). Device structure parameters are discussed to achieve a trade-off between breakdown voltage and on-resistance. Compared with conventional structures, the achieved 300 V nLDMOS not only owns high BV, but also possesses a simple manufacturing process and a low cost.

A lateral current regulator diode (CRD) with field plates is proposed and experimentally demonstrated. The proposed CRD is based on the junction field-effect transistor (JFET) structure. A cathode field plate is adopted to alleviate the channel-length modulation effect and to improve the saturated I—V characteristics. An anode field plate is induced to achieve a high breakdown voltage VB of the CRD. The influence of the key device parameters on the I—V characteristics of the lateral CRD are discussed. Experimental results show that the proposed CRD presents good I—V characteristics with a high VB about 180 V and a low knee voltage (Vk) below 3 V. Furthermore, the proposed CRD has a negative temperature coefficient. The well characteristic of the proposed CRD makes it a cost-effective solution for light-emitting-diode lighting.

Based on the optimization idea of the electric field from the surface to the bulk, this paper summarizes the basic theory and the two types of analytical optimization methods of the super junction (SJ) device. The essential difference between the SJ and the conventional power MOS structure is: the former is the junction-type voltage sustaining layer with the periodic N/P dopings and the later is the resistance-type voltage sustaining layer with the single conductive type. The positive and negative charges satisfying the charge balance are introduced into the SJ voltage sustaining layer, which causes the two-dimensional electric field to realize the optimization from the surface to the bulk. The paper gives the concepts of the charge and potential electric fields, analyzes the non-full depletion and full depletion modes, introduces the mechanism of the transient process and forward biased safe operating area, discusses the equivalent substrate model and the optimized substrate conditions. Finally, the minimum specific on-resistance R on,min optimization methodology is proposed to give the R on,min for a given breakdown voltage V B. R on of the SJ is decreased significantly compared to that of the conventional power MOS with the same V B. The R on -V B relationship changes from the R on∝ V B2.5 to V B1.32 even V B1.03, leading to the SJ as the “milestone in high voltage power MOS device”

An analytical model for a novel triple reduced surface field (RESURF) silicon-on-insulator (SOI) lateral double-diffused metal–oxide–semiconductor (LDMOS) field effect transistor with n-type top (N-top) layer, which can obtain a low on-state resistance, is proposed in this paper. The analytical model for surface potential and electric field distributions of the novel triple RESURF SOI LDMOS is presented by solving the two-dimensional (2D) Poisson's equation, which can also be applied to single, double and conventional triple RESURF SOI structures. The breakdown voltage (BV) is formulized to quantify the breakdown characteristic. Besides, the optimal integrated charge of N-top layer (Qntop) is derived, which can give guidance for doping the N-top layer. All the analytical results are well verified by numerical simulation results, showing the validity of the presented model. Hence, the proposed model can be a good tool for the device designers to provide accurate first-order design schemes and physical insights into the high voltage triple RESURF SOI device with N-top layer.

Based on 11-μm-thick silicon layer and 1-μm-thick buried oxide layer, a novel high-voltage thick layer SOI technology has been developed for driving plasma display panels (PDP). HV pLDMOS, nLDMOS, nLIGBT and LV CMOS are compatible with deep trench isolation. The length T, Y for HV pLDMOS and TD for HV nLDMOS are optimized to reduce the device size and satisfy the off-state breakdown voltage simultaneously. Interdigitated N+&P+ and a deep P+ are adopted in the source region of HV nLDMOS and cathode region of HV nLIGBT to suppress parasitic NPN action and gain better on-state characteristics. A PDP scan driver IC using the developed high-voltage thick layer SOI technology shows that the rise and fall times of the output stages are about 17.6 ns and 16.6 ns respectively.