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Noise-shaping (NS) successive approximation register (SAR) analog-to-digital converters (ADCs) using passive loop filters have drawn the increasing attentions owing to their simplicity, low power, zero static current, and PVT robustness. However, prior works show the limited resolution because of two main challenges: the thermal noise and the digital-to-analog converter (DAC) mismatch. This article presents a high-resolution full passive NS SAR ADC. It uses an efficient NS filter architecture that realizes a 4 $\times $ passive gain and the passive summation, significantly reducing the total thermal noise. It also realizes the second-order DAC mismatch error shaping (MES) that is tone-free. A digital prediction is proposed to solve the signal-range loss issue caused by the MES, recovering the ADC input signal range to the full swing. A prototype NS SAR ADC is implemented in 40-nm CMOS process. It measures 90.5-dB signal-to-noise-and-distortion ratio (SNDR) and 94.3-dB dynamic range (DR) over 40-kHz bandwidth without any calibration. It consumes 67.4 $\mu \text{W}$ power from a 1.1-V supply and occupies 0.061 mm2 area. [ABSTRACT FROM AUTHOR]

This article presents an enhanced interstage gain error shaping (GES) technique that adopts a digital error feedback (DEF) method to address the truncation error in the prior implementation, which can extend the interstage gain error tolerance by five times. The proposed DEF technique does not introduce additional errors as it operates purely in the digital domain. This article also proposes a first-order passive quantization noise shaping (NS) technique that reduces the input-pair ratio of the two-input-pair comparator by 2.7 times, thus alleviating the noise penalty caused by using a multiple-input-pair comparator. A prototype analog-to-digital converter (ADC) equipped with the proposed techniques in a 40-nm CMOS technology achieves a 77.1-dB signal-to-noise-and-distortion ratio (SNDR) over 6.25-MHz bandwidth while operating at 100 MS/s and consuming 1.38 mW. It achieves a 173.7-dB Schreier figure of merit (FoM). [ABSTRACT FROM AUTHOR]

This work introduces a second-order voltage-controlled oscillator (VCO)-based continuous-time delta–sigma modulator (CTDSM) that incorporates a distributed-input VCO as the second-stage integrator and quantizer. The distributed-input VCO topology virtually eliminates the VCO’s voltage-to-frequency (V-F) parasitic pole. One of the key ideas of this article is to demonstrate the use of a capacitive- $\pi $ network in the modulator’s loop filter to break the constraint between the size of the modulator’s inner capacitive digital-to-analog converter (DAC) and the factor by which the front-end Gm-C integrator is impedance scaled. This, in turn, helps to significantly reduce both analog and digital powers. The prototype chip has been fabricated in a 40-nm CMOS process. Despite not using any DAC calibration or explicit dynamic element matching (DEM) circuits, the worst case spurious-free dynamic range (SFDR) is −82 dBc across the signal bandwidth. The fabricated CTDSM achieves a 71.8-dB signal-to-noise-and-distortion ratio (SNDR) and a 74.5-dB dynamic range (DR) in a 10-MHz bandwidth at 655 MS/s, yielding an SNDR-based Walden figure of merit (FoM) of 45.6 fJ/step, an SNDR-based Schreier FoM of 167.2 dB, and a DR-based Schreier FoM of 169.9 dB. [ABSTRACT FROM AUTHOR]

This article presents a second-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with a process, voltage, and temperature (PVT)-robust closed-loop dynamic amplifier. The proposed closed-loop dynamic amplifier combines the merits of closed-loop architecture and dynamic operation, realizing robustness, high accuracy, and high energy-efficiency simultaneously. It is embedded in the loop filter of an NS SAR design, enabling the first fully dynamic NS-SAR ADC that realizes sharp noise transfer function (NTF) while not requiring any gain calibration. Fabricated in 40-nm CMOS technology, the prototype ADC achieves an SNDR of 83.8 dB over a bandwidth of 625 kHz while consuming only $107~\mu \text{W}$. It results in an SNDR-based Schreier figure-of-merit (FoM) of 181.5 dB. [ABSTRACT FROM AUTHOR]

This article presents an interstage gain error shaping (GES) technique that can substantially suppress the in-band quantization leakage error caused by the interstage gain error in pipeline analog-to-digital converters (ADCs). It works for both closed-loop and open-loop amplification. It does not require extra clock phases, long convergence time or an interruption of the digitization, incur large power or area overhead, or pose a constraint on the input signal. A prototype ADC equipped with the proposed second-order GES technique in 40-nm CMOS achieves a 75.8-dB signal-to-noiseand-distortion ratio (SNDR) over 12.5-MHz bandwidth while operating at 100 MS/s and consuming 1.54 mW. It achieves 174.9-dB Schreier figure of merit (FoM). The GES-related hardware only occupies less than 2% of the total active area. [ABSTRACT FROM AUTHOR]