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Layered materials held together by weak van der Waals (vdW) interactions are a promising class of materials in the field of nanotechnology. Besides the potential for single layers, stacking of various vdW layers becomes even more promising since unique properties can hence be precisely engineered. The synthesis of stacked vdW layers, however, remains to date, hardly understood. Therefore, in this work, the vdW epitaxy of transition metal dichalcogenides (TMDs) on single-crystalline TMD templates is investigated in depth. It is demonstrated that the role of lattice mismatch is insignificant. More importantly is the role of surface energy, calculated using density functional theory, which plays an essential role in the activation energy for adatom diffusion, hence nucleation density. This in turn correlates with defect density since the stacking sequence in vdW epitaxy is generally poorly controlled. Moreover, the vapor pressure of the transition metal is also found to correlate with adatom diffusion. Consequently, the proposed study enables important and new insight in the vdW epitaxy of multilayer 2D homo-/heterostructures. ispartof: ACS APPLIED MATERIALS & INTERFACES vol:12 issue:24 pages:27508-27517 ispartof: location:United States status: published

Barium titanate (BaTiO3 or BTO) is a perovskite structure material with interesting intrinsic properties, such as spontaneous ferroelectricity or electro-optical behavior, which strongly depend on thin film crystallinity. For such functional oxide systems, the pulsed-laser deposition (PLD) approach is one promising growth technique due to its precise stoichiometry control of the metals composing the perovskite crystal and higher oxygen environment compared to the classically used molecular beam epitaxy (MBE) approach. In this article, we demonstrate a BTO epitaxial layer by PLD onto an Si(001) substrate thanks to a thin pseudomorphic SrTiO3 buffer layer grown by MBE. In our study, the various investigated PLD parameters show strong impacts on the BTO polarization orientation. Hence, adjusting the growth conditions allows control of the polarization orientation, which is crucial for both electronic and optical applications. In addition, lattice parameter changes of BTO layers are investigated using x-ray diffraction and cross-sectional transmission electron microscopy, which evidenced a correlation between mismatch relaxation and oxygen growth pressure. Finally, with the analysis of BTO C– V curves, the polarization direction transition is demonstrated electrically. ispartof: Journal Of Applied Physics vol:128 issue:10 pages:104104-104104 status: published

© 2018 Elsevier B.V. Quantum Dots (QDs) are considered as an efficient building block of many optoelectronic applications, such as semiconductor laser, photodetector, whereby their physical dimension is the key parameter to be controlled. In this work, we have studied experimentally the growth of InAs QDs on InP(0 0 1) substrate by MOVPE and established a theoretical model explaining the observed epitaxial behaviour. In variance with the classical Stranski-Krastanov growth, we show that during the growth there is an intermediate stage whereby although first large 3D islands are formed, an increased density of small QDs is formed concurrent with the shrinkage of the large 3D islands. As a result, the growth can be divided into three regimes: 2D layer growth, large 3D islands growth and QDs growth. To explain this evolution, a thermodynamic model has been developed accounting for the process driven by surface energy, elastic relaxation energy and inter-island interaction energy. It will be shown that the balance between the surface energy and the elastic relaxation energy provides the transition from 2D layer to large 3D islands (around at 3 ML of InAs growth). This model also supports the energetically favourable truncated pyramidal shape for large 3D islands and the spherical cap shape for QDs. We show in this paper that a balance between surface energy, elastic relaxation energy and inter-island elastic interaction explains the volume shrinkage of the early large 3D islands towards the formation of small QDs in high density. ispartof: JOURNAL OF CRYSTAL GROWTH vol:509 pages:133-140 status: published

The three-dimensional carrier confinement in Quantum Dots (QDs) is the key to achieve superior properties (electronic and optical) compared to the Quantum Well (QWL) for optoelectronic applications, such as semiconductor lasers, photodiodes. After the growth of QDs, the encapsulation is the next crucial step to confine carriers in QDs and achieve the targeted wavelength emission. In this work, we have studied the InP capping of Stranski-Krastanov (S-K) grown InAs QDs on InP(0 0 1) substrate by MOVPE. During the encapsulation, the P/As exchange is a vital process which either transforms the QDs into a 2D layer or reduces QDs’ dimensions. This study shows that a control of Phosphorous concentration on the surface during InP capping facilitates to obtain the expected QDs dimension for 1550 nm wavelength. The emitted photoluminescence peak shifts following the preserved average QDs’ dimensions. By combining simulation with optical response we have proved the Phosphorous incorporation into the InAs structure (QDs or 2D layer) during the encapsulation step. As expected, the carrier lifetime reveals the superior quality of the preserved QDs in InP barrier compared to the 2D layer. Finally, the reduction of the non-radiative recombination sources, e.g. dangling bonds, by passivation treatment demonstrates a further increment in carrier lifetime.

Several approaches for growing III–V lasers on silicon were recently demonstrated. Most are not compatible with further integration, however, and rely on thick buffer layers and require special substrates. Recently, we demonstrated a novel approach for growing high quality InP without buffer on standard 001-silicon substrates using a selective growth process compatible with integration. Here we show high quality InGaAs layers can be grown on these InP-templates. High-resolution TEM analysis shows these layers are free of optically active defects. Contrary to InP, the InGaAs material exhibits strong photoluminescence for wavelengths relevant for integration with silicon photonics integrated circuits. Distributed feedback lasers were defined by etching a first order grating in the top surface of the device. Clear laser operation at a single wavelength with strong suppression of side modes was demonstrated. Compared to the previously demonstrated InP lasers 65% threshold reduction is observed. Demonstration ...

Two-dimensional transition metal dichalcogenide (TMD) semiconductors have risen as an important material class for novel nanoelectronic applications. Molybdenum disulfide (MoS2) is the most representative TMD compound due to its superior stability and attractive properties for (opto-) electronic devices. However, the synthesis of single-crystalline and functional MoS2 across large-area substrates remains crucial for its successful integration in semiconductor industry platforms. Therefore, this work focuses on the study of MoS2 epitaxy via two well-established industry-compatible synthesis methods, promising for the large-area and single-crystalline integration of van der Waals (vdW) materials. These methods are molecular beam epitaxy (MBE) and metalorganic vapor phase epitaxy (MOVPE) and have studied MoS2 quasi-vdW heteroepitaxy on reconstructed sapphire substrates and MoS2 vdW homoepitaxy on exfoliated MoS2 flakes. By examining the MoS2 structural properties using diffraction and spectroscopy techniques, the epitaxial relation and crystal quality are assessed, which reveals insights into the prevalence of inter- and intragrain defects such as grain boundaries and sulfur vacancies. The MBE method yields superior epitaxial MoS2 registry on both sapphire and MoS2 surfaces as compared to MOVPE, although inferior defectivity arises from the typical lower MBE growth temperature and chalcogen partial pressure. Moreover, both synthesis methods generate high densities of twinned MoS2 grain boundaries, which hamper defect-free integration. As a result, this challenging integration might become an important bottleneck for industrial TMD-based applications with a low tolerance for material defects.

Stranski-Krastanow (S-K) grown self-assembled quantum dots (QDs) are considered as an efficient active layer for many optoelectronic applications, such as semiconductor laser, photodetector, due to the possibility to confine carriers in three dimensions. Towards the device application, the subsequent growth of an encapsulation layer is a key step to obtain the desired QDs-based heterostructures. In this work, we have studied step-by-step the encapsulation process of S-K grown InAs QDs/InP(0 0 1) by InAlGaAs (lattice matched to InP) in MOVPE. A detailed investigation with Electron Channeling Contrast Imaging (ECCI) and cross-sectional Transmission Electron Microscopy (TEM), indicated that after the InAlGaAs capping the partially relaxed, dome shaped InAs QDs are transformed into fully biaxially strained, truncated pyramids however without introducing any defects in the heterostructure. The study also presents the important role of the capping layer thickness on the QDs photoluminescence efficiency. The gradual change of the surface morphology during the encapsulation process, has been investigated step-by-step in-depth by atomic force microscopy. The morphological changes can be explained by a capping model based on the localized growth rates. We show that two growth steps of Non-uniform capping, where growth rates are different from each other, result in the successful planarization of the InAlGaAs capping without forming any defect.

© 2018 Author(s). We study in this work the growth and fabrication of top-down highly doped n + InAs(Si)/p + GaSb(Si) Esaki tunneling diodes on (001) GaAs substrates. A careful investigation on the highly mismatched GaSb/GaAs growth is first conducted by means of Reflection High-Energy Electron Diffraction (RHEED), Atomic Force Microscopy (AFM), and X-Ray Diffraction (XRD) analyses. These results are expected to pave the way to methods for III-Sb buffer layer's integration with low threading dislocation (TD) densities. A comparison between AFM, XRD, defect revealing by chemical etching and transmission electron microscopy (TEM) is then presented to calculate the precise TD density and its influence on the device structure. In the last part, we report on first operating sub-30 nm III-V vertical NW tunneling devices on (001) commercial GaAs substrates. ispartof: JOURNAL OF APPLIED PHYSICS vol:124 issue:19 status: published

In this paper we review the details and results of the replacement fin process technique used to successfully demonstrate InGaAs based channel devices from FinFets to ultra scaled nanowires on 300 mm Si substrates. For FinFet devices a Mg p-type doping solution was developed to counteract the unintentional n-type doping of the InP buffer layer which resulted in high source-drain leakage. However, the performance of these devices is found to be limited by the Mg doping as the mobility is degraded. By switching to a GAA architecture the problem of source-leakage through the InP buffer is effectively eliminated and best devices with L G = 60 nm have a peak transconductance of 1030 μS/μm with a SS SAT of 125 mV/dec are achieved. A comparison of gate first to gate last processing highlights the importance of using a low thermal budget process to maintain the integrity of the InGaAs/high- k interface. Nanowires with a diameter of 6 nm were demonstrated to show quantization induced immunity to D it resulting in a SS SAT as low as 66 mV/dec for 85 nm L G devices.

Extracting plasmon-induced hot carriers over a metal-semiconductor Schottky barrier enables photodetection below the semiconductor bandgap energy. However, interfacial carrier recombination hinders the efficiency and stability of this process, severely limiting its implementation in telecommunication. This study proposes and demonstrates the use of epitaxially grown lattice-matched SrTiO3 for interfacial passivation of silicon-based plasmonic Schottky devices. The devices are activated by an electrical soft-breakdown of the interfacial SrTiO3 layer, resulting in reproducible rectified Schottky characteristics. The transition to a low resistance state of the SrTiO3 layer boosts the extraction efficiency of hot holes upon resonant plasmonic excitation, giving rise to a two orders of magnitude higher photocurrent compared to devices with a native oxide layer. Photoresponse, tunability, and barrier height studies under reverse biases as high as 100 V present superior stability with the incorporation of the SrTiO3 layer. The investigation paves the way toward plasmon-induced photodetection for practical applications including those under challenging operating conditions.

This chapter deals with the monolithic integration of InGaAs semiconductor on (001)-oriented Si substrate. This starts with a brief introduction to III-V semiconductor epitaxy, the effect of strain, and the relaxation mechanisms. An overview of the different structural defects' families is also included in the section. In a second part, the two most popular III-V growth techniques that are molecular beam epitaxy and metal-organic vapor phase epitaxy are compared. The main challenge in the heterogeneous integration of InGaAs on Si resides in the material mismatch between both semiconductors that results in the high-density generation of crystalline defects. In this chapter, several options such as strain-relaxed buffers, wafer bonding, epitaxial lateral growth, and selective area growth have been considered to reduce the defect density in III-V compounds on Si, which will be reviewed. Finally, a rich literature completes the chapter.

In this work, we report on the growth of pseudomorphic and highly doped InAs(Si)/GaSb(Si) heterostructures on p-type (0 0 1)-oriented GaSb substrate and the fabrication and characterization of n+/p+ Esaki tunneling diodes. We particularly study the influence of the Molecular Beam Epitaxy shutter sequences on the structural and electrical characteristics of InAs(Si)/GaSb(Si) Esaki diodes structures. We use real time Reflection High Electron Diffraction analysis to monitor different interface stoichiometry at the tunneling interface. With Atomic Force Microscopy, X-ray diffraction and Transmission Electron Microscopy analyses, we demonstrate that an “InSb-like” interface leads to a sharp and defect-free interface exhibiting high quality InAs(Si) crystal growth contrary to the “GaAs-like” one. We then prove by means of Secondary Ion Mass Spectroscopy profiles that Si-diffusion at the interface allows the growth of highly Si-doped InAs/GaSb diodes without any III-V material deterioration. Finally, simulations are conducted to explain our electrical results where a high Band to Band Tunneling (BTBT) peak current density of Jp = 8 mA/μm2 is achieved.

Themechanism of widely observed intermixing of wurtzite and zinc-blende crystal structures in InAs nanowire (NW) grown by selective area epitaxy (SAE) is studied. We demonstrate that the crystal structure in InAs NW grown by SAE can be controlled using basic growth parameters, and wurtzitelike InAs NWs are achieved.We link the polytypic InAs NWs SAE to the reconstruction of the growth front (111)B surface. Surface reconstruction study of InAs (111) substrate and the following homoepitaxy experiment suggest that (111) planar defect nucleation is related to the (1 × 1) reconstruction of InAs (111)B surface. In order to reveal it more clearly, a model is presented to correlate growth temperature and arsenic partial pressure with InAs NW crystal structure. This model considers the transition between (1 × 1) and (2 × 2) surface reconstructions in the frame of adatom atoms adsorption/desorption, and the polytypism is thus linked to reconstruction quantitatively. The experimental data fit well with the model, which highly suggests that surface reconstruction plays an important role in the polytypism phenomenon in InAs NWs SAE.https://doi.org/10.1103/PhysRevMaterials.1.074603

In this work, we will review possible technology options for next generation wireless communication. Next to the introduction of specific device architectures and materials, dissimilar from standard Si CMOS, the challenge will lie in the co-integration of these non-Si technologies with CMOS to enable power efficient systems with high performance, in this case high speed and output power, and reduced form factor. Next to monolithic integration, sequential 3D, currently been investigated for LOGIC density scaling, can be one of the enablers, allowing to combine technologies with very different needs at a finer grain and thus higher density than traditional 3D-SOC and 3D-IC technologies.

The relationship between the Threading Dislocation Density (TDD), the generation (τg) and recombination lifetime (τr) in relaxed n-type In.53Ga.47As is investigated for a series of p+n junction diodes, containing an TDD ranging from 105 to 1010 cm-2. The TDs are generated intentionally by lattice-misfit growth on Semi-Insulating (SI) InP and GaAs substrates. The lifetimes have been extracted from diode Current-Voltage (I-V) and Photoluminescence (PL) analysis showing that TDDs affect their values above a density of about 1×107 cm-2 (τg,E~0) and about 1×108 cm-2 (τr and τPL), which can be well-explained by the charged dislocation cylinder model. In addition, a detailed comparison between the results from Deep Level Transient Spectroscopy (DLTS) and from the diode characterization is performed, showing that the responsible G/R center shifts toward mid-gap in In.53Ga.47As and transfers from a native point defect (PD1) to a TD (E2/H1). Finally, the classical concept of generation lifetime and recombination lifetime in terms of dislocations is discussed based on the results.

The increasing scientific and industry interest in 2D MX2 materials within the field of nanotechnology has made the single crystalline integration of large area van der Waals (vdW) layers on commercial substrates an important topic. The c-plane oriented (3D crystal) sapphire surface is believed to be an interesting substrate candidate for this challenging 2D/3D integration. Despite the many attempts that have been made, the yet incomplete understanding of vdW epitaxy still results in synthetic material that shows a crystallinity far too low compared to natural crystals that can be exfoliated onto commercial substrates. Thanks to its atomic control and in situ analysis possibilities, molecular beam epitaxy (MBE) offers a potential solution and an appropriate method to enable a more in-depth understanding of this peculiar 2D/3D hetero-epitaxy. Here, we report on how various sapphire surface reconstructions, that are obtained by thermal annealing of the as-received substrates, influence the vdW epitaxy of the MBE-grown WSe2 monolayers (MLs). The surface chemistry and the interatomic arrangement of the reconstructed sapphire surfaces are shown to control the preferential in-plane epitaxial alignment of the stoichiometric WSe2 crystals. In addition, it is demonstrated that the reconstructions also affect the in-plane lattice parameter and thus the in-plane strain of the 2D vdW-bonded MLs. Hence, the results obtained in this work shine more light on the peculiar concept of vdW epitaxy, especially relevant for 2D materials integration on large-scale 3D crystal commercial substrates.

The observation and interpretation of Frank stacking faults, Shockley stacking faults, Lomer dislocations, and 60 degrees misfit dislocations, which have similar line shapes in the (001) In0.53Ga0.47As crystalline surface, are performed with the electron channeling contrast imaging (ECCI) technique. To minimize the backscattered electron (BSE) contrast that resulted from the surface morphology, a relatively flat region is first selected and compared with an atomic force microscopy (AFM) image and then, subsequently, examining ECCI with transmission electron microscopy (TEM)-like invisibility criteria. By orthogonally choosing the diffraction vector g between (220) and (2-20), misfit dislocations seem to be always visible but partially faint in the g parallel to the line direction on the surface. With respect to the image contrast, Frank stacking faults and Lomer dislocations are likely to be completely invisible for parallel g. The criteria are further confirmed by cross-sectional TEM analysis, which shows a preferred homogeneous surface nucleation.

In this work, the epitaxy of SrTiO3 and BaTiO3 perovskites on the (001)-oriented silicon substrate by molecular beam epitaxy is investigated. The heterostructures are studied by means of various structural and electrical characterization techniques. In this study especially, the authors reveal experimentally by nanobeam electron diffraction analysis the critical thickness prior relaxation of BaTiO3 grown on an SrTiO3/Si pseudosubstrate. They also propose to use a strain mediated superlattice composed of stacked [BaTiO3/SrTiO3] bilayers to prevent misfit dislocation formation. Using this approach, they could demonstrate high quality and dislocation free BaTiO3 ferroelectric layers integrated on silicon as confirmed by piezo-force microscopy techniques.In this work, the epitaxy of SrTiO3 and BaTiO3 perovskites on the (001)-oriented silicon substrate by molecular beam epitaxy is investigated. The heterostructures are studied by means of various structural and electrical characterization techniques. In this study especially, the authors reveal experimentally by nanobeam electron diffraction analysis the critical thickness prior relaxation of BaTiO3 grown on an SrTiO3/Si pseudosubstrate. They also propose to use a strain mediated superlattice composed of stacked [BaTiO3/SrTiO3] bilayers to prevent misfit dislocation formation. Using this approach, they could demonstrate high quality and dislocation free BaTiO3 ferroelectric layers integrated on silicon as confirmed by piezo-force microscopy techniques.

On-chip optical interconnects still miss a high-performance laser monolithically integrated on silicon. Here, we demonstrate a silicon-integrated InP nanolaser that operates at room temperature with a low threshold of 1.69 pJ and a large spontaneous emission factor of 0.04. An epitaxial scheme to grow relatively thick InP nanowires on (001) silicon is developed. The zincblende/wurtzite crystal phase polytypism and the formed type II heterostructures are found to promote lasing over a wide wavelength range.

To design a high performance BaTiO3 (BTO)-integrated Si modulator, understanding how BTO domain orientations influence its electro-optical (EO) properties is crucial. The 100-nm-thick BTO films with c-oriented and a-oriented domains are obtained by exploiting various thickness of SrTiO3 buffer layers grown on Si(001) substrates. Then, the electro-optical behavior for 2 differently oriented samples is analyzed using spectroscopic ellipsometry.

This work investigates the interface resistivity of several heterostructures. Theoretical simulations suggest that, apart from the doping impact, the band offset and the difference in density of states (DOS) increase significantly the heterostructure interface resistivity. This conclusion corresponds well to our experiments that 1) high interface resistances are observed between (high-Ge content) p-SiGe/p-Si, n-InAs/n-Si, and n-InAs/n-Ge; and that 2) a TiSi x /12nm Si:P/n-Ge contact with favorable band alignment between Si:P/n-Ge approaches low effective contact resistivity of 1.4×10−8 Ω cm2, close to a record-low value for n-Ge contacts.

We report In 0.53 GaAs-channel gate-all-around FETs with channel width down to 7nm and L g down to 36nm, the smallest dimensions reported to date for IIIV devices fabricated on 300mm Si wafer. Furthermore, we systematically study the device scalability. InGaAs S/D improves the peak g m by 25% compared to InAs S/D. A g m of 1310 µS/µm with an SS sat of 82mV/dec is achieved for an L g =46nm device. At this L g , a record I on above 200µA/µm is obtained at I off of 100nA/µm and V ds =0.5V on a 300mm Si platform.

In the paper, we review our work on heterogeneous integration of InP photonic devices on silicon. We elaborate on two integration technologies that have been widely explored in the Photonics Research group, i.e. the relatively mature adhesive bonding based integration scheme and a newly demonstrated buffer-less epitaxial growth approach. Based on these techniques, we describe a broad range of photonic devices including mode-locked lasers, high speed directly modulated distributed feedback lasers, electro-absorption modulators, photodetectors, super-luminescent light emitting diodes, etc.

An imperative factor in adapting GeSn as the channel material in CMOS technology, is the gate-oxide stack. The performance of GeSn transistors is degraded due to the high density of traps at the oxide-semiconductor interface. Several oxide-gate stacks have been pursued, and a midgap Dit obtained using the ac conductance method, is found in literature. However, a detailed signature of oxide traps like capture cross-section, donor/acceptor behavior and profile in the bandgap, is not yet available. We investigate the transition region between stoichiometric insulators and strained GeSn epitaxially grown on virtual Ge substrates. Al2O3 is used as high-κ oxide and either Ge1-xSnxO2 or GeO2 as interfacial layer oxide. The interface trap density (Dit) profile in the lower half of the bandgap is measured using deep level transient spectroscopy, and the importance of this technique for small bandgap materials like GeSn, is explained. Our results provide evidence for two conclusions. First, an interface traps density of 1.7 × 10(13) cm(-2)eV(-1) close to the valence band edge (Ev + 0.024 eV) and a capture cross-section (σp) of 1.7 × 10(-18) cm(2) is revealed for GeSnO2. These traps are associated with donor states. Second, it is shown that interfacial layer passivation of GeSn using GeO2 reduces the Dit by 1 order of magnitude (2.6 × 10(12) cm(-2)eV(-1)), in comparison to GeSnO2. The results are cross-verified using conductance method and saturation photovoltage technique. The Dit difference is associated with the presence of oxidized (Sn(4+)) and elemental Sn in the interfacial layer oxide.

The semiconductor ICT industry continues its neverending pursuit of new approaches for fabricating integrated circuits to reduce device cost and improve device performance. For future device generations, many different approaches are considered, for which the efficient engineering of new materials and architectures are the main challenge to improve device performance. InP is one of these new materials, which is considered to be used as virtual substrate for III-V based nMOS devices.

CMOS scaling for sub-12 nm nodes will need high-mobility channel semiconductors such as III-V materials to be integrated on large diameter Si substrates. A way to overcome lattice mismatch is to confine defects resulting from strain relaxation on the sidewalls of trenches made by etch-back of Si in standard Shallow-Trench-Isolation (STI) structures. The surface of the InP layers, grown as buffer material in these trenches by selective epitaxy, is planarized by means of CMP, after which it needs to be recessed to allow for the deposition of the III-V channel stack. We have developed an in-situ HCl etching process allowing a close control of the recess depth down to a few nm and leaving a clean and planar InP surface well suited for subsequent III-V epitaxial growth. The process development was carried out in a commercial Aixtron Crius MOCVD reactor on standard SiO2 STI patterned 200 mm Si (001) wafers.

The integration of higher carrier mobility materials to increase drive current capability in the next CMOS generations is required for device scaling. But a fundamental issue regarding the introduction of high-mobility III–V in CMOS is the electrical passivation of the interface with the high-κ gate dielectric. In this work, we show that in situ H2S surface treatment on GaAs(001) leads to a stable and reorganized oxide/III–V interface. The exposition of the GaAs surface is monitored in situ by RHEED and the interface is characterized by XPS analyses. Finally, MOS capacitors are fabricated to extract interface state density over the band gap. These results highlight a promising re-interest in chalcogenide passivation of III–V surfaces for CMOS applications.

Si and Se implantations have been systematically investigated in In"0"."5"3Ga"0"."4"7As. Different implant doses and various activation anneals with temperatures up to 700^oC have been examined. Raising Si implant dose from 1x10^1^4 to 1x10^1^5cm^-^2 was found to increase the active doping concentration by about a factor of two. As confirmed by Transmission Electron Microscopy (TEM) and electrical measurements, the rest of the implanted Si ions remain as defects in the crystal and degrade the mobility. It was also confirmed from Secondary Ion Mass Spectrometry (SIMS) that the Si diffusivity in InGaAs is negligible up to 700^oC implant activation anneal making Si a suitable option for the formation of shallow junctions in InGaAs. The activation efficiency, sheet resistance, carrier density and mobility data of 25keV Se and Si implanted InGaAs layers are also presented under various activation anneal temperatures.

© 2018 Author(s). In0.53Ga0.47As p + n diodes with different densities of extended defects have been analyzed by detailed structural and electrical characterization. The defects have been introduced during Metal-Organic Vapor Phase Epitaxy (MOVPE) growth by using a lattice-mismatched layer on a semi-insulating InP or GaAs substrate. The residual strain and indium content in the n-type In0.53Ga0.47As layer have been determined by high-resolution X-ray diffraction, showing nearly zero strain and a fixed indium ratio of 0.53. The deep levels in the layer have been characterized by Deep Level Transient Spectroscopy. The mean value of electron traps at 0.17 ± 0.03 eV below the conduction band minimum EC is assigned to the "localized" states of α 60° misfit dislocations; another broad electron trap with mean activation energies between EC- 0.17 ± 0.01 and 0.39 ± 0.04 eV, is identified as threading dislocation segments with "band-like" states. A high variation of the pre-exponential factor KT by 7 orders of magnitude is found for the latter when changing the filling pulse time, which can be explained by the coexistence of acceptor-like and donor-like states in the core of split dislocations in III-V materials. Furthermore, two hole traps at EV+ 0.42 ± 0.01 and EV+ 0.26 ± 0.13 eV are related to the double acceptor of the Ga(In) vacancy (VGa/In3-/2-) and 60° β misfit dislocations, respectively. Finally, the dislocation climbing mechanism and the evolution of the antisite defects AsGa/In are discussed for n-type In0.53Ga0.47As. ispartof: JOURNAL OF APPLIED PHYSICS vol:124 issue:16 status: published

Vertical InAs nanowires (NWs) grown on a Si substrate are promising building-blocks for next generation vertical gate-all-around transistor fabrication. We investigate the initial stage of InAs NW selective area epitaxy (SAE) on a patterned Si (111) substrate with a focus on the interfacial structures. The direct epitaxy of InAs NWs on a clean Si (111) surface is found to be challenging. The yield of vertical InAs NWs is low, as the SAE is accompanied by high proportions of empty holes, inclined NWs, and irregular blocks. In contrast, it is improved when the NW contains gallium, and the yield of vertical InxGa1-xAs NWs increased with higher Ga content. Meanwhile, unintentional Ga surface contamination on a patterned Si substrate induces high yield vertical InAs NW SAE, which is attributed to a GaAs-like seeding layer formed at the InAs/Si interface. The role of Ga played in the III-V NW nucleation on Si is further discussed. It stabilizes the B-polarity on a non-polar Si (111) surface and enhances the nuc...

We present in this paper the use of Gas Source Molecular Beam Epitaxy for the large-scale growth of transition metal dichalcogenides. Fiber-textured MoS2 co-deposited thin films (down to 1 MLs) are grown on commercially 200 mm wafer size templates where MX2 crystalline layers are achieved at temperatures ranging from RT to 550 °C. Raman Spectroscopy and photoluminescence measurements along with X-Ray Photoelectron Spectroscopy show that a low growth rate is essential for complete Mo sulfurization during MoS2 co-deposition. Finally, cross-section Transmission Electron Microscopy investigations are discussed to highlight the influence of SiO2 and Al2O3 used surfaces on MoS2 deposition.

Silicon does not emit light efficiently, therefore the integration of other light-emitting materials is highly demanded for silicon photonic integrated circuits. A number of integration approaches have been extensively explored in the past decade. Here, the most recent progress in this field is reviewed, covering the integration approaches of III-V-to-silicon bonding, transfer printing, epitaxial growth and the use of colloidal quantum dots. The basic approaches to create waveguide-coupled on-chip light sources for different application scenarios are discussed, both for silicon and silicon nitride based waveguides. A selection of recent representative device demonstrations is presented, including high speed DFB lasers, ultra-dense comb lasers, short (850nm) and long (2.3 mu m) wavelength lasers, wide-band LEDs, monolithic O-band lasers and micro-disk lasers operating in the visible. The challenges and opportunities of these approaches are discussed.

Monolithically integrating BaTiO3 on silicon substrates has attracted attention because of the wide spectrum of potential novel applications ranging from electronics to photonics. For optimal device performance, it is important to control the BaTiO3 domain orientation during thin film preparation. Here, we use molecular beam epitaxy to prepare crystalline BaTiO3 on Si(001) substrates using a SrTiO3 buffer layer. A systematic investigation is performed to understand how to control the BaTiO3 domain orientation through the thickness engineering of the SrTiO3 buffer layer and the BaTiO3 layer itself. This provides different possibilities for obtaining a given BaTiO3 orientation as desired for a specific device application.

Silicon photonics holds the promise of converging electronics and photonics. The key component, a low-cost high-performance laser, is still missing however within this platform. Although novel solutions have been proposed to increase the light emission directly from silicon (or Ge), compared with their III-V counterparts, these solutions are still in their infancy. Recently, the epitaxial growth of III-Vs on silicon regained a wide interest. III-V nanowire growth has been widely investigated. However, most of the III-V nanowire lasers on silicon require a complex cleaving and transfer process, which make these devices not suitable for dense integration. In addition, the large cavity dimensions along the nanowire axis (several microns) hinder dense integration. Here, we present the first room-temperature operation of an ultra-short InP nanowire laser that is epitaxially grown on an exactly [001] oriented silicon substrate. The sub-micron sized laser cavity largely enhances the interaction of the lasing mode with the gain medium, and a large spontaneous emission factor has been obtained.

In this work, we present a systematic study of the effect of the stoichiometry of BaTiO3 (BTO) films grown on the Ge(001) substrate by molecular-beam-epitaxy using different characterization methods relying on beam diffraction, including reflection high-energy electron diffraction (RHEED), X-ray diffraction (XRD), and selected-area electron diffraction in transmission electron microscopy. Surprisingly, over a wide range of [Ba]/[Ti] ratios, as measured by the Rutherford backscattering spectrometry, all the BTO layers exhibit the same epitaxial relationship < 100 > BTO(001)//< 110 > Ge(001) with the substrate, describing a 45 degrees lattice rotation of the BTO lattice with respect to the Ge lattice. However, varying the [Ba]/[Ti] ratio does change the diffraction behavior. From RHEED patterns, we can derive that excessive [Ba] and [Ti] generate twinning planes and a rougher surface in the non-stoichiometric BTO layers. XRD allows us to follow the evolution of the lattice constants as a function of the [Ba]/[Ti] ratio, providing an option for tuning the tetragonality of the BTO layer. In addition, we found that the intensity ratio of the 3 lowest-order Bragg peaks I-(001)/I-(002), I-(101)/I-(002), and I-(111)/I-(002) derived from omega - 2 theta scans characteristically depend on the BTO stoichiometry. To explain the relation between observed diffraction patterns and the stoichiometry of the BTO films, we propose a model based on diffraction theory explaining how excess [Ba] or [Ti] in the layer influences the diffraction response. Published by AIP Publishing.

Electron beam evaporation in a molecular beam epitaxy reactor was used to deposit, at 400°C, amorphous LaAlO3 high-κ oxide films on p-type Si(001). X-ray photoelectron spectroscopy and transmission electron microscopy showed that the interface with Si is free of SiO2 or silicates. Electrical measurements performed on as-deposited samples reveal an equivalent oxide thickness as low as 5A for a film having a physical thickness of 41A, a leakage current of 5.6×10−2A∕cm2 at ∣Vg−VFB∣=1V, and no flatband voltage shift.

This work reports on the molecular beam epitaxy of high quality single crystal γ‐Al2O3 thin films on Si(001) and Si(111) substrates. For both substrate orientations, film surfaces are found to be smooth and the oxide-Si interfaces are atomically abrupt without interfacial layers. Reflection high energy electron diffraction, x-ray diffraction, and transmission electronic microscopy characterizations were used to study the epitaxial relationship and the structural quality of the γ‐Al2O3 layers depending on the Si substrate orientation. On Si(111), the alumina layers present a high crystalline quality. Evidence is made for a “two-for-three” unit cell indirect epitaxial relationship between γ‐Al2O3 and Si(111). On Si(001), after a transition from cubic to hexagonal surface symmetry, the growth planes of γ‐Al2O3 change from (001) to (111) leading to a bidomain growth.

This work reports on the structural properties of an epitaxial SrTiO3 (STO) layer grown by molecular beam epitaxy on a Si(001) substrate with a two step process. The study, which includes a complete characterization of large scale plane-view images of the STO layer, is based on a careful analysis of x-ray spectra and transmission electron microscopy images. The STO layer presents a good crystalline quality and a slight texturation related to the presence of extended defects. A thin Ti-rich amorphous silicate layer (thickness ≈1.3nm) is formed at the interface between the STO and the Si substrate, evidencing the thermodynamic instability of the STO/Si interface. The difference between the thermal expansion coefficients of Si and STO is shown to be at the origin of an increased in-plane lattice parameter (3.927A) of the STO layer as compared to its bulk value (3.905A). This effect of differential thermal expansion is expected to be responsible for the formation of at least part of the extended defects of th...

The efficiency of the ammonium sulfide vapor (ASV) treatment, as opposed to the wet treatment in the liquid ammonium sulfide solution, on the performance improvement of the In0.53Ga0.47As surface-channel as well as InP-capped buried-channel metal-oxide-semiconductor field-effect-transistors (MOSFET) was demonstrated for the first time. MOSFETs were fabricated with either HCl or ASV surface treatments prior to the gate oxide deposition. ASV treatment was found to be very efficient in boosting the drive current of the transistors compared to that of the HCl treatment. It was also found that the ASV treatment leads to a lower border trap density and slightly higher oxide/semiconductor interface defect density compared to that of the HCl treatment. X-ray photoelectron spectroscopy (XPS) studies of In0.53Ga0.47As native oxide regrowth after both surface treatments identified indium sub-oxides as a possible cause of the performance degradation of the HCl treated devices. Based on this work, ASV treatment could be an efficient solution to the passivation of III-V surfaces. (C) 2011 American Institute of Physics. [doi: 10.1063/1.3638492] The authors acknowledge the European Commission for financial support in the DualLogic project no. 214579. Further, we thank the IMEC core partners within the IMEC’s Industrial Affiliation Program on Logic/Ge-III/V.

The integration of high carrier mobility materials into future CMOS generations is presently being studied in order to increase drive current capability and to decrease power consumption in future generation CMOS devices. If III-V materials are the candidates of choice for n-type channel devices, antimonide-based semiconductors present high hole mobility and could be used for p-type channel devices. In this work we first demonstrate the heteroepitaxy of fully relaxed GaSb epilayers on InP(001) substrates. In a second part, the properties of the Al2O3/GaSb interface have been studied by in situ deposition of an Al2O3 high-kappa gate dielectric. The interface is abrupt without any substantial interfacial layer, and is characterized by high conduction and valence band offsets. Finally, MOS capacitors show well-behaved C-V with relatively low D-it along the bandgap, these results point out an efficient electrical passivation of the Al2O3/GaSb interface. (C) 2011 American Institute of Physics. [doi:10.1063/1.3569618] This work is part of the IMEC Industrial Affiliation Program and is supported by the European Commission’s project FP7-ICT-DUALLOGIC no. 214579, “Dual-Channel CMOS for (sub)-22nm High Performance Logic.” The authors would like to thank Th. Conard and A. Franquet for XPS characterizations, F. Paola and H. Bender for TEM analyses, and H. Costermans for the support of the MBE tool.