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In this article, a novel SOI MESFET which can be suitable for high power applications is proposed. In order to upgrade its electrical characteristics, a protruded gate and dual wells (PGDW) n-type silicon in the buried oxide are formed. This strategy by using a protruded gate and a right well at the drain side increases the channel thickness causing a rise in the drain current. Besides, a reduction in the electric field maximum value near the drain side leads to improving the maximum power density of the PGDW- structure 143% over a Conventional MESFET. A left well in the proposed structure has been used to absorb the created holes due to the impact ionization mechanism and causes improvement of floating body effect. Also, the PGDW-MESFET demonstrates the improved performance in the RF characteristics, consequently, two parameters h21, Unilateral power gain boost almost 14%, and 11%, respectively compared to the C-MESFET.

We investigated a novel drug delivery system comprising nanoparticles based on chitosan/graphene oxide (GO)/folic acid for targeted delivery of chemotherapeutic drugs. In this research, GO is accompanied with chitosan as natural cationic polysaccharide to increase compatibility. First, GO was synthesized, then chitosan was grafted to it by chemical interaction, and then chitosan nanoparticle and GO hybrid nanocomposite were synthesized. The resulting nanocarrier is analyzed via different characterization methods. FTIR and XRD results were used to show the chemical and structural information before and after modification of GO nanocarrier. FESEM image of GO observed showed the nanoparticle was successfully attached on the surface of GO sheets. The thermal decomposition obtained showed that the thermal stability has been extended by the grafted Chitosan chains to GO; also, the highest loading capacity with folic acid was related to graphene oxide–chitosan nanoparticle nanocomposite. Then, folic acid was loaded on nanocarrier and its release was assessed. Results of this research show the combination of chitosan and GO by chemical interaction leading to creating holes, which increase loading to 99.97% and release to 94% for 72 h.

This paper proposes a new silicon on nothing lateral double-diffused metal-oxide-semiconductor with two air gaps in the gate insulator (SON-APG LDMOS). Utilizing air for the buried layer and placing two air pillars in gate oxide has improved DC and AC characteristics of the transistor. 2-D simulation results of ATLAS simulator illustrate a 50% enhancement in the breakdown voltage compared to a conventional SOI-LDMOS (C-LDMOS). Besides, the on-state resistance reduces 60% as a result of drain current augmentation in the SON-APG LDMOS. Moreover, the RF feature of the SON-APG LDMOS improves due to the enhancement in the gate capacitances of the transistor. Therefore, the cut-off (fT), as well as maximum oscillation frequency (fMax), grows. The extra noise that the device adds to the signal reaching the load (Noise Figure) has improved in the proposed structure.

In this study, a junctionless double-gate metal-oxide semiconductor field-effect transistor (MOSFET) is investigated by using the concept of charge plasma. The n+ charge plasma in source and drain regions is created electrically in the double-gate MOSFET (CPSD-MOSFET) using additional appropriate metals without applying doping. The results showed that the structure is like a conventional MOSFET, which can improve some electrical parameters. It protects the proposed structure from some limitations such as random doping oscillations and short-channel effects bearing its conventional structure. In addition, high temperature and annealing processes are unnecessary for making the source/drain doping of the CPSD-MOSFET because their regions are created electrically. Thus, the thermal budget step is removed. Furthermore, the proposed structure has some improvements as compared to the junctionless transistor structure, and it can overcome the main problem of this structure, namely the high off current. In general, in the proposed structure, the charge plasma idea changes the charges and depletion regions besides the channel and improves the short-channel effects such as hot electron effect and leakage current because of the improved electric field.

In this paper, we offer a new structure of N+-P-P Fin Field Effect Transistor (FinFET) with a dual material gate in which the drain side P–N junction has been physically removed. The P-type drain consists of two parts, depletion region (DR) and electrically doped (ED) area, where the ED region is surrounded by an extra gate with optimized length and appropriate work function made of barium (B-gate). The ED region located under the B-gate is converted to N+ drain using the charged plasma (CP) concept to design the CP-FinFET. Improved ability to control the hot carrier effect by amending the critical electric field is the main idea of this work. The p-type depletion region (DR) created between the silicon active layer and electrically doped drain eliminates the gate-drain overlap and reduces the charge sharing and short channel effects (SCE). The modified electric field in the DR region offers advantages including improved hot-electron reliability and high-performance devices. Therefore, in the CP-FinFET the degradation mechanism improves due to the hot carrier effect (HCE) reduction. Indeed, the improvement in device performance is investigated using three-dimensional Atlas simulator with concentrating on the gate current, off-state current, reliability, electron temperature and gate induced drain leakage (GIDL). The comparison results demonstrate the superiority of the proposed structure as a high-efficiency device to design reliable Complementary metal–oxide–semiconductor circuits in nanoscale.

The detection of photons by plasmonic subwavelength devices underpins spectroscopy, low-power wavelength division multiplexing for short-distance optical communication, imaging, and time-gated distance measurements. In this work, we demonstrate infrared light-sensing using toroidal dipole-resonant plasmonic multipixel meta-atoms. As a key factor, the toroidal dipolar mode is an extremely localized electromagnetic excitation independent of the conventional multipoles. The exquisite behavior of this mode enables significant enhancements in the localized electromagnetic field and absorption cross-section, which boost the field confinement at the metal-dielectric interfaces. The proposed novel approach offers an advanced photodetection of the incident light based on substantial confinement of electromagnetic fields in a tiny spot, giving rise to the generation of hot carriers and a large photocurrent. Using both n- and p-type silicon (Si) substrates, we exploited the free-carrier absorption advantage of p-type Si to devise a high-responsivity device. Our findings show an unprecedented performance for infrared plasmonic photodetectors with low noises, high detectivity and remarkable internal quantum efficiency (IQE). Moreover, the tailored photodetection device provides a significant linear dynamic range of 46 dB and a fast operation speed. Our narrowband infrared light sensing photodevice offers a promising approach for further research studies over the optoelectronic and plasmonic tools and paves a viable route for low-dimensional photonic systems.

New silicon on insulator triple-gate transistor structure is presented by using Silicon- Germanium material in the source and the buried oxide region which creates a tunneling diode to reduce the generated holes by impact ionization in the channel. The Kink effect, self-heating effect, and recombination reduce in the proposed structure by collecting holes in the channel. In this paper, we study the improvement of off current, output resistance, hole concentration, electric field, heat power, and drain induced barrier lowering (DIBL) of the proposed structure in comparison with a conventional triple-gate transistor.

A new Metal Semiconductor Field Effect Transistor (MESFET) structure in Silicon on Insulator (SOI) technology will be introduced in this paper. In our idea, an oxide barrier is used on the drain side of the gate to improve DC and AC characteristics of MESFETs. We call the proposed structure as modified equipotential contour MESFET (MEC-MESFET). Our main reason to present this proposed structure is to modify the equipotential contour distributions by using the oxide barrier. In addition, the oxide barrier has a greater energy band gap rather than a silicon (Si) semiconductor. So, in comparison with Si, it will break at higher voltages. The maximum electric field occurs on the gate edge near the drain side in a conventional MESFET (C-MESFET). Therefore, in the proposed structure, by placing an additional oxide barrier in the drain side of the gate and modifying the maximum electrical field in this part, the breakdown voltage increases. The drain saturation and breakdown voltage of the proposed structure improve 21 and 29 percent, respectively, which increases the maximum output power density to 56 percent in comparison with conventional silicon on insulator MESFET (C-MESFET). Moreover, the gate capacitance decreases by using the oxide barrier and consequently improves the frequency characteristics like Unilateral power gain (U), Maximum Available Gain (MAG), current gain (h21), and noise in comparison with the C-MESFET.

This paper suggests and investigates a p-n structure, which emulates as a MOSFET. In the proposed structure we utilize an L-shape contact with a proper work function over the source region of silicon on insulator MOSFET to convert the source region from p+ to n+. We check its performance by indicating the band diagram and electron and hole concentrations which acts as n-p-n transistor in OFF state. By employing this idea, the p-n structure acts as MOSFET by a Virtual Hole’s Well at the source side (VW-SOI MOSFET), so the carrier concentrations specially hole concentration modify in the channel chiefly the source side in ON state which suppresses the floating body effect. The hole concentration, electric field, floating body effect and finally the lattice temperature improve. So the self heating effect that is one of the biggest problems in SOI devices, improves. Also, the simulation results of the VW-SOI MOSFET indicate that it is a suitable case for a switching performance because of decreasing gate-source, gate-drain capacitances, and noise. And finally the proposed structure can be a reliable structure because it decreases the effect of hot carriers due to short channel effects.

We propose herein a new dual-gate metal---oxide---semiconductor field-effect transistor (MOSFET) with just a unipolar junction (UJ-DG MOSFET) on the source side. The UJ-DG MOSFET structure is constructed from an $${N}^{+}$$N+ region on the source side with the rest consisting of a $${P}^{-}$$P- region over the gate and drain, forming an auxiliary gate over the drain region with appropriate length and work function (named A-gate), converting the drain to an $${N}^{+}$$N+ region. The new structure behaves as a MOSFET, exhibiting better efficiency than the conventional double-gate MOSFET (C-DG MOSFET) thanks to the modified electric field. The amended electric field offers advantages including improved electrical characteristics, reliability, leakage current, $${I}_{\mathrm{ON}}/I_{\mathrm{OFF}}$$ION/IOFF ratio, gate-induced drain leakage, and electron temperature. Two-dimensional analytical models of the surface potential and electric field over the channel and drain are applied to investigate the drain current in the UJ-DG MOSFET. To confirm their accuracy, the MOSFET characteristics obtained using the 2D Atlas simulator for the UJ-DG and C-DG are analyzed and compared.

Progress in the technology of submicron semiconductor device, which makes a short-channel and quantum effects, having equations of nonlinear modelling, leads to complicated and time-consuming calculations. In order to control these complexities and obtain the device characteristics according to device parameters, a faster method is needed. In this paper, a combinational algorithm is proposed for modelling a nano silicon-on-insulator metal–oxide–semiconductor field effect transistor (SOI MOSFET) characteristic. The proposed method shows the same device characteristics with lower input parameters. In this method, a combination of genetic algorithm (GA) and artificial neural network are used. Then quantum evolutionary algorithm (QEA) is employed instead of genetic algorithm (GA) for comparing and modifying algorithm. Results show that the algorithm’s accuracy is 95% and 98% for test data of GA and QGA, respectively. Moreover, the reduction percentage of input parameters are 11% and 52% for GA and QEA, respectively. The simulation results represent that the implemented quantum genetic algorithm for prediction of device characteristics is more effective and accurate than GA.

A novel 2-D analytical drain current model of novel Dual Metal Gate Tunnel Field Effect Transistors Based on MOSFETs (DMG-TFET) is presented in this paper. The proposed Tunneling FET is extracted from a MOSFET structure by employing an additional electrode in the source region with an appropriate work function to induce holes in the N + source region and hence makes it as a P + source region. The electric field is derived which is utilized to extract the expression of the drain current by analytically integrating the band to band tunneling generation rate in the tunneling region based on the potential profile by solving the Poisson's equation. Through this model, the effects of the thin film thickness and gate voltage on the potential, the electric field, and the effects of the thin film thickness on the tunneling current can be studied. To validate our present model we use SILVACO ATLAS device simulator and the analytical results have been compared with it and found a good agreement.

This paper suggests and investigates a double-gate (DG) MOSFET, which emulates tunnel field effect transistors (M-TFET). We have combined this novel concept into a double-gate MOSFET, which behaves as a tunneling field effect transistor by work function engineering. In the proposed structure, in addition to the main gate, we utilize another gate over the source region with zero applied voltage and a proper work function to convert the source region from N+ to P+. We check the impact obtained by varying the source gate work function and source doping on the device parameters. The simulation results of the M-TFET indicate that it is a suitable case for a switching performance. Also, we present a two-dimensional analytic potential model of the proposed structure by solving the Poisson’s equation in x and y directions and by derivatives from the potential profile; thus, the electric field is achieved. To validate our present model, we use the SILVACO ATLAS device simulator. The analytical results have been compared with it.

In this article, we study a novel double-gate SOI MOSFET structure incorporating insulator packets (IPs) at the junction between channel and source/drain (S/D) ends. The proposed MOSFET has great strength in inhibiting short channel effects and OFF-state current that are the main problems compared with conventional one due to the significant suppressed penetrations of both the lateral electric field and the carrier diffusion from the S/D into the channel. Improvement of the hot electron reliability, the ON to OFF drain current ratio, drain-induced barrier lowering, gate-induced drain leakage and threshold voltage over conventional double-gate SOI MOSFETs, i.e. without IPs, is displayed with the simulation results. This study is believed to improve the CMOS device reliability and is suitable for the low-power very-large-scale integration circuits.

A Double-Gate Armchair-Graphene Nanoribbon FET is proposed to realize a high-sensitive and small-size biosensor in order to detect DNA without high-cost and time-consuming labeling process. Two nanogap cavities open inside the top and bottom gate oxides by the method of sacrificed layer etching. When the DNA biomolecule is introduced to the nanogap cavity, the hybridization event which is actually the formation of a double-strand of DNA will occur thus electrically modulating the GNR channel leading to a change in the drain current. The important report of this research is about attained high sensitivity of the proposed biosensor for a vast spectrum of the DNA biological samples. It is worth noting that a DNA sequence by 23 nucleotides extracted from Neisseria gonorrhoeae can be detected as a special case. An extensive numerical approach has been applied in order to characterize the proposed biosensor. The suggested biosensor has been evaluated by solving Schrodinger equation )SE( with Non-Equilibrium Green Function (NEGF) method in the mode-space coupled into Poisson solver in a self-consistent manner assuming ballistic limit. Two different expressions of sensitivity in terms of the threshold voltage and current have been defined giving a good metric for the sensitivity analysis. The results revealed a relative sensitivity of 1 mV/nm2 by a filled area by the DNA about 120 nm2 showing the excellent superiority for the proposed biosensor as compared to other counterparts. The effective area of the proposed biosensor obtains 240 nm2 which is very small in comparison with other reports highlighting high capability of the biosensor in the detection. It has been shown that the proposed biosensor can be implemented in ultra-scaling domain resulting in considerable increase in the sensitivity promising a potent and reliable candidate for high-sensitive and small-size biosensors. Also, the technical issues on designing the suggested biosensor have been investigated to achieve a useful guideline in detection and identification of the target DNAs.

To recuperate subthreshold characteristics and short channel endurance of gate-all-around field effect transistors (GAA-FETs) by scaling, we incorporate an auxiliary gate with an appropriate work function close to the source side of a conventional circular GAA(CGAA) transistor in our simulation study. The CGAA electrical characteristics have been calibrated against a 22 nm IBM sample. Based on our simulation results, utilizing an auxiliary gate with higher work function material in the proposed structure (AuxG-GAAFET) leads electron energy sub-bands to be more split out. This reduces electron concentration in the channel and thus the leakage current is decreased along with subthreshold slope (SS). Furthermore, the proposed AuxG-GAAFET shows better ION/IOFF current ratio, lower threshold voltage roll-off, better subthreshold slope (SS) and better drain induced barrier lowering (DIBL) factor caused by scaling. For this, utilizing an appropriate auxiliary gate can be among promising methods for deep transistor scaling in the future.

For achieving reliable transistor, we investigate an amended channel doping (ACD) engineering which improves the electrical and thermal performances of fully-depleted silicon-on-insulator (SOI) MOSFET. We have called the proposed structure with the amended channel doping engineering as ACD-SOI structure and compared it with a conventional fully-depleted SOI MOSFET (C-SOI) with uniform doping distribution using 2-D ATLAS simulator. The amended channel doping is a vertical graded doping that is distributed from the surface of structure with high doping density to the bottom of channel, near the buried oxide, with low doping density. Short channel effects (SCEs) and leakage current suppress due to high barrier height near the source region and electric field modification in the ACD-SOI in comparison with the C-SOI structure. Furthermore, by lower electric field and electron temperature near the drain region that is the place of hot carrier generation, we except the improvement of reliability and gate induced drain lowering (GIDL) in the proposed structure. Undesirable Self heating effect (SHE) that become a critical challenge for SOI MOSFETs is alleviated in the ACD-SOI structure because of utilizing low doping density near the buried oxide. Thus, refer to accessible results, the ACD-SOI structure with graded distribution in vertical direction is a reliable device especially in low power and high temperature applications.

We describe herein a 4H-SiC metal---semiconductor field-effect transistor (MESFET) with a novel dual well in the buffer layer. The key idea is to change the channel thickness to decrease the hole concentration and modify the depletion region shape and drain current path in the channel. In the proposed structure, a dual well is created in the buffer layer exactly under the gate. We call this structure the dual-well MESFET (DW-MESFET). The drain current of the proposed structure increases by 34.7 % compared with the conventional structure (C-MESFET) due to the change in channel thickness and modification of the depletion region and drain current path. Also, the maximum power density ($$P_{\mathrm{max}}$$Pmax) and the direct-current (DC) transconductance ($$g_{\mathrm{m}}$$gm) of the DW-MESFET increase by 45.23 and 72.5 %, respectively, in comparison with the C-MESFET structure. Hence, the proposed structure can be used for high-current and high-power applications.

Effective and efficient management of human betacoronavirus severe acute respiratory syndrome (SARS)-CoV-2 virus infection i.e., COVID-19 pandemic, required sensitive and selective sensors with short sample-to-result durations for performing desired diagnostics. In this direction, one appropriate alternative approach to detect SARS-CoV-2 virus protein at low level i.e., femtomolar (fM) is exploring plasmonic metasensor technology for COVID-19 diagnostics, which offers exquisite opportunities in advanced healthcare programs, and modern clinical diagnostics. The intrinsic merits of plasmonic metasensors stem from their capability to squeeze electromagnetic fields, simultaneously in frequency, time, and space. However, the detection of low-molecular weight biomolecules at low densities is a typical drawback of conventional metasensors that has recently been addressed using toroidal metasurface technology. This research is focused on the fabrication of a miniaturized plasmonic immunosensor based on toroidal electrodynamics concept that can sustain robustly confined plasmonic modes with ultranarrow lineshapes in the terahertz (THz) frequencies. By exciting toroidal dipole mode using our quasi-infinite metasurface and a judiciously optimized protocol based on functionalized gold nanoparticles (AuNPs) conjugated with the specific monoclonal antibody specific to spike protein (S1) of SARS-CoV-2 virus onto the metasurface, the resonance shifts for diverse concentrations of the spike protein are monitored. Possessing molecular weight around ~76 kDa allowed to detect the presence of SARS-CoV-2 virus protein with significantly low as limit of detection (LoD) was achieved as ~4.2 fM. We envisage that outcomes of this research will pave the way toward the use of toroidal metasensors as practical technologies for rapid and precise screening of SARS‐CoV‐2 virus carriers, symptomatic or asymptomatic, and spike proteins in hospitals, clinics, laboratories, and site of infection., Highlights • Terahertz plasmonic metasensors for the detection of SARS-CoV-2 clinical diagnosis. • Quantitative and qualitative detection of spike proteins. • Rapid and precise detection of SARS-CoV-2 spike proteins at femtomolar concentrations. • Simple detection approach and compatible for high throughput COVID-19 screening in hospitals and test laboratories. • Early-stage detection of the infection through noninvasive tests.

In this paper, a novel symmetrical structure (SS) of 4H---SiC metal semiconductor field effect transistor (MESFET) as an effective way to improve the breakdown voltage is presented. The key idea in this work is to improve the breakdown voltage, maximum output power density, and frequency parameters of the device using a symmetrical structure with recessed gate. The SS-MESFET modifies the electric field in the drift layer significantly. The influence of the SS-MESFET on the saturation current, breakdown voltage $$(\hbox {V}_{\mathrm{BR}})$$(VBR), and small-signal characteristics of the SS-MESFET are studied by numerical device simulation. Using two-dimensional device simulation, we demonstrate that the breakdown voltage $$(\hbox {V}_{\mathrm{BR}})$$(VBR) improved by factors 2.5 and 3.3 in comparison with an asymmetrical conventional MESFET structure (AC-MESFET) and a symmetrical conventional MESFET structure (SC-MESFET), respectively. Also, the maximum output power density $$(\hbox {P}_{\mathrm{max}})$$(Pmax) improved about by 93 and 250 % in comparison with the AC-MESFET and SC-MESFET structures, respectively. So, the SS-MESFET shows the superior maximum available gain (MAG), unilateral power gain (U), and current gain $$(\hbox {h}_{12})$$(h12) which is presenting the proposed structure is more suitable device for high power microwave applications.

One of the serious prevalent weaknesses for silicon-on-insulator junctionless (CSOI-JLT) devices is high leakage current resulting in the limitation of it in nanoscale circuits. To solve this main concern, an efficient technique relying on the modification of band energy profile has been suggested. To reach this important achievement, a special part of the buried oxide (BOX) is replaced by the silicon material (Si) which is the same as the substrate in terms of type and doping concentration. Dividing the BOX redistributes the band energy and makes the channel region (Ch/R) near the source narrower which is desirable in the off-state situation. The considerable reduction of the leakage current and increase in the current gain (Ion/Ioff) is exhibited in the proposed structure. The modification of band energy for the suggested junctionless is announced as an initial start for improvement of the electrical performance in terms of leakage current, subthreshold swing (SS), global lattice temperature (GLT), electron velocity, output conductance, unilateral power gain, cut-off frequency, maximum oscillation frequency, total gate capacitance and minimum noise figure as compared to the common junctionless (CSOI-JLT).