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A metal ion threshold switch (MITS) based on an Ag/TiN/HfO2/Pt stack is experimentally demonstrated with improved endurance. The incorporation of a low-temperature atomic layer deposition (ALD) TiN layer as an efficient diffusion barrier enables optimum Ag infiltration during the electroforming step. Further, the tunability of the threshold voltage (VTS) from 0.25 to 1.1V via bottom electrode (BE) work function engineering is demonstrated. The Ag/TiN/HfO2/Al MITS selector exhibits a 4.4x increase in VTS, $100~\mu \text{A}$ ON-current handling capability, low leakage (~10 pA), $10^{{7}}$ half-bias non-linearity and fast (

In recent years, several designs that use in-memory processing to accelerate machine-learning inference problems have been proposed. Such designs are also a perfect fit for discrete, dynamic, and distributed systems that can solve large-dimensional optimization problems using iterative algorithms. For in-memory computations, ferroelectric field-effect transistors (FerroFETs) owing to their compact area and distinguishable multiple states offer promising possibilities. We present a distributed architecture that uses FerroFET memory and implements in-memory processing to solve a template problem of least squares minimization. Through this architecture, we demonstrate an improvement of $21 \times $ in energy efficiency and $3 \times $ in compute time compared to a static random access memory (SRAM)-based processing-in-memory (PIM) architecture.

In this letter, the write disturb of Hf0.5Zr0.5O2-based 1T-FeFET nonvolatile AND memory array is experimentally investigated for ${V}_{W}$ /2 and ${V}_{W}$ /3 inhibition bias schemes to determine the worst-case memory sensing condition. Read margin analysis reveals that the increased leakage current in the low- ${V}_{\textsf {TH}}$ erased state and the increased read current of the high- ${V}_{\textsf {TH}}$ programmed state are the key factors that limit the maximum array size.

We fabricate, characterize, and establish the critical design criteria of Hf0.5Zr0.5O2 (HZO)-based ferroelectric field effect transistor (FeFET) for nonvolatile memory application. We quantify ${V}_{\textsf {TH}}$ shift from electron (hole) trapping in the vicinity of ferroelectric (FE)/interlayer (IL) interface, induced by erase (program) pulse, and ${V}_{\textsf {TH}}$ shift from polarization switching to determine true memory window (MW). The devices exhibit extrapolated retention up to 10 years at 85 °C and endurance up to $5\times 10^{6}$ cycles initiated by the IL breakdown. Endurance up to 1012 cycles of partial polarization switching is shown in metal–FE–metal capacitor, in the absence of IL. A comprehensive metal–FE–insulator–semiconductor FeFET model is developed to quantify the electric field distribution in the gate-stack, and an IL design guideline is established to markedly enhance MW, retention characteristics, and cycling endurance.

An oscillator-based true random number generator (TRNG) is experimentally demonstrated by exploiting inherently stochastic threshold switching in the insulator-to-metal transition (IMT) in vanadium dioxide. Through experimentation and modeling, we show that the origin of stochasticity arises from small perturbations in the nanoscale domain structure, which are then subsequently amplified through a positive feedback process. Within a 1T1R oscillator, the stochastic cycle-to-cycle variations in the IMT trigger voltage result in random timing jitter, which is harnessed for a TRNG. The randomness of the IMT TRNG output is validated using the NIST SP800-22 statistical test.

In this work, we exploit the spatio-temporal switching dynamics of ferroelectric polarization to realize an energy-efficient, and massively-parallel in-memory computational primitive for at-node sensor data fusion and analytics based on an industrial 28nm HKMG FeFET technology [1]. We demonstrate: (i) the spatio-temporal dynamics of polarization switching in HfO 2 -based ferroelectrics under the stimuli of sub-coercive voltage pulses using experiments and phase-field modeling; (ii) an inherent rectifying conductance accumulation characteristic in FeFET with a large dynamic range of $G_{\max}/G_{\min} > 100$ in the case of 3.0V, 50ns gate pulses; (iii) transition to more abrupt accumulation characteristics due to single/few domain polarization switching in scaled FeFET (34nm L G ); and (iv) successful detection of physiological anomalies from realworld multi-modal sensor data streams.

In this work, we demonstrate a novel Hybrid-FeFET (H-FeFET) that leverages the threshold switching characteristics of Ag/HfO 2 to overcome the fundamental trade-off between memory window MW /read current ratio (I read,1 /I read,0 ) , and program voltage (V prog )/maximum electric-field in standard FeFETs for non-volatile memory application. The H-FeFET incorporates the threshold switch (TS) in the source of the FeFET, and is designed to exhibit a ferroelectric state-dependent volatile HRS to LRS transition (I ON /I OFF >107) – during read, the TS turns ON only if the FeFET is in the low-V T SET state, and remains OFF if the FeFET is in the high-V T RESET state, thus, selectively suppressing the RESET read current. Leveraging this principle, the H-FeFET: a Demonstrates 77% higher MW and 1000× larger I read,1 /I read,0 compared to the FeFET, at iso-V prog (DC); (b) Enables 25% reduction in V prog at iso-I read,1 /I read,0 during pulse operation-facilitated by the 8× improvement in I read,1 /I read,0 ; (c) Exhibits 2.5×reduction in programming power at iso-I read,1 /I read,0 in the H-FeFET-based AND array architecture, as shown by simulations. Thus, the H-FeFET overcomes the FeFET design challenges while retaining its existing advantages, making it a promising candidate for nonvolatile memory applications.

In this work, we report on the fabrication, characterization, and modeling of ferroelectric field-effect- transistors (FeFET). We demonstrate that polarization switching within ordinary 1T ferroelectric memory devices under specific conditions results in the measurement of subthreshold slopes $ , near-zero hysteresis, negative drain induced barrier lowering (N-DIBL), and negative differential resistance (NDR) (Fig. 1). The polarization switching origin is identified by a strong dependence on the magnitude of the gate voltage, where below the critical gate voltage required to switch polarization, $\mathrm{SS} , near-zero hysteresis, and negative DIBL cannot be observed. Further, we identify the source of NDR in the output characteristics to result from polarization switching near the drain of the FeFET at 10w $\mathrm{V}_{\mathrm{GS}}$ and high $\mathrm{V}_{\mathrm{DS}}$ . The NDR can be reproduced by a simple analytical model where two VT are present within the FeFET channel due to a non-uniform distribution of the polarization charge along the channel length. The intent of this work is to disambiguate and draw distinction between the effects of polarization switching in FeFET memory devices from that of negative capacitance as shown in Kwon et. al. [1], where a physically thicker oxide shows all the electric nronerties of a nhvsicallv thinner dielectric.

In this work we develop a compact model of ferroelectric field-effect-transistors (FeFET) for memory applications, enabling their exploration at the circuit and architecture level. In contrast to Landau-Khalatnikov (L-K) based approaches, the presented model is founded on the combination of a nucleation dominated multi-domain Presiach theory of ferroelectric switching with a conventional transistor model. The model successfully reproduces the evolution of the FeFET memory window as a function of the program and erase conditions (amplitude, pulse width, and history). To calibrate the model, we fabricated 10nm thick Hf 0.4 Zr 0.6 O 2 (HZO) MFM capacitors and FeFETs and characterized the polarization switching dynamics. Our results highlight the importance of accounting for the switching history, minor loop trajectory, and coupled time-voltage response of the ferroelectric to quantitatively reproduce the measured FeFET characteristics.

In this paper, we consider devices, circuits, and systems comprised of transistors with integrated ferroelectrics. Said structures are actively being considered by various semiconductor manufacturers as they can address a large and unique design space. Transistors with integrated ferroelectrics could (i) enable a better switch (i.e., offer steeper subthreshold swings), (ii) are CMOS compatible, (iii) have multiple operating modes (i.e., I-V characteristics can also enable compact, 1-transistor, non-volatile storage elements, as well as analog synaptic behavior), and (iv) have been experimentally demonstrated (i.e., with respect. to all of the aforementioned operating modes). These device level characteristics offer unique opportunities at the circuit, architectural, and system-level, and are considered here from device, circuit/architecture, and foundry-level perspectives.

The memory requirement of at-scale deep neural networks (DNN) dictate that synaptic weight values be stored and updated in off-chip memory such as DRAM, limiting the energy efficiency and training time. Monolithic cross-bar / pseudo cross-bar arrays with analog non-volatile memories capable of storing and updating weights on-chip offer the possibility of accelerating DNN training. Here, we harness the dynamics of voltage controlled partial polarization switching in ferroelectric-FETs (FeFET) to demonstrate such an analog synapse. We develop a transient Presiach model that accurately predicts minor loop trajectories and remnant polarization charge (P r ) for arbitrary pulse width, voltage, and history. We experimentally demonstrate a 5-bit FeFET synapse with symmetric potentiation and depression characteristics, and a 45x tunable range in conductance with 75ns update pulse. A circuit macro-model is used to evaluate and benchmark on-chip learning performance (area, latency, energy, accuracy) of FeFET synaptic core revealing a 103 to 106 acceleration in online learning latency over multi-state RRAM based analog synapses.

Artificial neural networks can harness stochasticity in multiple ways to enable a vast class of computationally powerful models. Electronic implementation of such stochastic networks is currently limited to addition of algorithmic noise to digital machines which is inherently inefficient; albeit recent efforts to harness physical noise in devices for stochasticity have shown promise. To succeed in fabricating electronic neuromorphic networks we need experimental evidence of devices with measurable and controllable stochasticity which is complemented with the development of reliable statistical models of such observed stochasticity. Current research literature has sparse evidence of the former and a complete lack of the latter. This motivates the current article where we demonstrate a stochastic neuron using an insulator-metal-transition (IMT) device, based on electrically induced phase-transition, in series with a tunable resistance. We show that an IMT neuron has dynamics similar to a piecewise linear FitzHugh-Nagumo (FHN) neuron and incorporates all characteristics of a spiking neuron in the device phenomena. We experimentally demonstrate spontaneous stochastic spiking along with electrically controllable firing probabilities using Vanadium Dioxide (VO$_2$) based IMT neurons which show a sigmoid-like transfer function. The stochastic spiking is explained by two noise sources - thermal noise and threshold fluctuations, which act as precursors of bifurcation. As such, the IMT neuron is modeled as an Ornstein-Uhlenbeck (OU) process with a fluctuating boundary resulting in transfer curves that closely match experiments. As one of the first comprehensive studies of a stochastic neuron hardware and its statistical properties, this article would enable efficient implementation of a large class of neuro-mimetic networks and algorithms., Added sectioning, Figure 6, Table 1, and Section II.E Updated abstract, discussion and corrected typos

Stochastic sampling machines (SSM) utilize neural sampling from probabilistic spiking neurons to escape local minima and prevent overfitting of training datasets [1]. This enables improved error rates compared to deterministic implementations, and, in turn, enables lower bit precision, decreased chip area, and reduced energy consumption. In this work, we experimentally demonstrate: (i) Insulator-to-Metal Phase Transition (IMT) neurons with record low peak operating power of 11.9μW at V DD =0.7V; (ii) the IMT in vanadium dioxide (VO 2 ) provides a natural probabilistic hardware substrate for realizing a compact stochastic IMT neuron for SSMs; (iii) implementation of SSM for pattern recognition on MNIST database [2] using experimentally calibrated device modeling. These results are compared to a 22nm CMOS ASIC which shows stochastic IMT neuron based SSMs result in a 4.5x reduction in system power consumption.

Random number generators (RNG) are a fundamental hardware component in modern cryptographic systems [1]. The generation of random numbers can be subdivided into two classes, pseudo-RNGs and hardware RNGs. In pseudo-RNGs software algorithms are implemented on deterministic hardware but are dependent on a set of initial values or “seed”, which reduces the security. In contrast, hardware RNGs generate random numbers from a naturally occurring physical phenomenon, such as thermal noise. However, implementations often suffer from large silicon footprints due to the need to create resistor-amplifier-ADC chains [2] or bias removal circuits [3]. In this work, we experimentally demonstrate a compact and scalable 1T1R based RNG by harnessing the inherent stochasticity in the insulator-to-metal phase transition (IMT) in vanadium dioxide (VO 2 ).

In this paper we review recent work on computational paradigms involving coupled relaxation oscillators built using metal-insulator-transition (MIT) devices. Such oscillators made using MIT devices based on Vanadium-Dioxide thin films are very compact and can be realized in hardware. Networks of such oscillators have interesting phase and frequency dynamics which can be programmed to solve computationally hard problems.

Two-dimensional materials are being investigated for potential nanoelectronic applications such as transistors for scaled technology nodes. Here we investigate the possibility of further augmenting the performance of such 2D materials through a novel device concept known as the hybrid-phase transition FET or Phase-FET. The MoS 2 based Phase-FET incorporates an insulator-to-metal transition material VO 2 integrated in series with the source of a MOSFET, which provides an internal amplification across the insulator-to-metal transition and results in steep slope switching.

We demonstrate a novel Ag/HfO 2 based threshold switch (TS) with a selectivity∼107, a high ON-state current (Ion) of 100 μA, and ∼10pA leakage current. The thresholding characteristics of the TS result from electrically triggered spontaneous formation and rupture of an Ag filament which acts an interstitial dopant in the HfO2 insulating matrix. Further, we harness the extreme non-linearity of the TS in (1) Selectors for Phase Change Memory (PCM) based cross-point memory. We show through array level simulations of a 1024kb memory, a read margin of 28% and write margin of 32% for a leakage power of ds ), and >10x Ion improvement over the conventional FET (at iso-I off ) at T=90C (50x at T=25C); making this a promising TS for both emerging memory, and steep-slope transistor applications.

In this paper we review recent work on novel computing paradigms using coupled oscillatory dynamical systems. We explore systems of relaxation oscillators based on linear state transitioning devices, which switch between two discrete states with hysteresis. By harnessing the dynamics of complex, connected systems we embrace the philosophy of "let physics do the computing" and demonstrate how complex phase and frequency dynamics of such systems can be controlled, programmed and observed to solve computationally hard problems. Although our discussion in this paper is limited to Insulator-to-Metallic (IMT) state transition devices, the general philosophy of such computing paradigms can be translated to other mediums including optical systems. We present the necessary mathematical treatments necessary to understand the time evolution of these systems and demonstrate through recent experimental results the potential of such computational primitives., Submitted to Journal of Nanophotonics for review

Coupled oscillators provide an efficient non-Boolean paradigm for solving a variety of computationally intensive problems in computer vision. This motivates the realization of large networks of low-power coupled oscillators. In this work, we experimentally demonstrate: (i) a relaxation oscillator based on the insulator-metal transition (IMT) in vanadium dioxide (VO 2 ) with record low DC input (peak) power of ∼23 µW; (ii) a network of coupled VO 2 oscillators with record number of elements (6 oscillators) which perform image processing functionalities in high dimensional space like color detection and morphological operations such as dilation and erosion). Calibrated simulations show that 10× reduction in power compared to a 32 nm CMOS accelerator at iso-throughput.

Spiking neural networks are expected to play a vital role in realizing ultra-low power hardware for computer vision applications [1]. While the algorithmic efficiency is promising, their solid-state implementation with traditional CMOS transistors lead to area expensive solutions. Transistors are typically designed and optimized to perform as switches and do not naturally exhibit the dynamical properties of neurons. In this work, we harness the abrupt insulator-to-metal transition (IMT) in a prototypical IMT material, vanadium dioxide (VO 2 ) [2], to experimentally demonstrate a compact integrate and fire spiking neuron [3]. Further, we show multiple spiking dynamics of the neuron relevant to implementing ‘winner take all’ max pooling layers employed in image processing pipelines.

Vanadium dioxide (VO 2 ), which exhibits electrically induced abrupt insulator-to-metal phase transition (IMT), is monolithically integrated with Silicon MOSFET to demonstrate a steep-slope (sub-kT/q) Phase-Transition FET (Phase-FET). The Phase-FET exhibits switching-slope (SS) of 8mV/decade leading to 36% increase in ON current (I ON ) over baseline MOSFET. We analyze the electrical characteristics of several threshold-switching materials with enhanced resistivity ratios (>105) beyond VO 2 and harness them to enhance the performance of 14nm node FinFETs. Our analysis shows that up to 2.9× increase in I ON , and 1.86× reduction in energy at (iso-delay) for an 11 stage ring oscillator (RO) is achievable with Phase FETs using Cu-doped HfO 2 threshold switches.

The switching dynamics of electrically driven insulator-to-metal transition (IMT) and metal-to-insulator transition (MIT) in vanadium dioxide are investigated. The transient response of time domain measurements are modeled using a domain based 2-D heterogeneous resistive network, taking into account local electronic potential and local Joule heating. It reveals, the switching time is dominated by a spatially non-uniform percolation of the metallic phase during the IMT driven by electro-thermal forces. We demonstrate an IMT switching time of 793ps in scaled VO 2 devices and project IMT and MIT switching speed for scaled devices.

Dense analog synaptic crossbar arrays are a promising candidate for neuromorphic hardware accelerators due to the ability to mitigate data movement by performing in-situ vector-matrix products and weight updates within the storage array itself. However, many analog weight storage cells suffer from long latencies or low dynamic ranges, limiting the achievable performance. In this work, we demonstrate that the voltage-controlled partial polarization switching dynamics in ferroelectric-field-effect transistors (FeFET) can be harnessed to enable a 32 state non-volatile analog synaptic weight cell with large dynamic range (67×) and low latency weight updates (50 ns) for an amplitude modulated pulse scheme.