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The material and electrical modification of HF-based dielectrics at different annealing conditions and different Si incorporations is investigated. The X-ray photoelectron spectroscopy (XPS) results have indicated a great signature of the formation of a HF-silicate layer.

In this study, key enabling technologies such as the oxide liner by the PECVD, the barrier and seed layers by the PVD, and Cu plating of blind TSVs on 300 mm wafers for 3D integration are investigated. Emphasis is placed on the determination and optimization of the important parameters for each of the key enabling technologies. Also, the leakage current of the fabricated Cu-filled TSVs is measured. Furthermore, cross sections and SEM of the fabricated TSVs are examined. [ABSTRACT FROM AUTHOR]

The etch rate of HfO2 etch processing has been feedback controlled in inductively coupled Cl2/N2/Ar plasmas. The ion current and the root mean square rf voltage on the wafer stage, which are measured using a commercial impedance meter connected to the wafer stage, are chosen as controlled variables because the positive-ion flux and ion energy incident upon the wafer surface are the key factors that determine the etch rate. Two 13.56 MHz rf generators are used to adjust the inductively coupled plasma power and bias power which control ion density and ion energy, respectively. The adopted HfO2 etch processing used rather low rf voltage. The ion-current value obtained by the power/voltage method is underestimated, so the neural-network model was developed to assist estimating the correct ion-current value. The experimental results show that the etch-rate variation of the closed-loop control is smaller than that of the open-loop control. However, the first wafer effect cannot be eliminated using closed-loop control and thus to achieve a constant etch rate, the chamber-conditioning procedure is required in this etch processing. [ABSTRACT FROM AUTHOR]

The etch selectivity of HfO2 to Si reported to date is poor. To improve the selectivity, one needs to either increase the etch rate of HfO2 or decrease the etch rate of Si. In this work, the authors investigate the etch selectivity of HfO2 in Cl2/N2 plasmas. In particular, the effects of in situ N2 plasma treatment of HfO2 and Si were investigated. The silicon substrate was exposed to nitrogen plasma and was nitrided, which was confirmed by x-ray photoelectron spectroscopy. The nitrided Si etching was suppressed in Cl2/N2 plasmas. The effectiveness of nitridation was studied with varying the plasma power, bias power, pressure, and N2 plasma exposure time. The results show that the etch resistance increased with increased power and decreased pressure. A minimum exposure time was required to obtain etch resistant property. The applied bias power increased the etch rate of Si substrate, so it should not be used during N2 plasma treatment. Fortunately, the etch rate of HfO2 was increased by the nitridation process. Therefore, HfO2/Si selectivity can be improved by nitridation and became higher than 5 under proper exposure condition. [ABSTRACT FROM AUTHOR]

The physical properties of HfO2 and Hf-silicate layers grown by the atomic layer chemical vapor deposition are characterized as a function of the Hf concentration and the annealing temperature. The peaks of Fourier transform infrared spectra at 960, 900, and 820 cm-1 originate from Hf-O-Si chemical bonds, revealing that a Hf-silicate interfacial layer began to form at the HfO2/SiO2 interface after postdeposition annealing process at 600°C for 1 min. Moreover, the intensity of the peak at 750 cm-1 can indicate the degree of crystallization of HfO2. The formed Hf-silicate layer between HfO2 and SiO2 is also confirmed by X-ray photoelectron spectroscopy. [ABSTRACT FROM AUTHOR]

The physical and reliability characteristics of strained-Si0.8Ge0.2 MOS capacitor and strained-Si0.7Ge0.3 MOSFET with Hf-based gate dielectrics prepared by atomic layer chemical vapor deposition are investigated. The thickness and composition of the gate dielectrics are measured by high-resolution transmission electron microscopy and X-ray photoelectron spectroscopy, respectively. The gate leakage current and interface traps of HfO2/Si1-xGex gate structure are slightly higher as compared to the HfO2/Si MOS devices, which is basically caused by the Ge at the interface. The electrical properties of both HfO2/Si and HfO2/Si1-xGex devices can be improved with increasing PDA temperature up to 800°C, which is due to the thicker interfacial layer grown at the interface, even though crystallization also grows with increasing temperature. However, with higher PDA temperature (>800°C), serious crystallization of HfO2 film causes more bulk traps induced electrical degradation. The electrical stress induced degradation of Si1-xGex substrate is slightly higher as compared to the control Si, due to more traps generations at the HfO2/Si1-xGex interface. For MOSFET, strained-Si1-xGex can effectively improve the drain current for about 20% at saturation and 69% at linear region. The higher gate leakage (Jg∼1.4×10-9A/cm2 at 2 V) and lower breakdown voltage (BD∼3.1 V) of Si0.7Ge0.3 pMOS devices are observed as compared to control Si devices (Jg∼7.9×10-12A/cm2 at 2 V and BD∼7.4 V). After the electrical stress, the degradation of drain current and transconductance and the shift of threshold voltage for Si1-xGex PMOSFET are larger than those for control Si devices, implying Ge induced trap generation at the Hf-silicate/Si1-xGex interface. [ABSTRACT FROM PUBLISHER]

Investigates a comprehensive study of plasma-charging effects on the electrical properties of metal oxide semiconductor (MOS) devices. Effect of plasma-induced charging on thin gate oxide in MOS devices; Effect of plasma charging on high dielectric constant material as gate insulator; Effect of shunt diode on the electrical properties for MOS transistors.

Operating properties of charge-trapping-type Flash memory devices with single or stacked structures on trapping layer are investigated in this letter. Improved operation and re- liability characteristics can be achieved by adapting the stacked high-k films as charge-trapping layer due to the modification in the trap density and the energy level of traps, the mechanism of electron/hole transmission, and the suitable band offset. Moreover, with a small bandgap of second film in the stacked trapping layer, operating characteristics of devices are further enhanced. [ABSTRACT FROM AUTHOR]

A novel method of fabricating HfOx-based resistive memory device with excellent nonvolatile characteristics is proposed. By using a thin AlCu layer as the reactive buffer layer into the anodic side of a capacitor-like memory cell, excellent memory performances, which include reliable programming/erasing endurance (> 105 cycles), robust data retention at high temperature, and fast operation speed (< 50 ns), have been demonstrated. The resistive memory based on AlCu/HfOx stacked layer in this letter shows promising application in the next generation of non-volatile memory. [ABSTRACT FROM AUTHOR]

Unipolar resistive switching behaviors of Ru/HfOx/TiN devices with Ru as anode were investigated. Wide dispersion of switching operation parameters was observed. The conduction mechanisms in low and high resistance states of the devices were characterized to be Ohmic-like and tunneling, respectively. The band offset of the Ru/HfOx interface was extracted from the measured tunneling current versus voltage characteristics. Instability of the band offset at the anodic interface was observed and may be responsible for the wide fluctuation of the operation voltage in the Ru/HfOx/TiN device at a high resistance state. The possible mechanism for these unstable characteristics of band offset at the Ru/HfOx interface is also discussed. [ABSTRACT FROM AUTHOR]

The bias polarity-dependent inelastic electron tunneling spectroscopy is employed to detect the thermal stability of the Ta–Pt/SiO2/Si and Ta–Pt/HfO2/Si structures. This work provides a direct evidence that the Fermi-level pinning of metal gates is counted for the generation of extrinsic states due to interface interaction. A Ta2O5 layer forms at the Ta–Pt/SiO2 interface during thermal annealing whereas only an intermittent Ta–O bond is observed at the Ta–Pt/HfO2 interface. Although the heat of formation of HfO2 is lower than that of SiO2, Si presumably diffuses into HfO2 layer and replaces Hf atoms during the high-temperature annealing. [ABSTRACT FROM AUTHOR]