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When a local oscillator signal generation system is based on an LC oscillator and a frequency multiplier, the question of determining the optimal multiplication factor is a key issue. In this paper, the problem is addressed in order to minimize the 1/ f2 phase noise within a tuning range constraint. The analysis, with a practical graphical representation, reveals the oscillator phase noise dependence on the oscillating frequency in the transition from two different regimes, named the inductor-limited quality factor and the capacitor-limited quality factor. The results obtained enable the evaluation of the phase noise performance of systems based on a sub-harmonic and super-harmonic oscillators and how they compare with an oscillator in the fundamental mode. Crucial questions like the phase noise improvement that these systems can achieve are analytically answered. A design methodology is thus proposed and verified through measurements on a frequency source at 31 GHz, composed by a sub-harmonic voltage-controlled oscillator followed by an injection-locked frequency tripler, dedicated to backhauling applications, designed on a BiCMOS process technology. The tuning range is 10%, and the phase noise at a 1-MHz offset is −112 dBc/Hz. Copyright © 2017 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

In this article, an original method to design silicon-integrated fully differential three-branch channelized filters is described. These filters are based on first-order recursive bandpass filter stages. Frequency-tunable responses exhibiting one or two transmission zeros and one or two passbands have been achieved. © 2006 Wiley Periodicals,Inc. Microwave Opt Technol Lett 48:2028–2032, 2006; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.21857 [ABSTRACT FROM AUTHOR]

The design of a 500 MHz oscillator in a 65 nm CMOS process using a 2 GHz bulk acoustic wave (BAW) resonator is presented. A digital frequency control is implemented using a switched capacitor bank in parallel to the resonator. The tuning range is up to 500 kHz with a minimum step of 200 Hz. The oscillator core uses a differential topology and is designed for low phase noise (-128 dBc/Hz at 100 kHz offset) at low power consumption (0.9 mW). It is followed by a low-noise divider, which provides a 500 MHz output with a phase noise of -139 dBc/Hz at 100 kHz offset from the carrier. [ABSTRACT FROM AUTHOR]

An accurate, continuous-time, active IC filter based on G[sub m]-C integrators dedicated to the design of high dynamic range, low-oversampling ratio (OSR) continuous-time (CT) sigma-delta (ΣΔ) modulators is presented. Despite temperature and process variations, the biasing technique used enables design of a constant G[sub m]-C cell without additional tuning circuit. A zero-IF (ZIF) receiver has been designed integrating I (in-phase) and Q (quadrature-phase) ΣΔ modulators. The measured peak SNR for a single modulator is 82.5 dB in temperature range [-30°C, +85°C]. Its power consumption, including I and Q modulators, biasing circuitry and delay-locked loop is 7.25 mW under 2.5 V. [ABSTRACT FROM AUTHOR]

A full-wave analysis extending the transverse resonance technique to inhomogeneous stacks is considered to investigate coupling effects in typical BiCMOS structures. Dependences of crosstalk on the presence of buried epitaxial layers (BEL), the line spacing and the substrate thickness are presented. The use of low-resistivity localised diffusions to interrupt BEL yields significant isolation improvement. [ABSTRACT FROM AUTHOR]

An integrated LC-VCO using an 8-shaped inductor for reduced EM radiation is presented. A low phase noise is measured at 1 MHz offset ranging from -134 to -128 dBc/Hz for carrier frequencies from 2.9 to 3.47 GHz, respectively. The coil is implemented with a double aluminium metal layer and presents a measured quality factor Q>20 at 3 GHz. The circuit is realised in a 40 GHz-fT 0.25 µm BiCMOS technology. Power consumption is about 13.5 mW from a 1.8 V regulated supply voltage. [ABSTRACT FROM AUTHOR]

A new way of designing a 14-bit pipeline analogue-to-digital converter is described. Combined gain calibration and capacitor mismatch correction permit limiting power consumption and achieve a differential nonlinearity of 0.25LSB in a low-cost digital CMOS process (0.18 µm). [ABSTRACT FROM AUTHOR]