40 results on '"Breuil, L."'
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2. Rare-earth aluminates as a charge trapping materials for NAND flash memories: Integration and electrical evaluation
3. Optimization of gate stack parameters towards 3D-SONOS application
4. Effect of high temperature annealing on tunnel oxide properties in TANOS devices
5. A Novel Ni-Al Alloy Metal Induced Lateral Crystallization Process for Improved Channel Conduction in 3-D NAND Flash.
6. High-k dielectrics for hybrid floating gate memory applications
7. Lateral Distribution of Electrons Trapped in Nitride Layers
8. Scaling effects in dual-bit split-gate nitride memory devices
9. Impact of Charge Trapping and Depolarization on Data Retention Using Simultaneous P – V and I – V in HfO₂-Based Ferroelectric FET.
10. Defect profiling in FEFET Si:HfO2 layers.
11. Improvement of Poly-Si Channel Vertical Charge Trapping NAND Devices Characteristics by High Pressure D2/H2 Annealing.
12. Intrinsic electron traps in atomic-layer deposited HfO2 insulators.
13. Electron energy distribution in Si/TiN and Si/Ru hybrid floating gates with hafnium oxide based insulators for charge trapping memory devices.
14. Integration of a multi-layer Inter-Gate Dielectric with hybrid floating gate towards 10nm planar NAND flash.
15. A novel multilayer Inter-Gate Dielectric enabling up to 18V Program / Erase window for planar NAND flash.
16. High Performance THANVaS Memories for MLC Charge Trap NAND Flash.
17. Novel Bi-Layer Poly-Silicon Channel Vertical Flash Cell for Ultrahigh Density 3D SONOS NAND Technology.
18. Understanding the impact of metal gate on TANOS performance and retention.
19. Investigation of rare-earth aluminates as alternative trapping materials in Flash memories.
20. Optimization of the crystallization phase of Rare-Earth aluminates For blocking dielectric application in TANOS type flash memories.
21. O2 post deposition anneal of Al2O3 blocking dielectric for higher performance and reliability of TANOS Flash memory.
22. Experimental evaluation of trapping efficiency in silicon nitride based charge trapping memories.
23. Advantages of the FinFET architecture in SONOS and Nanocrystal memory devices.
24. Enabling Transparent Data Sharing in Component Models.
25. Comparative reliability investigation of different nitride based local charge trapping memory devices.
26. Lanthanide Aluminates as Dielectrics for Non-Volatile Memory Applications: Material Aspects.
27. Hybrid Floating Gate Cell for Sub-20-nm NAND Flash Memory Technology.
28. Highly Scaled Vertical Cylindrical SONOS Cell With Bilayer Polysilicon Channel for 3-D nand Flash Memory.
29. Validation of Retention Modeling as a Trap-Profiling Technique for SiN-Based Charge-Trapping Memories.
30. Investigation of Window Instability in Program/Erase Cycling of TANOS NAND Flash Memory.
31. Nitride Engineering for Improved Erase Performance and Retention of TANOS NAND Flash Memory.
32. Improvement of TANOS NAND Flash Performance by the Optimization of a Sealing Layer.
33. A Consistent Model for the SANOS Programming Operation.
34. Physical Understanding of SANOS Disturbs and VARIOT Engineered Barrier as a Solution.
35. Nitride based FinFLASH memory device using multilevel Hot Carrier Program/Erase.
36. Stacked-etch induced charge loss in Hybrid Floating Gate cells using high-κ Inter-Gate Dielectric.
37. Defects characterization of Hybrid Floating Gate/Inter-Gate Dielectric interface in Flash memory.
38. Instability study of high-κ Inter-Gate Dielectric stacks on hybrid floating gate flash memory.
39. Ultra thin hybrid floating gate and high-k dielectric as IGD enabler of highly scaled planar NAND flash technology.
40. Optimization of inter-gate-dielectrics in hybrid float gate devices to reduce window instability during memory operations.
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