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In this letter, a Ni-Al alloy based metal induced lateral crystallization (MILC) process in a vertical Si channel, from 3-D NAND flash cell, is reported. Alloying Ni with Al improves NiSi2 nucleation, resulting in a favorable channel morphology after the silicide transport. We show that it is possible to achieve better ON-current and gate control over the existing Ni-only MILC process with no observable impact on the memory performance. [ABSTRACT FROM AUTHOR]

The ferroelectric (FE)-HfO2-based field-effect transistor (FEFET) is a promising candidate for emerging memory. However, data retention (DR) loss has been flagged as a key issue. Although two models of DR loss in FEFET have been proposed—the charge trapping model and the depolarization model—it is difficult to separate the dominant cause. In this article, simultaneous ${P}$ – ${V}$ and ${I}$ – ${V}$ measurements are performed which enable separation of these mechanisms. Different behavior of polarization and threshold voltage loss and recovery in a “set” state between two types of FEFET structures, metal (TiN)/FE-HfO2/SiO2/Si substrate (MFIS) and metal (TiN)/Si/FE-HfO2/SiO2/Si-substrate (MSFIS), clarify that the dominant mechanism of the DR loss in both structures is different. In addition, the impact of external bias and interfacial layer (IL) on the DR loss is revealed: the polarization loss is strongly affected by the external bias in both types of FEFET, indicating effective work function (eWF) has a strong impact on depolarization. On the other hand, the thickness and processing of IL strongly impact the charge trapping characteristics. Based on our understanding, excellent improvement of the DR is achieved: memory window ~0.8 V at 85 °C, extrapolated to ten years. [ABSTRACT FROM AUTHOR]

Ferroelectric Si-doped HfO2 is a promising candidate for future generation memory devices. However, such devices are vulnerable to significant threshold voltage shifts resulting from charge trapping in oxide defects. We use complementary characterization and modeling techniques to reveal significant electron trapping/de-trapping behavior, together with a strong temperature dependence of the electron emission kinetics in ferroelectric layers, which results from the onset of polarization of the ferroelectric layer. This can lead to an apparent difference in the defect characteristics in ferroelectric-HfO2 compared to the paraelectric-HfO2 structures they are shown to closely resemble when this contribution is decoupled. The results demonstrate the presence of a defect band closely aligned to the silicon conduction band, which can easily be accessed during device operation. [ABSTRACT FROM AUTHOR]

Analysis of photodepopulation of electron traps in HfO2 films grown by atomic layer deposition is shown to provide the trap energy distribution across the entire oxide bandgap. The presence is revealed of two kinds of deep electron traps energetically distributed at around Et ≈2.0 eV and Et ≈3.0 eV below the oxide conduction band. Comparison of the trapped electron energy distributions in HfO2 layers prepared using different precursors or subjected to thermal treatment suggests that these centers are intrinsic in origin. However, the common assumption that these would implicate O vacancies cannot explain the charging behavior of HfO2, suggesting that alternative defect models should be considered. [ABSTRACT FROM AUTHOR]

Scaling the planar NAND flash cells to the 20 nm node and beyond mandates introduction of inter-gate insulators with high dielectric constant ( κ). However, because these insulators provide a smaller electron barrier at the interface with the poly-Si floating gate, the program window and the retention properties of these scaled cells are jeopardized. To reduce the charge loss from the floating to the control gate, one may consider the introduction of a hybrid floating gate (HFG) structure comprised of poly-Si and a high work function (WF) metal, e.g., TiN x ( x ∼ 1; WF ∼ 4.7 eV) or Ru (WF ∼ 5.3 eV). However, the very HFG concept is based on the assumption that electron trapping occurs inside the HFG stack rather than on traps present in the high- κ insulator. To examine this critical hypothesis, we analyzed the energy distribution of electrons trapped in flash cells with poly-Si(2 nm)/TiN (6 nm)/Hf0.8Al0.2O x(19 nm, κ ∼ 15-19)/TiN x (10 nm) and Si(2 nm)/Ru (1 nm)/Hf0.8Al0.2O x(5 nm)/Al2O3 (5 nm)/Hf0.8Al0.2O x (5 nm)/TiN x (10 nm) trapping gate stacks using the exhaustive photo-depopulation spectroscopy. We found that trapped electron energy levels show a broad distribution (± 0.3 eV) centred at ∼3.2 eV below the oxide conduction band. The energy onset of electron de-trapping at ∼2.8 eV matches the TiN x/HfO2 barrier height found from internal photoemission experiments, indicating that electrons are predominantly trapped inside the HFG. [ABSTRACT FROM AUTHOR]

The lanthanide aluminates GdAlO3 and LuAlO3 have been examined for integration into advanced non-volatile memory devices. From a materials point of view, a number of physical properties of the material need to be understood prior to successful device integration, such as e.g. band gap, dielectric permittivity, or crystallization behavior. In addition to these material properties, the layers may have to withstand high thermal budgets during device processing such that thermal stability and interdiffusion in contact with surrounding materials become important. [ABSTRACT FROM AUTHOR]

The hybrid floating gate (FG) concept, previously demonstrated in FG capacitors, has been proven in fully integrated stacked memory cells. Results not only confirm the high potential of the concept in terms of improved program performance, but also show excellent data retention and program/erase cycling endurance. Key for achieving this result has been the optimization of the sidewall and spacer processing. Hybrid FG cells are therefore a viable solution to extend the nand Flash memory roadmap below the 20-nm technology node. [ABSTRACT FROM AUTHOR]

A vertical cylindrical SONOS cell with a novel bilayer polysilicon channel down to 22-nm diameter for 3-D nand Flash memory is successfully developed. We introduce a thin amorphous silicon layer along with the oxide–nitride–oxide (ONO) gate stack inside the memory hole. This silicon layer protects the tunnel oxide during opening of the gate stack at the bottom of the memory hole, after which it serves as the first layer of the bilayer polysilicon channel. This approach enables the 3-D architecture to achieve minimum cell area (\4F^2, with F being the feature size) without the need for the so-called pipeline connections. The smallest functional cells have the memory hole diameter F = \45 \ \nm, resulting in 22-nm channel diameter. In case 16 cells are stacked, F = \45 \ \nm would correspond to an equivalent 11-nm planar cell technology node. Excellent program/erase and retention obtained with the all-deposited ONO stack are demonstrated. [ABSTRACT FROM PUBLISHER]

We applied the recently developed trap spectroscopy by charge injection and sensing to validate the extraction of the silicon nitride trap distribution (both in space and energy) from the modeling of retention transients of charge-trapping memories. We compared three different types of silicon nitrides using these two techniques, and similar distributions were extracted, thus confirming the validity of the charge profiles resulting from the modeling of retention transients and the physics of the proposed model, based on two main mechanisms of charge loss: Poole-Frenkel emission (dominating at high temperature) and direct tunneling (dominating at room temperature). [ABSTRACT FROM AUTHOR]

High-k dielectric stacks have been used in the 20 nm generation of floating gate (FG) flash memory cells. However, electron trapping in high-k materials remains a major concern for further development of FG technology. The hybrid FG (HFG) device with high-k inter-gate-dielectric (IGD) is a promising candidate with advantages of larger windows and less cell-to-cell interference, in which the poly floating gate is replaced by an n-poly/p-metal bi-layer structure. In this paper, to continue our previous work, the window instability in HFG with engineered IGD stacks during memory operations has been extensively studied. The results show that the HFG cell with the HAH (HaH) IGD structure provides not only the largest window but also the least instability, making it a suitable candidate beyond the 1× nm flash technology node. [ABSTRACT FROM AUTHOR]