Optimization of inter-gate-dielectrics in hybrid float gate devices to reduce window instability during memory operations.

High-k dielectric stacks have been used in the 20 nm generation of floating gate (FG) flash memory cells. However, electron trapping in high-k materials remains a major concern for further development of FG technology. The hybrid FG (HFG) device with high-k inter-gate-dielectric (IGD) is a promising candidate with advantages of larger windows and less cell-to-cell interference, in which the poly floating gate is replaced by an n-poly/p-metal bi-layer structure. In this paper, to continue our previous work, the window instability in HFG with engineered IGD stacks during memory operations has been extensively studied. The results show that the HFG cell with the HAH (HaH) IGD structure provides not only the largest window but also the least instability, making it a suitable candidate beyond the 1× nm flash technology node. [ABSTRACT FROM AUTHOR]