Cite
Optimization of inter-gate-dielectrics in hybrid float gate devices to reduce window instability during memory operations.
MLA
Tang, B. J., et al. “Optimization of Inter-Gate-Dielectrics in Hybrid Float Gate Devices to Reduce Window Instability during Memory Operations.” Microelectronics Reliability, vol. 54, no. 9/10, Sept. 2014, pp. 2258–61. EBSCOhost, https://doi.org/10.1016/j.microrel.2014.07.087.
APA
Tang, B. J., Zhang, W. D., Breuil, L., Robinson, C., Wang, Y. Q., Toledano-Luque, M., Van den Bosch, G., Zhang, J. F., & Van Houdt, J. (2014). Optimization of inter-gate-dielectrics in hybrid float gate devices to reduce window instability during memory operations. Microelectronics Reliability, 54(9/10), 2258–2261. https://doi.org/10.1016/j.microrel.2014.07.087
Chicago
Tang, B.J., W.D. Zhang, L. Breuil, C. Robinson, Y.Q. Wang, M. Toledano-Luque, G. Van den Bosch, J.F. Zhang, and J. Van Houdt. 2014. “Optimization of Inter-Gate-Dielectrics in Hybrid Float Gate Devices to Reduce Window Instability during Memory Operations.” Microelectronics Reliability 54 (9/10): 2258–61. doi:10.1016/j.microrel.2014.07.087.