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This paper proposes a curve extraction method for I-V curves and analog figures-of-merit of self-cascode MOSFET associations (SC) using a code that exploits I-V curves of single transistors as input. The method was validated by using experimental measurements of fabricated SC and the very single transistors that compose them. The results indicate a very low error between the SC generated by the code and the measured reference for operation in saturation regime and above threshold voltage, for both the I-V curves and their derivatives. This method is then valid for the assessment of the SC structures in new technologies, avoiding experimental dedicated layouts or complex setups.

This paper presents an experimental analysis of the analog characteristics of self-cascode structures composed by 28 nm technological node ultra-thin body and BOX fully-depleted silicon-on-insulator planar MOSFETs, focusing on the subthreshold operation regime. Apart from the increased gain promoted by the reduction of front gate voltage, there is further improvement when the back-gate bias is used to reduce the threshold voltage of transistor close to the drain of the composite device, making this structure a promising option for low-power low-voltage (LPLV) analog applications.

This paper showcases SPICE simulated results of single transistors and self-cascode (SC) associations of UTBB transistors from 28FDSOI technology by ST-Microelectronics with a focus on analog integrated circuit design. This comparison demonstrates significant improvement of the voltage gain for the SC association without compromising the transconductance, especially when featuring asymmetric threshold voltages (Asymmetric Self-Cascode – A-SC).

This paper assesses the DC analog performance of a composite transistor named Asymmetric Self-Cascode structure, which is formed by two Fully Depleted SOI nMOSFETs connected in series with shortened gates. The in-fluence of geometrical parameters, such as different channel widths and lengths on the transistors at source and drain sides is evaluated through three-dimensional numerical simulations, which have been firstly adjusted to the experimental measure-ments. The transconductance, output conductance, Early volt-age and intrinsic voltage gain have been used as figures of merit to explore the advantages of the composite transistor. From the obtained results, the largest intrinsic voltage gain has been ob-tained by using longer channel lengths for both transistors, with narrower device close to the source and wider transistor near to the drain.

In this paper, the linearity of the Asymmetric Self-Cascode composed by Fully Depleted SOI nMOSFETs is experimentally evaluated, using transistors with different channel lengths. The abnormal (flat) transconductance of this composite transistor is used to promote a linearity enhancement. Disregarding the gain, the minimum harmonic distortion for low-power low-voltage applications has been obtained for the shortest transistor near the source and longest transistor near the drain.

This paper aims at demonstrating, for the first time, the use of back bias to improve the analog performance of current mirrors composed by self-cascode structures with 25 nm-long n- and p-type UTBB SOI MOSFETs. The use of back gate bias has shown to enhance the intrinsic gain of p-type devices by about 7 dB, making it higher than the one from a single device with equivalent channel length whereas the mirroring precision has shown to be improved by 20 % with respect to single devices.

In this paper the origin of low-frequency noise in the Asymmetric Self-Cascode (A-SC) structure composed by Fully Depleted SOI nMOSFETs is investigated through experimental results. It is shown that the predominant noise source of the A-SC structure is linked to carrier number fluctuations, being governed by the noise generated in the transistor near the source. Larger channel doping concentrations degrade the quality of the Si-SiO2 interface and the gate oxide, which causes an increase of the normalized drain current noise spectral density, just as the reduction of the gate voltage overdrive, since there are few carriers in the channel. The A-SC structures have showed higher noise compared with single transistors. In saturation regime, the increase of the gate voltage overdrive has incremented the corner frequency, shifting the g-r noise to higher frequencies. Besides that, the normalized noise has been significantly increased when compared with the linear regime due to the rise of the drain current noise spectral density.

This paper presents an experimental study of mismatching on the analog characteristics of fully-depleted graded-channel SOI MOSFET in comparison to uniformly doped transistors. The study is carried out using dedicated structures to account for the mismatch that have been fabricated at the same chip and with the same technology. Important basic parameters such as threshold voltage and subthreshold slope were analyzed as well as analog parameters, namely transconductance, output conductance, Early voltage and intrinsic voltage gain.

In this paper, the analog performance of the Asymmetric Self-Cascode structure of Fully Depleted SOI nMOSFETs has been evaluated with regards to the variation of channel width, through three-dimensional numerical simulations. The largest gain has been obtained using the narrowest transistor near the source and the widest transistor near the drain.

The aim of this work is to analyze the operation of junctionless nanowire transistors down to the liquid helium temperature. The drain current, the transconductance, the output conductance, the subthreshold slope, the threshold voltage and the interface trap density are the key parameters under analysis, which has been performed through experimental results together with simulated data. Oscillations in the transconductance and output conductance have been observed in the experimental results of junctionless devices for temperatures lower than 77 K. The experimental drain current curves also exhibited a 'drain threshold voltage' for the lower temperatures. The impact of the source/drain contact resistance and discrete trap levels has been analyzed by means of simulations.

This work presents a highly linear temperature sensors implemented with SOI Lateral PIN Diodes, for low-power applications, biased on the exponential region of the I-V characteristics. Experimental results are shown for temperatures ranging between 150 K and 400 K, showing that depending on the selected bias currents, the linearity can be improved in comparison to a single SOI PIN diode. Simulations results show that the sensing range can be extended for both lower and higher temperatures maintaining high linearity.

This paper compares the performance of Asymmetric Self-Cascode and Graded-Channel SOI nMOSFETs, both proposed to improve the analog performance of fully depleted SOI nMOSFETs. The differences at device level are evaluated and the impact of their application in basic analog circuits, i.e. common-source amplifier, source-follower and common-source current mirror are explored through experimental results.

This paper reports, for the first time, the use of back gate bias to improve the intrinsic voltage gain of self-cascode structures composed by planar FD and UTBB SOI MOSFETs. It is shown a voltage gain improvement larger than 10 dB when either a forward back bias is applied to the drain-side transistor or a reverse back bias is applied to the source side device.

The aim of this work is to analyze the operation of Junctionless Nanowire Transistors at liquid helium temperature, focusing the operation at linear regime. The drain current, the transconductance, the low field mobility, subthreshold slope, the interface trap density and the channel resistance are the key parameters under analysis.

This work assesses the analog performance of Graded-Channel FD SOl nMOSFET transistors regarding the dependence of gate voltage overdrive over the length of lightly doped region which maximizes the intrinsic voltage gain, unit gain frequency and breakdown voltage. It is shown that the optimum length of lightly doped region depends on the target application of GC devices.

This paper presents an analysis on the linearity of Asymmetric Self-Cascode (A-SC) of FD SOI nMOSGET transistors at cryogenic temperatures. This is achieved by evaluating experimental results of associations of transistors with various combinations of channel doping, obtained at temperatures ranging between liquid helium temperature (LHT, 4K) and room temperature (300K). It has been observed that A-SC presents better analog characteristics than the Symmetric Self-Cascode (S-SC) even at temperatures below 100K. The results show improved harmonic distortion at cryogenic temperatures and for structures composed by transistors with lower channel doping.

This paper presents an analysis on the linearity of Asymmetric Self-Cascode (A-SC) of FD SOI nMOSGET transistors at cryogenic temperatures. This is achieved by evaluating experimental results of associations of transistors with various combinations of channel doping, obtained at temperatures ranging between liquid helium temperature (LHT, 4K) and room temperature (300K). It has been observed that A-SC presents better analog characteristics than the Symmetric Self-Cascode (S-SC) even at temperatures below 100K. The results show improved harmonic distortion at cryogenic temperatures and for structures composed by transistors with lower channel doping.

This paper presents an experimental analysis of the harmonic distortion of asymmetric self-cascode (A-SC) association of SOI transistors. This goal is achieved by comparing the A-SC to the symmetric self-cascode (S-SC) configuration with different channel lengths. The non-linearity data have been obtained by applying the Integral Function Method to experimental measurements, for the evaluation of the total and third-order harmonic distortion. The results show that the asymmetric self-cascode provides lower total harmonic distortion than S-SC for all studied channel length associations. If a target distortion level is fixed, the A-SC enables an increase of input signal amplitude. On the other hand, smaller input signal amplitude and distortion are verified in the A-SC when fixing the output amplitude.

This paper aims at analyzing, through two-dimensional numerical simulations and experimental results, the influence of technological parameters downscaling on the analog performance of Graded-Channel FD SOI nMOSFET transistors. Front gate oxide and silicon film thicknesses, channel doping concentration, total channel and lightly doped region lengths have been varied to target the highest intrinsic voltage gain.

In this work a comparison between the performance of current mirrors implemented with uniformly doped and graded-channel (GC) transistors operating down to low temperature (150 K) is presented. This analysis has been carried out through experimental measurements of Common-source, Cascode and Wilson current mirrors architectures. The advantages of the use of graded-channel transistors for implementation of current mirrors in comparison to standard ones is discussed, focusing on the increase of output swing and output resistance. In all architectures some performance degradation has been observed with the temperature reduction, although current mirrors with GC transistors still present better performance than those implemented with standard SOI transistors. Two-dimensional numerical simulations were performed in order to further investigate the behavior of graded-channel current mirrors, looking at the bias condition of each transistor in the current mirror architectures. The obtained results indicate that good performance, compared to that of GC current mirrors, may be obtained by combining both standard and graded-channel transistors, rather than using the same channel engineering for all devices in the circuit.

In this paper the analog performance of Graded-Channel (GC) SOI nMOSFETs with deep submicrometer channel length is presented. Experimental data of GC transistors fabricated in an industrial 150 nm fully-depleted SOI technology from OKI Semiconductors were used to adjust the two-dimensional numerical simulations, in order to analyze the devices analog behavior by extrapolating their physical parameters. The obtained results show that the larger intrinsic voltage gain improvement occurs when the length of the lightly doped region is approximately 100 nm regardless the total channel length, doping concentration and temperature.

This paper presents an experimental analysis of channel length influence on the analog characteristics of asymmetric self-cascode association of SOI transistors. It is shown that the increase of the drain current and transconductance is more pronounced with the reduction of the length of the transistor close to the source (L1), and, differently from the symmetric self-cascode, suffers little influence of the length close to the drain (L2). On the contrary, the output conductance of symmetric and asymmetric threshold voltage structures is benefited by the increase of L2 and L1, although the asymmetric structure may offer a reduction of up to one order of magnitude in comparison to the symmetric one. It results in larger intrinsic voltage drain for asymmetric devices. This increase has shown to reach more than 20 dB for similar dimensions, or allow for dimension reduction without intrinsic gain degradation.

The origin of the low-frequency noise in submicron fully depleted Graded-Channel (GC) SOI MOSFET is investigated in terms of the channel length comparing two different technologies, OKI semiconductors and UCL.

This paper aims to demonstrate the performance of GC SOI MOSFET devices in comparison to standard SOI MOS transistors, comparing the improvements achieved by the adoption of the GC architecture in a submicron fully depleted SOI technology varying the channel length. The results obtained by two-dimensional numerical simulations show that the best improvement is obtained when the length of lightly doped region length is approximately 100 nm, independently of the total channel length.

Fully Depleted (FD) SOI technology is well known to provide improved analog performance of CMOS transistors [1, 2]. However, FD SOI transistors may suffer from parasitic bipolar effects (PBE) that cause the degradation of the output conductance [3]. The use of cascode transistors with common gate (making a self-cascode – SC topology) has been shown to reduce the output conductance of MOSFETs, while keeping some advantages of long-channel transistors [4]. Fig. 1 represents the self-cascode transistor, composed by transistors MS and MD, with channel lengths LS and LD, and threshold voltages VT,S and VT,D, respectively (with VT,S = VT,D in the symmetric SC– S-SC).Recent works [5, 6] showed that the use of different threshold voltages (VT) for MS and MD (so-called asymmetric self-cascode – A-SC) is able to further enhance the analog properties of SC n- and pMOS transistors, in comparison to the S-SC, at room temperature (RT). In this paper the enhanced analog performance of asymmetric SC structure is experimentally demonstrated at deep cryogenic environments emphasizing its capability to minimize (or even suppress) PBE in FD SOI n- and p-type MOSFETs at liquid helium temperature (LHT), where this effect is more pronounced.

This work reports, for the first time, the operation of Graded-Channel SOI nMOSFETs at liquid helium temperature. As expected, for all measured devices it has been observed that at 4.2K the transconductance increases with respect to room temperature as a consequence of the mobility rise. On the opposite hand, all the studied devices demonstrated a degradation of the output conductance with temperature reduction. However, this degradation is attenuated below 90K. As a consequence, an increase of the Early voltage and of the intrinsic voltage gain were obtained, in contrast to the data reported in the literature, for devices operating down to 100K. It is demonstrated that GC SOI presented larger Early voltage increase at 4.2K than at room temperature. The rise of the voltage gain promoted by GC architecture has shown to be constant with temperature down to 4.2K.

We propose the use of an alternative multi-exponential model to describe multiple conduction mechanisms in thin-film SOI PIN diodes with parasitic series resistance over a wide operating temperature range, from 90 to 390 K. This alternative multi-exponential model can be used for semiconductor junctions which exhibit multiple conduction mechanisms with series and shunt resistances. Using Thevenin’s theorem and the Lambert W function, the terminal current is expressed explicitly as a function of the terminal voltage. Its explicit nature allows higher computational efficiency and makes this model better suited for repetitive simulation applications than conventional implicit models. Additionally, direct analytic differentiation and integration are possible. This alternative model is used to describe the I-V characteristics of real SOI PIN diodes.

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This work presents an analysis of the analog performance of asymmetric threshold voltage self-cascode fully depleted (FD) p-type SOI transistors. The experimental results showed that this structure is able to improve the devices transconductance and output conductance, resulting in increased intrinsic voltage gain and breakdown voltage in comparison to single transistors and the conventional symmetric self-cascode.

In this work the low temperature performance of ultra-low-power SOI CMOS diodes is presented. Experimental measurements performed in fabricated devices from 148K to 373K show that the temperature lowering can promote a significant leakage current reduction and increase of the forward current. Two-dimensional numerical simulations are used to extend the studied temperature range and analyze the doping concentration influence on the low temperature operation of these diodes.

This work presents an analysis of the temperature influence on the performance of a lateral thin-film SOI PIN photodiodes when illuminated by low wavelengths, in the range of blue and ultra-violet (UV). Experimental measurements performed from 100K to 400K showed that the optical responsitivity of SOI PIN photodetectors is affected by temperature change, being reduced at low and moderately high temperatures. Two-dimensional numerical simulations showed the same trends as in the experimental results, and were used both to investigate the physical phenomena responsible for the observed behavior as a function of the temperature as well as to predict the influence of silicon film thickness downscaling on the photodetector performance.

A recent work showed that gD of long-channel self-cascode transistors can be further reduced by replacing M2 with a transistor with intrinsic concentration in the channel. In order to extend this proposal to more recent technologies, the current work presents an analysis of short-channel asymmetric self-cascode transistors implemented using a multi-threshold voltage commercial process. Numerical simulations were also performed aiming to extend the study, searching for the optimal doping concentration and length for M1 and M2.

A global lateral fitting procedure is proposed to extract the parameters of quadratic double exponential junction models in the presence of parasitic series resistance. Error analysis of the extracted parameters values within a large representative family of synthetic data indicate excellent match between the extracted values and a wide range of the original given model parameters. The procedure was also tested on real data to extract the model parameters of an experimental Silicon PIN diode measured at cryogenic temperature.

This work studies the operation of source-follower buffers implemented with standard and graded-channel (GC) fully depleted (FD) SCI nMOSFETs at low temperatures. The analysis is performed by comparing the voltage gain of buffers implemented with GC and standard SOI nMOS transistors considering devices with the same mask channel length and same effective channel length. It is shown that the use of GC devices allows for achieving improved gain in all inversion levels in a wide range of temperatures. In addition, this improvement increases as temperature is reduced. It is shown that GC transistors can provide virtually constant gain, while for standard devices, the gain departs from the maximum value depending on the temperature and inversion level imposed by the bias current and input voltage. Two-dimensional numerical simulations were performed in order to study the reasons for the enhanced gain of GC MOSFETs at low temperatures. (C) 2009 Elsevier Ltd. All rights reserved.