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Technological Parameters Scaling Influence on the Analog Performance of Graded-Channel SOI nMOSFET Transistors

Authors :
UCL - SST/ICTM/ELEN - Pôle en ingénierie électrique
Assalti, R.
Pavanello, Marcelo Antonio
de Souza, Michelly
Flandre, Denis
International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)
UCL - SST/ICTM/ELEN - Pôle en ingénierie électrique
Assalti, R.
Pavanello, Marcelo Antonio
de Souza, Michelly
Flandre, Denis
International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)
Publication Year :
2014

Abstract

This paper aims at analyzing, through two-dimensional numerical simulations and experimental results, the influence of technological parameters downscaling on the analog performance of Graded-Channel FD SOI nMOSFET transistors. Front gate oxide and silicon film thicknesses, channel doping concentration, total channel and lightly doped region lengths have been varied to target the highest intrinsic voltage gain.

Details

Database :
OAIster
Notes :
English
Publication Type :
Electronic Resource
Accession number :
edsoai.on1130482089
Document Type :
Electronic Resource