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Charge transport mechanisms of forward and reverse leakage currents in vertical GaN Schottky barrier diodes are investigated by measuring the temperature-dependent current–voltage characteristics. The results show that the leakage current is primarily governed by dislocation-associated thermionic field emission (TFE). The primary transport path is the reduced, localized conduction band around the dislocation core rather than the continuum defect states. A refined phenomenological physical model is developed for conductive dislocations in GaN, emphasizing that: 1) surface donors, surrounding the core of dislocations, can significantly shrink the barrier region after ionization, causing severe TFE leakage; 2) the ON donors likely to be responsible for TFE have a typical density of ~ 1 × 1018 cm−3 at 300 K and activation energy of 78 meV; and 3) the barrier height at donor sites is ~0.65 eV at 300 K, which is reduced by ~0.4 eV with respect to the dislocation-free region. [ABSTRACT FROM AUTHOR]

Structures integrated onto a BiCMOS test chip are specially designed to characterize the complex mechanisms related to proton radiation response in bipolar technologies. Bipolar devices from a commercial process are modified to include independent gate terminals. Through the use of gate control, the effects of proton-induced defects on discrete bipolar devices and analog bipolar circuits can be analyzed independently, thereby facilitating a quantitative description of the nonlinear relationship between the radiation defects and electrical response at both the device and circuit level. [ABSTRACT FROM AUTHOR]

This paper models the indeterminacy that occurs during the formation of breakdown current channels in a bipolar structure, when subjected to an ultrafast high voltage pulse. The experimental results, pertaining to different regimes of the voltage ramp speed, applied across the bipolar structure are modeled. The avalanche injection mechanisms under variable high speed ramps are studied through the formation and propagation of ionizing waves, which lead to either weak or strong injection of mobile carriers, as the high current injection paths get coupled. Furthermore, the role of emitter injection is related to the indeterminacy associated with the snapback phenomenon and systematically related to the experimental observations. [ABSTRACT FROM PUBLISHER]

InAs–AlSb high-electron mobility transistors stressed with hot carriers may exhibit shifts in the peak transconductance toward more negative gate-voltages. The devices are most degradation prone in operating conditions with high longitudinal (in the direction of IDS) electric fields in the channel. Room-temperature annealing, gate current, and channel-mobility measurements suggest the presence of a metastable defect in the top AlSb layer. Device simulations and first-principles quantum–mechanical calculations are used to investigate the physical nature of the defects responsible for degradation. Metastable configurations of substitutional and interstitial oxygen have charge states and transition energies consistent with the degradation trends. [ABSTRACT FROM PUBLISHER]

The energy distributions of electrons in gate-all-around (GAA) Si MOSFETs are analyzed using full-band 3-D Monte Carlo (MC) simulations. Excellent agreement is obtained with experimental current–voltage characteristics. For these 24-nm gate length devices, the electron distribution features a smeared energy peak with an extended tail. This extension of the tail results primarily from the Coulomb scattering within the channel. A fraction of electrons that enter the drain retains their energy, resulting in an out-of-equilibrium distribution in the drain region. The simulated density and average energy of the hot electrons correlate well with experimentally observed device degradation. We propose that the interaction of high-energy electrons with hydrogen-passivated phosphorus dopant complexes within the drain may provide an additional pathway for interface-trap formation in these devices. [ABSTRACT FROM AUTHOR]

The operation of transistorized Marx-bank circuits (MBCs) is analyzed, and physics-based modeling is used to understand the anomalous switching behavior of the first stage single trigger avalanche transistors of MBCs at high-current-injection conditions. The role of a voltage trigger pulse having variable rise time when applied to the base terminal is investigated to model the underlying physics of the anomalous switching behavior. Experimental observations related to ultrafast anomalous switching mechanisms of trigger transistor, i.e., either primary breakdown or current mode secondary breakdown, for faster and slower base drives are presented. This demonstrates the importance of the dynamic avalanche process and reverse saturation current on the switching mechanism under high-speed base-trigger ramps for different avalanche BJTs from various manufacturers and different lots. The agreement between 2-D TCAD device simulation results and the experimental observations shows the validity of the proposed theory when the base width and mobile carrier recombination rate are used as parameters in the device simulation setup. [ABSTRACT FROM AUTHOR]

The electrostatic and leakage effects of extended defects on Si and Ge MOSFETs are investigated. A technology computer-aided design model of extended defects is developed based upon measured device electrical properties. A single extended defect is introduced into simulated 2-D planar and 3-D FinFET structures. It is found that a 2-D extended defect is a source of variability in planar transistors, with the electrical effects depending on its position along the channel. A 2-D extended defect increases the threshold voltage and subthreshold swing when it is in the channel and increases the leakage current when it is in the drain. The dislocation effect on transistor characteristics increases with decreasing transistor width. The effect is less pronounced in FinFETs due to the well-controlled electrostatics and the small dislocation volume. [ABSTRACT FROM PUBLISHER]

We report the experimental data, quantum-mechanical calculations, and engineering-level modeling that provide insight into the atomic-scale processes that underlie the hot-electron degradation of AlGaN/GaN high-electron-mobility transistors during electrical stress at moderate drain bias. There is relatively large degradation (up to 20%) of the peak transconductance ( gm ) in the semi-ON state, along with a small shift of the threshold voltage ( VT ). The VT shift and gm degradation increase with temperature. A model of the degradation is presented, based on the hot-carrier-induced defect generation. The model considers carrier energy distributions for different temperatures obtained using an ensemble Monte Carlo (EMC) approach. The Ensemble Monte-Carlo results show that the concentration of energetic carriers is maximum at the end of the gate on the gate–drain access side in the semi-ON state of operation. The degradation is directly related to the number of carriers with sufficient energy to generate defects, and the carrier energy distribution depends strongly on the device temperature. The first-principles density functional theory calculations and the analysis suggest that the dehydrogenation of substitutional iron and its complexes is the dominant cause of the observed degradation in these devices. [ABSTRACT FROM AUTHOR]

Monte Carlo analysis of hot-electron degradation in AlGaN/GaN high-electron mobility transistors shows that, for gate voltages corresponding to semi-ON bias conditions, the average electron energy has a spatial peak with \langleEAVE\rangle\sim1.5~\rm eV . The peak is located at the edge of the gate. At this location, the carrier versus energy distribution has a large tail extending over 3 eV. When transferred to the lattice, this energy can cause defect dehydrogenation and device degradation. These results are consistent with the experimental data indicating maximum degradation in the semi-ON bias condition. [ABSTRACT FROM AUTHOR]

The temperature dependence of the low-frequency noise of 4H-silicon carbide (SiC) MOSFETs with nitrided oxides is reported over the temperature range 85–510 K. The 1/f noise decreases significantly with increasing measurement temperature. This decrease in noise results primarily from a decrease in the density of interface traps at increasing temperatures. The 1/f noise is also characterized after total ionizing dose irradiation and postirradiation annealing. No significant change in the 1/f noise is observed after the devices are irradiated to 1 Mrad (SiO2) and then annealed under bias at elevated temperature. These results show that the 1/f noise in 4H-SiC MOSFETs is dominated by the interaction of channel carriers with slow interface traps at temperatures <360~K and with border traps >\rm\!360~K. This result contrasts with most experience with Si/SiO2-based MOSFETs, and results from the wider bandgap and greater density of slow interface traps in SiC/SiO2-based MOSFETs than in Si/SiO2-based MOSFETs. [ABSTRACT FROM AUTHOR]

A novel on-chip test circuit to measure single-event transient (SET) pulse widths has been developed and implemented in IBM 130-nm and 90-nm processes for characterizing logic soft errors. Test measurements with heavy ions and alpha particles show transient widths ranging from 100 ps to over 1 ns, comparable to legitimate logic signals in such technologies. Design options to limit the SET pulse width and hence to mitigate soft errors are evaluated with the test circuit to demonstrate the effectiveness of such design techniques. [ABSTRACT FROM AUTHOR]

We report experimental results from noninvasive second harmonic generation (SHG) measurements applied to characterize separation by implantation of oxygen (SIMOX) and bonded thin film silicon-on-insulator (SOI) wafers. Results demonstrate that the SHG response of the SOI structure can provide an indication of the quality of the buried oxide interfaces, including roughness, charge states, and detection of the presence of metallic contamination. The potential application of SHG as a noncontact metrology tool for process control is described. [ABSTRACT FROM AUTHOR]

In the silicon-on-insulator four-gate transistors (G4-FETs), the conducting channel can be surrounded by depletion regions induced by independent vertical metal-oxide-semiconductor gates and lateral JFET gates. This unique conduction mechanism named depletion-all-around (DAA) enables majority carriers to flow in the volume of the silicon film far from the silicon/oxide interfaces. Especially when the interfaces are driven to inversion, the control of the lateral JFET gates on the conduction is maximized, while the sensitivity of the volume channel to the oxide and interface defects is minimized. This leads to excellent analog performance, low noise, and reduced sensitivity to ionizing radiation. The G4-FET properties in DAA mode are presented from multiple perspectives: experimental results, 3-D device simulations, and analytical modeling. [ABSTRACT FROM AUTHOR]