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10 results on '"Pelloie, Jean-Luc"'

1. Hot-carrier effects and reliable lifetime prediction in deep submicron N-and P-channel SOI MOSFET's

Author

Renn, Shing-Hwa, Pelloie, Jean-Luc, and Balestra, Francis

Subjects
Metal oxide semiconductor field effect transistors -- Research, Business, Electronics, Electronics and electrical industries
Abstract

A detailed analysis of hot-carrier effects in deep submicron N and P channel SOI MOSFETs is presented, for gate lengths down to 0.1 mum. The two-stage time dependence of degradation is also investigated to provide reliable lifetime prediction methods that can be used under various hot-carrier stress conditions. Saturation levels are reliant on gate length, thus degradation time dependence needs to be carefully determined.

Published
1998

2. A thorough investigation of the degradation induced by hot-carrier injection in deep submicron N- and P-channel partially and fully depleted unibond and SIMOX MOSFET's

Author

Renn, Shing-Hwa, Raynaud, Christine, Pelloie, Jean-Luc, and Balestra, Francis

Subjects
Silicon-on-isolator -- Research, Metal oxide semiconductor field effect transistors -- Observations, Business, Electronics, Electronics and electrical industries
Abstract

Hot carrier induced degradation is more complex in SOI devices than in bulk devices due to the thin Si-film effects. The reliability of SOI technologies are assessed, focusing on the hot-carrier effects (HCE) in deep submicron SIMOX and Unibond MOSFETs, hot carrier immunity of PD devices and analysis of the degradation N and P channel transistors. An investigation of the aging/recovery mechanisms for P-channel MOSFETs is also made.

Published
1998

3. Generation-recombination transient effects in partially depleted SOI transistors: systematic experiments and simulations

Author

Munteanu, Daniela, Weiser, Douglas A., Cristoloveanu, Sorin, Faynot, Olivier, Pelloie, Jean-Luc, and Fossum, Jerry G.

Subjects
Metal oxide semiconductor field effect transistors -- Models, Transients (Electricity) -- Models, Business, Electronics, Electronics and electrical industries
Abstract

Gate-induced transient effects in floating-body and nonideally body-tied partially-depleted MOSFETs have been studied. These phenomena are caused by time-dependence threshold voltage resulting from changes in body potential due to capacitive coupling to the gates. A physical compact model of the carrier generation and recombination has been formulated to simulate the behavior of the MOSFETs to front and back gate pulses.

Published
1998

4. Hot-carrier effects and lifetime prediction in off-state operation of deep submicron SOI N-MOSFETs

Author

Renn, Shing-Hwa, Rauly, Emmanuel, Pelloie, Jean-Luc, and Balestra, Francis

Subjects
Silicon-on-isolator -- Analysis, Metal oxide semiconductor field effect transistors -- Analysis, Bipolar transistors -- Analysis, Business, Electronics, Electronics and electrical industries
Abstract

Research was conducted to examine hot-carrier effects resulting from parasitic bipolar transistor action in deep submicron N-channel silicon-on-insulator metal oxide semiconductor field effect transistors for a range of temperature and gate length. Device aging was heavily influenced by variations in the leakage currents. Moreover, variations of threshold voltage shifts for a stress in off-state showed unusual behaviors.

Published
1998

5. Total dose effects of a fully-depleted SOI NMOSFET and its lateral parasitic transistor

Author

Ferlet-Cavrois, Veronique, Musseau, Olivier, Leray, Jean-Luc, Pelloie, Jean-Luc, and Raynaud, Christine

Subjects
Transistors -- Research, Charge transfer -- Research, Metal oxide semiconductor field effect transistors -- Research, Business, Electronics, Electronics and electrical industries
Abstract

There are close connections between the dose-induced threshold voltage shift of fully-depleted NMOS transistors and charge trapping in the buried oxide. Coupling between the front and back gate transistors is responsible for the significant shift in the fully-depleted SOI/NMOSFET which results from radiation-induced charge trapping in the buried oxide. Research indicates that the lateral parasitic transistor is more affected than the main active transistor by the buried oxide trapping.

Published
1997

6. A new generation of IC processing: Low-power, high-performance SOI CMOS. (Materials (SOI))

Author

Pelloie, Jean-Luc and Auberton-Herve, Andre

Subjects
Semiconductor industry, Integrated circuit design, Circuit designer, Transistors -- Research, Circuit design -- Research, Metal oxide semiconductor field effect transistors -- Research, Semiconductor industry -- Research, Transistor circuits -- Research
Abstract

OVERVIEW To take full advantage of the SOI structure, device architecture and design issues must be addressed. While circuit design is achieved with standard CAD tools, specific modeling is required […]

Published
2001

7. A physically based relation between extracted threshold voltage and surface potential flat-band voltage for MOSFET compact modeling

Author

Benson, James, D'Halleweyn, Nele V., Redman-White, William, Easson, Criag A., Uren, Michael J., Faynot, Olivier, and Pelloie, Jean-Luc

Subjects
Metal oxide semiconductor field effect transistors -- Models, Business, Electronics, Electronics and electrical industries
Abstract

A link between extracted threshold voltage and surface potential flat-band voltage in MOSFET compact modeling is described.

Published
2001

8. Design myths surround strained SOI

Author

Pelloie, Jean-Luc

Subjects
Market trend/market analysis, Integrated circuit design, Circuit designer, Circuit design -- Forecasts and trends, Silicon-on-isolator -- Design and construction
Published
2004

9. SOI CMOS requires complex modeling

Author

Pelloie, Jean-Luc

Subjects
Technology application, Microprocessor, Research and development, Semiconductor industry -- Research, Microprocessors -- Research, High technology industry -- Research
Published
2002

10. Silicon-On-Insulator Technology Bumps Up SoC Performance.

Author

Pelloie, Jean-Luc and Auberton-Herve, Andre

Subjects
*INTEGRATED circuits, *SILICON-on-insulator technology, *SYSTEMS on a chip, *ELECTRONICS
Abstract

Features the innovative enhancements supportingsilicon-on-insulator (SOI) for systems-on-a-chip. Optimization ofSOI design processes and methodologies; Advantage in using SOI;Various features and characteristics of SOI. INSET: HIGHLIGHTS:.

Published
2003

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