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The electrocardiogram (ECG) is one of the most extensively employed signals used to diagnose and predict cardiovascular diseases (CVDs). In recent years, several deep learning (DL) models have been proposed to improve detection accuracy. Among these, deep neural networks (DNNs) are the most popular, wherein the features are extracted automatically. Despite the increment in classification accuracy, DL models require exorbitant computational resources and power. This causes the mapping of DNNs to be slow; in addition, the mapping is challenging for a wearable device. Embedded systems have constrained power and memory resources. Therefore full-precision DNNs are not easily deployable on devices. To make the neural network faster and more power-efficient, spiking neural networks (SNNs) have been introduced for fewer operations and less complex hardware resources. However, the conventional SNN has low accuracy and high computational cost. Therefore, this paper proposes a new binarized SNN which modifies the synaptic weights of SNN constraining it to be binary (+1 and -1). In the simulation results, this paper compares the DL models and SNNs and evaluates which model is optimal for ECG classification. Although there is a slight compromise in accuracy, the latter proves to be energy-efficient.

Image processing is one of the major techniques that are used for computer vision. Nowadays, researchers are using machine learning and deep learning for the aforementioned task. In recent years, digit recognition tasks, i.e., automatic meter recognition approach using electric or water meters, have been studied several times. However, two major issues arise when we talk about previous studies: first, the use of the deep learning technique, which includes a large number of parameters that increase the computational cost and consume more power; and second, recent studies are limited to the detection of digits and not storing or providing detected digits to a database or mobile applications. This paper proposes a system that can detect the digital number of meter readings using a lightweight deep neural network (DNN) for low power consumption and send those digits to an Android mobile application in real-time to store them and make life easy. The proposed lightweight DNN is computationally inexpensive and exhibits accuracy similar to those of conventional DNNs.

In this paper, a negative high voltage DC-DC converter using a new cross-coupled charge pump structure has been proposed, which can solve the shoot-through current problem of the conventional charge pump by using a four clock phase scheme. Also, by switching the power supply to each stage based on the supply voltage, a variable voltage gain can be obtained. A complete analysis of the interaction between the power efficiency, area, and frequency have been presented. The proposed negative charge pump is designed to deliver 40μA with a widesupply range from 2.5V to 5.5V using 0.18μm high voltage LDMOS technology.

This paper proposes a novel Built-in Self Calibration (BISC) technique for a 12-bit 32MS/s successive approximation register (SAR) analog-to-digital converter (ADC) using a single input to reduce the capacitor mismatch of the digital-to-analog converter (DAC) and to compensate the comparator input offset voltage. The proposed self-calibration scheme optimize the mismatch of the DAC by changing additional auxiliary capacitor array during calibration mode. In addition, in order to minimize the offset voltage of the comparator in the SAR ADC, a simplified voltage amplifier is proposed. The controller for the proposed algorithm operates as foreground operation to achieve low power consumption during operation. Compared to the converters that use the conventional procedure, INL and DNL are reduced by about 47% and 52%, respectively. The prototype was designed using 130nm single poly 6 metal standard CMOS technology. The ADC achieves a SNDR of 65.6 dB and consumes 4.62 mW. The ADC core occupies an active area of only 240μmÍ 298 μm using 1.2V supply and the sampling rate of 50 MS/s.

Electrocardiogram (ECG) classification has become an essential task of modern day wearable devices, and can be used to detect cardiovascular diseases. State-of-the-art Artificial Intelligence (AI)-based ECG classifiers have been designed using various artificial neural networks (ANNs). Despite their high accuracy, ANNs require significant computational resources and power. Herein, three different ANNs have been compared: multilayer perceptron (MLP), convolutional neural network (CNN), and spiking neural network (SNN) only for the ECG classification. The ANN model has been developed in Python and Theano, trained on a central processing unit (CPU) platform, and deployed on a PYNQ-Z2 FPGA board to validate the model using a Jupyter notebook. Meanwhile, the hardware accelerator is designed with Overlay, which is a hardware library on PYNQ. For classification, the MIT-BIH dataset obtained from the Physionet library is used. The resulting ANN system can accurately classify four ECG types: normal, atrial premature contraction, left bundle branch block, and premature ventricular contraction. The performance of the ECG classifier models is evaluated based on accuracy and power. Among the three AI algorithms, the SNN requires the lowest power consumption of 0.226 W on-chip, followed by MLP (1.677 W), and CNN (2.266 W). However, the highest accuracy is achieved by the CNN (95%), followed by MLP (76%) and SNN (90%).

Most of the existing hand detection methods rely on the contour shape of hand after skin color segmentation. Such contour shape based computations, however, are not only susceptible to noise and other skin color segments but also inherently sequential and difficult to efficiently parallelize. In this paper, we implement and accelerate our in-house distance image based approach using CPU-GPU heterogeneous computing. Using emerging CPU-GPU heterogeneous computing technology, we achieved 5.0 times speed-up for 320x240 images, and 17.5 times for 640x480 images and our experiment demonstrates that our proposed distance image based hand detection is robust and fast, reaching up to 97.32% palm detection rate, 80.4% of which have more than 3 fingers detected on commodity processors.

In this paper, a 12-bit high resolution, power and area efficiency hybrid digital pulse width modulator (DPWM) with process and temperature (PT) calibration has been proposed for digital controlled DC-DC converters. The hybrid structure of DPWM combines a 6-bit differential tapped delay line ring-mux digital-to-time converter (DTC) schema and a 6-bit counter-comparator DTC schema, resulting in a power and area saving solution. Furthermore, since the 6-bit differential delay line ring oscillator serves as the clock to the high 6-bit counter-comparator DTC, a high frequency clock is eliminated, and the power is significantly saved. In order to have a simple delay cell and flexible delay time controllability, a voltage controlled inverter is adopted to build the deferential delay cell, which allows fine-tuning of the delay time. The PT calibration circuit is composed of process and temperature monitors, two 2-bit flash ADCs and a lookup table. The monitor circuits sense the PT (Process and Temperature) variations, and the flash ADC converts the data into a digital code. The complete circuits design has been verified under different corners of CMOS 0.18um process technology node.

Conventional synchronous design circuits cannot only satisfy the timing requirement of the low voltage digital systems, but also they may generate wrong outputs under the influence of PVT variations and aging effects. Therefore, in this paper, a NCL (Null Convention Logic) design as an asynchronous design method has been proposed, where the NCL method doesn`t require any timing analysis, and it has a very simple design methodology. Base on the NCL method, a new low power reliable ALU has been designed and implemented using MagnaChip-SKhynix 0.18um CMOS technology. The experimental results of the proposed NCL ALU have been compared to those of a conventional pipelined ALU in terms of power consumption and speed.

As CMOS technology is scaled down more aggressively, the reliability mechanism (or aging effect) caused by the diffusion of metal atoms along the conductor in the direction of the electron flow, also called electromigration (EM), has become a major reliability concern. With the present of EM, it is difficult to control the current flows of the MOSFET device and interconnect. In addition, nanoscale CMOS circuits suffer from increased gate leakage current and power consumption. In this paper, the EM effects on current of the nanoscale CMOS circuits are analyzed. Finally, this paper introduces an on-chip current measurement method providing lifetime electromigration management which are designed using 45-nm CMOS predictive technology model.

This paper presents a UHF RFID Reader designed for recognition and tracking in IoT domain. It is built by NI USRP software radio platform and NI LabVIEW with flexible physical/MAC layer parameters, which can be modified easily and monitored clearly from front panel of this Reader compared to commercial RFID Reader. Queried random number sequence from a commercial Tag can be detected within half meter using this UHF Reader. All designs of this Reader are based on EPC Gen-2 RFID protocol, any further research based on this Reader can be easily connected and tested with commercial Tags.

Any real architecture designed only in the CNFET technology as a hopeful substitution of the silicon CMOSFET has not been developed because of shortage of self-assembly CNFET technology for designing complex CNFET structures. Therefore, for designing the real architecture in the current self-assembly CNFET technology, the development of a simple CNFET circuit structure forming all the digital function is required. This paper proposes a simple CNFET circuit structure using back-gate voltages to design the real digital architecture and to overcome the high fabrication cost of CNFETs and manufacturing variability and imperfection of CNFET technology. The function of the proposed CNFET cell is determined by the back-gate voltages, and the determined function is the same as NAND or NOR gate function. The simulation results present that the propagation delay time of the ISCAS85 circuits in a 32nm Stanford CNFET technology deploying the proposed CNFET cells is reduced by over 42% compared to the conventional CNFET cell in ultra-low voltage (0.4V).

Ultra low-power design and energy harvesting applications require digital systems to operate under extremely low voltages approaching the point of balance between dynamic and static power consumption which is attained in the sub-threshold operation mode. Delay variations are extremely large in this mode. Therefore, in this paper, a new low-power logic design methodology using asynchronous NCL circuits is proposed to reduce power consumption and not to be affected by various technology variations in nanoscale MOSFET technology. The proposed NCL is evaluated using various benchmark circuits at 0.4V supply voltage, which are designed using 45nm MOSFET predictive technology model. The simulation results are compared to those of conventional synchrouns logic circuits in terms of power consumption and speed.

This paper presents the impact of time dependent dielectric breakdown (TDDB, also called as gate oxide breakdown) failure on nanoscale digital CMOS Circuits. Recently, TDDB for ultra-thin gate oxides has been considered as one of the critical reliability issues which can lead to performance degradation or logic failures in nanoscale CMOS devices. Also, leakage power in the standby mode can be increased significantly. In this paper, TDDB aging effects on large CMOS digital circuits in the 45nm technology are analyzed. Simulation results show that TDDB effect on MOSFET circuits can result in more significant increase of power consumption compared to delay increase.

This paper proposes a new input pattern generator for minimal leakage power in the nanometer CMOS technology considering all the leakage current components (sub-threshold leakage, gate tunneling leakage, band-to-band tunneling leakage). Using the accurate macro-model, a heuristic algorithm is developed to generate a input pattern for the minimum leakage. The algorithm applies to ISCAS85 benchmark circuits, and the results are compared with the results of Hspice. The simulation result shows that our method"s accuracy is within a 5% difference of the Hspice simulation results. In addition, the simulation time of our method is far faster than that of the Hspice simulation.

—In deeply scaled CMOS technologies, two major non-ideal factors are threatening the survival of the CMOS; i) PVT (process, voltage, and temperature) variations and ii) leakage power consumption. In this paper, we propose a novel post-silicon tuning methodology to scale optimum voltage and frequency “dynamically”. The proposed design technique will use our PVT sensor circuits to monitor the variations and based on the monitored variation data, voltage and frequency will be compensated “automatically”. During the compensation process, supply voltage is dynamically adjusted to guarantee the minimum total power consumption without violating the frequency requirement. The simulation results show that the proposed technique can reduce the total power by 85% and the static power by 53% on average for the selected ISCAS’85 benchmark circuits with 45 nm CMOS technology compared to the results of the traditional PVT compensation method. Keywords —PVT Variation sensors, Yield, Voltage Scaling, Frequency Scaling

Ubiquitous network and wireless sensor networks is being applied in various fields. Located at target areas, node of wireless sensor network uses batteries as a power source. Batteries have a limited energy in sensor network applications. Also, before use, the battery must be charged and It is difficult to replace the battery. Therefore, energy harvesting technology is being researched and being developed for long life of sensor node. Especially, sola energy is being extensively researched. because that can have great amounts of energy than other environmental energy in a short time. In this study, we tested battery charging and recharging, operation of sensor node using Solar Cell. Also, monitoring data gathering and voltage Analysis showed energy harvesting time of Sola Cell battery for sensor node and operation of sensor node.

nanowires were synthesized by a hydrothermal reaction of metallic Y with aqueous solution of LiOH. The morphology and the size of the nanowires changed with varying the volume of the LiOH solution inside the autoclave. nanowires transformed to by a subsequent heat-treatment without morphological change. By a proper control of hydrothermal reaction parameter and heat-treatment, the yield of pure nanowires up to 97% was attained.

Accurate performance-degradation monitoring of nanometer MOSFET digital circuits is one of the most critical issues in adaptive design techniques for overcoming the performance degradation due to aging phenomena such as negative bias temperature instability (NBTI) and hot carrier injection (HCI). Therefore, this paper proposes new on-chip aging sensor circuits which deploy a threshold voltage detector for monitoring the performance degradation of an aged MOSFET. The new aging sensor circuits measure the threshold voltage difference between a NBTI/HCI stressed MOSFET device and a NBTI/HCI unstressed MOSFET device using an inverter chain and a phase comparator and digitalize the phase difference induced by the threshold voltage difference. The proposed sensor circuits achieve a direct correlation between the threshold voltage degradation and the phase difference (a phase difference resolution of 1 ns per 0.01 V threshold voltage shift). Also, the circuits are almost independent of temperature variation due to symmetrical circuit structures. A 45 nm CMOS technology and predictive NBTI/HCI models have been used to implement and evaluate the proposed circuits. The implemented layout size is 18.58 x 7.97 μm2; the post-layout power consumption is 18.57 μW during NBTI/HCI stress mode and 30.86 μW during NBTI/HCI measurement mode on average.

A novel power gating (PG) structure using only low-threshold-voltage metal-oxide-semiconductor field-effect transistors (MOSFETs) is proposed to extend the PG to an ultralow-voltage region ( ~ 0.3 V). The proposed structure deploys series-connected low-V th footers with two virtual ground ports and selectively chooses the logic cells for connecting them to each virtual ground port according to the delay criticality. Furthermore, additional circuitry is designed to reduce not only the subthreshold leakage current but also the gate-tunneling leakage and to reduce the wake-up time and rush current compared to the conventional PG. The total PG switch size of the proposed PG structure including the additional circuits is less than the conventional one. The simulation results are compared to those of other well-known circuit schemes and show that, in the ultralow-voltage region, the other high-V th-based PG schemes cannot be used due to the impractical delay increase and long wake-up time, whereas the proposed PG structure keeps the balance among the critical PG issues. The proposed PG is evaluated using inverter chains and ISCAS85 benchmark circuits at 0.6-V supply voltage, which are designed using 45-nm complementary metal-oxide-semiconductor predictive technology model.

This paper presents a novel statistical characterization for accurate timing and a new probabilistic-based analysis for estimating the leakage power in partially depleted silicon-on-insulator (PD-SOI) circuits in 100-nm BSIMSOI3.2 technology. This paper shows that the accuracy of modeling the leakage current in PD-SOI complementary metal-oxide-semiconductor (CMOS) circuits is improved by considering the interactions between the subthreshold leakage and the gate tunneling leakage, the stacking effect, the history effect, and the fan-out effect, along with a new input-independent method for estimating the leakage power based on a probabilistic approach. The proposed timing and leakage power estimate algorithms are implemented in MATLAB, HSPICE, and C. The proposed methodology is applied to ISCAS85 benchmarks, and the results show that the error is within 5%, compared with random simulation results.

This paper presents a fast statistical static timing and leakage power analysis in Partially-Depleted Silicon-On-Insulator (PD-SOI) CMOS circuits in BSIMSOI3.2 100 nm technology. The proposed timing analysis considers floating body effect on the propagation delay for more accurate timing analysis in PD-SOI CMOS circuits. The accuracy of modeling the leakage power in PD-SOI CMOS circuits is improved by considering the interactions between the subthreshold leakage and the gate tunneling leakage, the stacking effect, the history effect, and the fanout effect. The proposed timing and leakage power analysis algorithms are implemented in Matlab, Hspice, and C language. The proposed methodology is applied to ISCAS85 benchmarks, and the results show that the error is within 5% compared with random simulation results.

This paper proposes a novel design method to minimize the leakage power during standby mode using a novel optimal supply voltage and body-bias voltage generating technique for nanoscale VLSI systems. The minimum level of VDD is generated for different temperature and process conditions adaptively using a look-up-table method. The subthreshold current as well as gate-tunneling and band-to-band-tunneling currents are monitored and minimized adaptively by the optimally generated body-bias voltage. The proposed design method reduces the leakage power by 1000 times on average for ISCAS85 benchmark circuits designed using 32nm CMOS technology comparing to the case where the method is not applied.

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9 V power supply voltage. The simulation results show that the proposed PLL achieves 88% jitter reduction at 440 MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of 40 M~725 MHz with a multipli-cation range of 1-1023, and the RMS and peak-to-peak jitter are 5psec and 42.7 psec, respectively.

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit which becomes more serious problem due to the thin gate oxide and small threshold voltage in nanometer CMOS technology and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32㎚ predictive CMOS technology and uses a 0.9V power supply voltage. The simulation results show that the proposed PLL achieves a 88% jitter reduction at 440㎒ output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of 40M~725㎒ with a multiplication range of 1-1023, and the RMS and peak-to-peak jitter are 5ps and 42.7ps, respectively.

This paper proposes a novel ultra-low voltage and high speed Schmitt trigger circuit designed in silicon-on-insulator (SOI) technology. The proposed circuit is designed using dynamic threshold MOS (DTMOS) technique and multi-threshold voltage CMOS (MT-CMOS) technique to reduce power consumption and accomplish high speed operation. The experiment shows the proposed Schmitt trigger circuit consumes 4.68µW at 0.7V power supply voltage and the circuit demonstrates the maximum switching speed of 170psec.

This paper presents a novel modeling and analysis of inter-symbol interference (ISI)jitter in serial data channels either between chips or on chip. The simulation results show that ISI jitter is dependent on pole location, settling time, and damping ratio of the data serial channel. Based on the proposed ISI jitter model, the effect of the ISI jitter on other jitter components is illustrated along with realistic simulation results.

The performance of General-Purpose computation on Graphics Processing Units (GPGPU) is heavily dependent on the memory access behavior. In this paper, we present an algorithmic methodology to semi-automatically find the best mapping of memory accesses present in serial loop nest to underlying data-parallel architectures based on a comprehensive static memory access pattern analysis. To that end we present a simple, yet powerful, mathematical model that captures all memory access pattern information present in serial data-parallel loop nests. We then show how this model is used in practice to select the most appropriate memory space for data and to search for an appropriate thread mapping and work group size from a large design space. Our experimental results are reported using the industry standard heterogeneous programming language, OpenCL, targeting the NVIDIA GT200 architecture. The full version of the paper can be found at [1].

This paper presents a fully integrated on-chip switched-capacitor (SC) DC–DC converter that supports a programmable regulated power supply ranging from 2.6 to 3.2 V out of a 5 V input supply. The proposed 4-to-3 step-down topology utilizes two conventional 2-to-1 step-down topologies; each of them (2-to-1_up and 2-to-1_dw) has a different flying capacitance to maximize the load current driving capability while minimizing the bottom-plate capacitance loss. The control circuits use a low power supply provided by a small internal low-drop output (LDO) connected to the internal load voltage (VL_dw) from the 2-to-1_dw, and low swing level-shifted gate-driving signals are generated using the internal load voltage (VL_dw). Therefore, the proposed implementation reduces control circuit and switching power consumptions. The programmable power supply voltage is regulated by means of a pulse frequency modulation (PFM) technique with the compensated two-stage operational transconductance amplifier (OTA) and the current-starved voltage controlled oscillator (VCO) to maintain high efficiency over a wide range of load currents. The proposed on-chip SC DC–DC converter is designed and simulated using high-voltage 0.35 μm bipolar, complementary metal-oxide-semiconductor (CMOS) and DMOS (BCDMOS) technology. It achieves a peak efficiency of 74% when delivering an 8 mA load current at a 3.2 V supply voltage level, and it provides a maximum output power of 48 mW (IL = 15 mA at VL_up = 3.2 V) at 70.5% efficiency. The proposed on-chip SC voltage regulator shows better efficiency than the ideal linear regulator over a wide range of output power, from 2.6 mW to 48 mW. The 18-phase interleaving technique enables the worst-case output voltage ripple to be less than 5.77% of the load voltage.

As technology scales down, it has become one of the most critical issues in aging-tolerant nanoscale MOSFET circuit design to monitor the performance degradation of the circuits under aging stress conditions such as Negative-Bias-Temperature Instability (NBTI) and Hot-Carrier-Injection (HCI). Hence, this paper proposes a novel on-chip circuit to measure the delay degradation of stressed MOSFET digital circuits and digitalize the degradation for aging compensation. A 0.11μm CMOS technology has been used to implement and evaluate the proposed circuits.