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This paper reports a MEMS disk resonator gyroscope (DRG) with superior overall performance in terms of bias instability, measurement range, and size. Specifically, a fully filled electrodes MEMS DRG is proposed to improve sensing capacitance to 23.66 pF and drive capacitance to 6.14 pF. The DRG is fabricated using a wafer-level vacuum-package process and is controlled and sensed by a configurable ASIC, enabling a small footprint. The DRG achieves an angle random walk (ARW) of 0.05/h and bias instability of 0.42/h within a full scale of 300/s, making it a very promising solution for angular measurement in high-end industrial applications.

Severe process variations in advanced technology require more devices under test (DUTs) to be characterized in the wafer acceptance test (WAT) to more reliably qualify the fabricated wafers. However, conventional WAT takes a long test time to acquire sufficient characterization data. This article proposes an on-wafer test circuity to fast and accurately characterize DUT arrays during a single probing. It integrates the proposed compact DUT cells, an IR drop compensator, and a wide-input-range (WIR) current digitizer. The proposed IR drop compensator collaborates with the DUT cells to address the IR drop issue and thus improve the test accuracy of the parameter tests. The proposed multi-mode 12-bit WIR current digitizer achieves a 140-dB input range for digitizing the DUTs' output currents in various WAT test items. It eliminates the need of high-end ATE and saves the test cost. A prototype IC including 2048 DUTs has been designed and fabricated in 90-nm CMOS. Its active area is only 60 μm by 1900 μm which can be placed in a scribe line as conventional WAT structure is. Experimental results demonstrate the proposed test circuitry can render spatial variation results and other device parameters of the DUT arrays in addition to typical WAT items.

In this paper, an evaluation of machine learning classifiers to be applied in wafer defect detection is described. The objective is to establish the best machine learning classifier for Wafer Defect Detection application. k-Nearest Neighbours (k-NN), Logistic Regression, Stochastic Gradient Descent, and Support Vector Machine were evaluated with 3 defects categories and one non-defect category. The key metrics for the evaluation are classification accuracy, classification precision and classification recall. 855 images were used to train, test and validate the classifier. Each image went through the embedding process by InceptionV3 algorithms before the evaluated classifier classifies the images.

The semiconductor, β-Ga2O3 is attractive for applications in high power electronic devices with low conduction loss due to its ultra-wide bandgap (∼4.9 eV) and large Baliga's figure of merit. However, the thermal conductivity of β-Ga2O3 is much lower than that of other wide/ultra-wide bandgap semiconductors, such as SiC and GaN, which results in the deterioration of β-Ga2O3-based device performance and reliability due to self-heating. To overcome this problem, a scalable thermal management strategy was proposed by heterogeneously integrating wafer-scale single-crystalline β-Ga2O3 thin films on a highly thermally conductive SiC substrate. Characterization of the transferred β-Ga2O3 thin film indicated a uniform thickness to within ±2.01%, a smooth surface with a roughness of 0.2 nm, and good crystalline quality with an X-ray rocking curves (XRC) full width at half maximum of 80 arcsec. Transient thermoreflectance measurements were employed to investigate the thermal properties. The thermal performance of the fabricated β-Ga2O3/SiC heterostructure was effectively improved in comparison with that of the β-Ga2O3 bulk wafer, and the effective thermal boundary resistance could be further reduced to 7.5 m2K/GW by a post-annealing process. Schottky barrier diodes (SBDs) were fabricated on both a β-Ga2O3/SiC heterostructured material and a β-Ga2O3 bulk wafer. Infrared thermal imaging revealed the temperature increase of the SBDs on β-Ga2O3/SiC to be one quarter that on the β-Ga2O3 bulk wafer with the same applied power, which suggests that the combination of the β-Ga2O3 thin film and SiC substrate with high thermal conductivity promotes heat dissipation in β-Ga2O3-based devices.

Defect patterns on semiconductor wafer maps point to different manufacturing problems. Consequently, they have become key factors in identifying and resolving the root causes of yield improvement. Perhaps not surprisingly, the probability of having multiple defect patterns on a wafer map has increased in tandem with advances in manufacturing technology. Prior research on defect patterns has focused primarily on image classification methods which are neither good at mixed-type defect pattern classification nor able to provide locational information for further analysis. This study develops a framework that integrates a Mask R-CNN-based instance segmentation model with copy-paste and rotational data augmentation. The proposed method is able to precisely classify and locate defect patterns on a wafer map given limited training data, tasks which can help companies identify the manufacturing root causes of defects in a timely manner when ramping up their production for yield enhancement. Our experiments were performed using real-world WM-811K data. Using COCO pre-trained weights and only 1,056 items of original training data, the model reached an accuracy of 97.7% on single-type classification. Mixed-type classification hamming loss, exact match and accuracy were 0.155, 69% and 82%, respectively.

Transition metal dichalcogenides (TMDs) are materials that can exhibit intriguing optical properties like a change of the bandgap from indirect to direct when being thinned down to a monolayer. Well-resolved narrow excitonic resonances can be observed for such monolayers although only for materials of sufficient crystalline quality and so far mostly available in the form of micrometer-sized flakes. A further significant improvement of optical and electrical properties can be achieved by transferring the TMD on hexagonal boron nitride (hBN). To exploit the full potential of TMDs in future applications, epitaxial techniques have to be developed that not only allow the growth of large-scale, high-quality TMD monolayers but also allow the growth to be performed directly on large-scale epitaxial hBN. In this work, we address this problem and demonstrate that MoSe2 of high optical quality can be directly grown on epitaxial hBN on an entire 2 in. wafer. We developed a combined growth theme for which hBN is first synthesized at high temperature by metal organic vapor phase epitaxy (MOVPE) and as a second step MoSe2 is deposited on top by molecular beam epitaxy (MBE) at much lower temperatures. We show that this structure exhibits excellent optical properties, manifested by narrow excitonic lines in the photoluminescence spectra. Moreover, the material is homogeneous on the area of the whole 2 in. wafer with only ±0.14 meV deviation of excitonic energy. Our mixed growth technique may guide the way for future large-scale production of high quality TMD/hBN heterostructures.

This paper presents an all-SiC fiber-optic Fabry-Perot (FP) pressure sensor based on the hydrophilic direct bonding technology for the applications in the harsh environment. The operating principle, fabrication, interface characteristics, and pressure response test of the proposed all-SiC pressure sensor are discussed. The FP cavity is formed by hermetically direct bonding of two-layer SiC wafers, including a thinned SiC diaphragm and a SiC wafer with an etched cavity. White light interference is used for the detection and demodulation of the sensor pressure signals. Experimental results demonstrate the sensing capabilities for the pressure range up to 800 kPa. The all-SiC structure without any intermediate layer can avoid the sensor failure caused by the thermal expansion coefficient mismatch and therefore has a great potential for pressure measurement in high temperature environments.

Conductive atomic force microscopy (C-AFM) was employed to perform conductivity measurements on a facet-specific Cu2O cube, octahedron, and rhombic dodecahedron and intrinsic Si {100}, {111}, and {110} wafers. Similar I–V curves to those recorded previously using a nanomanipulator were obtained with the exception of high conductivity for the Si {110} wafer. Next, I–V curves of different Cu2O–Si heterostructures were evaluated. Among the nine possible arrangements, Cu2O octahedron/Si {100} wafer and Cu2O octahedron/Si {110} wafer combinations show good current rectification behaviors. Under white light illumination, Cu2O cube/Si {110} wafer and Cu2O rhombic dodecahedron/Si {111} wafer combinations exhibit the largest degrees of photocurrent, so such interfacial plane-controlled semiconductor heterojunctions with light sensitivity can be applied to make photodetectors. Adjusted band diagrams are presented highlighting different interfacial band bending situations to facilitate or inhibit current flow for different Cu2O–Si junctions. More importantly, the observation of clear current-rectifying effects produced at the semiconductor heterojunctions with properly selected contacting faces or planes implies that novel field-effect transistors (FETs) can be fabricated using this design strategy, which should integrate well with current chip manufacturing processes., The Cu2O octahedron/Si {100} wafer combination gives a large current-rectifying effect. The Cu2O rhombic dodecahedron/Si {111} wafer combination shows a notable photocurrent response.

Complementary metal-oxide-semiconductor (CMOS) image sensors have widely been used in internet of thinking (IoT) devices such as smartphones, smart watch and personal computer tablets [1] . The consumer market strongly requires higher sensitivity and higher speed image data processing to realize high functional CMOS image sensors such as three dimensionally stacked back-side-illuminated CMOS image sensors (3D-CIS) [2] . However, there are some serious technological issues in the fabrication of advanced CMOS image sensors as shown in Fig. 1 .

Rare earth (RE) doped oxides have demonstrated great potential for photonic applications and have also appeared as promising candidates for quantum memory devices and microwave to optical transducers. Here, we investigate the potential of Chemical Vapor Deposited (CVD) europium-doped Y2O3thin films on silicon as a new platform for integrated quantum devices. We aim at improving the optical properties of such thin films by carefully controlling the RE ion's environment. In particular, we study the effect of annealing post treatments and demonstrate that a significant source of broadening of the optical transition arises from interfacial reactions with the silicon substrate. We thus propose to encapsulate RE ions between undoped high-quality thick layers in order to limit the impact of interfacial reactions on their properties during thermal annealing. Using this approach, we succeeded in measuring a narrow inhomogeneous linewidth of 18 GHz and an ultra-narrow homogeneous linewidth of 5 MHz inferred from spectral hole width. These results are promising towards the use of these engineered RE doped thin films for the development of a scalable nanostructured spin-photon interface. In addition, our strategy could be applied to a large variety of oxide films for a broad range of applications. Paper published in Materials Advances.

We introduce a new innovative damage-free neutral beam etching (NBE) technique to transfer a honeycomb resist pattern to silicon (Si) wafer (thickness of 180 µm). Front-surface texturing of Si helps to reduce surface reflection and increase light absorption for solar cell applications. NBE was performed with Cl2 and Cl2/ SF6 gases chemistries, and the influence of the etching time on the etching profiles, surface reflection and potential short-circuit densities (p-JSC) was studied. The Si etching rate with pure Cl2 was ~ 5 nm/min and resulted in anisotropic etch profiles and a minimum surface reflection of 15% at 1000 nm, which is too high for practical use. With the introduction of 5% of SF6, the etching rate increased to 30 nm/min, the etching became isotropic (anisotropy of ~ 1), and sloped sidewalls appeared. NBE with Cl2 (95%)/SF6 (5%) produced a sample with an average surface reflection of 3.7% over the wavelength range 300–1000 nm without any antireflection coating. The minimum surface reflection in this case was ~ 1% at 1030 nm and p-JSC was 40.63 mA/cm2. This type of surface pattern is well suited for low-consumption-material (thin), high-efficiency Si solar cells.

In this article, we report a wafer-level packaged Pirani vacuum gauge using the proprietary InvenSense CMOS MEMS technology. The micro Pirani vacuum gauge features three serpentine-shaped molybdenum thermistors on the suspended silicon-on-insulator (SOI) bridges, while the wiring gap of each serpentine-shaped silicon microbridge is 1.6 ${ {\mu }}\text{m}$ . For the vacuum range of $5\times 10^{-{4}}$ –760 Torr, the CMOS MEMS Pirani gauge configured with a constant temperature interface circuit achieves a sensitivity of 0.414 V/Torr in a very fine vacuum regime, while its heating power is less than 21.3 mW. Moreover, the measured output of the micro Pirani gauge shows good agreement with a semi-empirical model, while the model predicts that the proposed Pirani gauge can measure a vacuum pressure as low as $2.6\times 10^{-{4}}$ Torr. The performance achieved by this Pirani vacuum gauge combined with its high level of integration makes it a promising Internet of Things (IoT) sensing node for vacuum monitoring in the industry.

GaAs on Si grown via metalorganic chemical vapor deposition is demonstrated using various Si substrate thicknesses and three types of dislocation filter layers (DFLs). The bowing was used to measure wafer‐scale characteristics. The surface morphology and electron channeling contrast imaging (ECCI) were used to analyze the material quality of GaAs films. Only 3‐μm bowing was observed using the 725‐μm‐thick Si substrate. The bowing shows similar levels among the samples with DFLs, indicating that the Si substrate thickness mostly determines the bowing. According to the surface morphology and ECCI results, the compressive strained indium gallium arsenide/GaAs DFLs show an atomically flat surface with a root mean square value of 1.288 nm and minimum threading dislocation density (TDD) value of 2.4 × 107 cm−2. For lattice‐matched DFLs, the indium gallium phosphide/GaAs DFLs are more effective in reducing the TDD than aluminum gallium arsenide/GaAs DFLs. Finally, we found that the strained DFLs can block propagate TDD effectively. The strained DFLs on the 725‐μm‐thick Si substrate can be used for the large‐scale integration of GaAs on Si with less bowing and low TDD.

A novel fan-out wafer-level packaging (FOWLP) technology with double-sided redistribution layers (RDLs) and tall copper vertical interconnects is described. The design of a dual-polarized magnetoelectric (ME) dipole antenna based on this new packaging technology is presented. It is shown that the antenna with a size of $10\times10$ mm2 achieves good impedance matching and a stable radiation pattern over a wide bandwidth from 25 to 43 GHz, which can cover most of the millimeter-wave (mmWave) bands of the fifth-generation (5G) mobile networks in different countries. The measurement results demonstrate that the antenna is well suited for FOWLP technology and can be used for phased-array modules in 5G wireless communication systems.

Funding Information: This work was financially supported by NanoLund, Myfab, the Swedish Research Council, the Swedish Energy Agency, and the Knut and Alice Wallenberg Foundation. Publisher Copyright: © 2021 The Authors. Published by American Chemical Society. Nanowire solar cells have the potential to reach the same efficiencies as the world-record III-V solar cells while using a fraction of the material. For solar energy harvesting, large-area nanowire solar cells have to be processed. In this work, we demonstrate the synthesis of epitaxial InP nanowire arrays on a 2 inch wafer. We define five array areas with different nanowire diameters on the same wafer. We use a photoluminescence mapper to characterize the sample optically and compare it to a homogeneously exposed reference wafer. Both steady-state and time-resolved photoluminescence maps are used to study the material's quality. From a mapping of reflectance spectra, we simultaneously extract the diameter and length of the nanowires over the full wafer. The extracted knowledge of large-scale nanowire synthesis will be crucial for the upscaling of nanowire-based solar cells, and the demonstrated wafer-scale characterization methods will be central for quality control during manufacturing.

Field-Plate (FP) MOSFET structure has been studied to get higher performance characteristics. To get low drift layer resistance, reduction of the trench width is one typical method with FP-MOSFET because it enables us to design the fine cell pitch of the FP-MOSFET. The main method for reducing the trench width is to design large trench angle. However large trench angle for better characteristics causes some challenges. And process window always becomes narrow to get excellent characteristic. For quality control of trench angle, we found that the wafer warpage was related to the trench angle at two process steps. We confirmed these mechanisms by simulation and experiment. Furthermore, we examined which process step was appropriate for monitoring the trench angle by wafer warpage. Finally, we acquired four correlation data related to the wafer warpage after field plate oxidation. Subsequently, we derived the regression equation for quality control and confirmed the validity of the equation.

A space-divided plasma-enhanced atomic layer deposition (PE-ALD) system in which disk and wafer rotate at the same time was developed. In the space-divided PE-ALD system, the disk and the wafer are each independently rotated and deposited. It has the advantage that high productivity and dispersion can be improved by controlling the rotation speed of the disk and wafer. Also, it can be applied to various processes by changing the design of the upper lid slightly. In this study, a study on the deposition characteristics of SiO2 thin films was conducted using the developed spatially divided PE-ALD system. The effect of the rotation speed of the disk and wafer on the deposition rate and the uniformity characteristics of the SiO2 thin film was confirmed, and a study on the correlation with the wet etch rate was conducted.

Close integration of transducer arrays with supporting electronic circuits is essential in achieving efficient and compact ultrasound systems. An integral part of hybrid integration of 2D CMUT array to CMOS electronics is the introduction of through-glass-via (TGV) interconnects in glass substrates as an integral part of the 2D CMUT array fabrication. Micro-cracks around via locations, via discontinuity, and poor coplanarity between the vias and glass substrate are some of the challenges with laser-drilled, paste-filled copper-through-glass-via (Cu-TGV) interconnects. This study provides a detailed fabrication process for making $32\times 32$ -element 2D CMUT arrays on a composite glass substrate incorporating silicon-through-glass vias (Si-TGV) as interconnects using sacrificial release approach. On one column of a fabricated 2D CMUT array, we measured a mean resonant frequency of 5.6 MHz in air and an average device capacitance of 1.5 pF. With the introduction of a buried top electrode in the device structure, we achieved a collapse voltage of 93 V, which is considerably lower than the collapse voltage measured in our previously demonstrated 2D CMUT arrays with top electrode on top of the nitride plate. The fabricated array is flip-chip bonded on a custom-designed driving integrated circuit to demonstrate the complete system operation. We measured a peak-to-peak pressure of 1.82 MPa at 3.4 MHz, and 5 mm from the array surface in a 0.33 mm focal spot size. [2021-0101]

Different combinations of metal thin films were investigated as metal interconnect for miniaturized microelectromechanical system (MEMS) encapsulation with stable electrical properties and sealing capability. The candidates of metal as the adhesion layer include Cr, Ti, and Ta. Metals Pt and Pd are the selection for the diffusion barrier layer. Comparison results of adhesion tests, stress measurements, and aging tests show that the interconnect of Ti-Pd-Au has the best stability in MEMS devices. After the screening process, the analyses of scanning acoustic tomography (SAT), scanning electron microscope (SEM), and pull test verify that the symmetric and ultrathin Ti-Pd-Au structure can be bonded well for the sealing process. Furthermore, the plasma treatment was conducted to reduce the thermal budget of encapsulation. The reliability tests present the bonding scheme with plasma treatment can withstand rapid temperature variation and high moisture for a long duration. All the results show that the interconnect of Ti-Pd-Au simultaneously used in the sealable encapsulation has a great potential for advanced miniaturized MEMS packaging.

A novel electron beam detector made on Si wafers by the advanced CMOS FinFET processes has been proposed in this study. Through electron beam (e-Beam) charging of on-wafer sensing pads, electron dosage can be registered on the detector for follow-up read-out. Without external power or battery connections, this detector has successfully delivered on-chip dosage, intensity, and energy after e-Beam exposure.

This article focuses on the material properties of two III-V semiconductors, AlGaAs and GaInAsP, and their usage as middle cell absorber materials in a wafer-bonded III-V//Si triple-junction solar cell. To this end single-junction solar cells were grown epitaxially lattice matched on GaAs wafers using metalorganic vapor phase epitaxy. By optimizing the growth temperature and the V/III ratio we could increase the open-circuit voltage at a target absorber band gap of 1.50 eV by up to 100 mV. In the future these results will be implemented into two-terminal III-V//Si triple-junction solar cells to increase the conversion efficiency beyond 35% under the AM1.5g solar spectrum.

Integrating two-dimensional (2D) materials into semiconductor manufacturing lines is essential to exploit their material properties in a wide range of application areas. However, current approaches are not compatible with high-volume manufacturing on wafer level. Here, we report a generic methodology for large-area integration of 2D materials by adhesive wafer bonding. Our approach avoids manual handling and uses equipment, processes, and materials that are readily available in large-scale semiconductor manufacturing lines. We demonstrate the transfer of CVD graphene from copper foils (100-mm diameter) and molybdenum disulfide (MoS2) from SiO2/Si chips (centimeter-sized) to silicon wafers (100-mm diameter). Furthermore, we stack graphene with CVD hexagonal boron nitride and MoS2 layers to heterostructures, and fabricate encapsulated field-effect graphene devices, with high carrier mobilities of up to \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$4520\;{\mathrm{cm}}^2{\mathrm{V}}^{ - 1}{\mathrm{s}}^{ - 1}$$\end{document}4520cm2V−1s−1. Thus, our approach is suited for backend of the line integration of 2D materials on top of integrated circuits, with potential to accelerate progress in electronics, photonics, and sensing., The existing integration approaches for 2D materials often degrade material properties and are not compatible with industrial processing. Here, the authors devise an adhesive wafer bonding strategy to transfer and stack monolayers, suitable for back end of the line integration of 2D materials.

Advancements in technology have made deep learning a hot research area, and we see its applications in various fields. Its widespread use in silicon wafer defect recognition is replacing traditional machine learning and image processing methods of defect monitoring. This article presents a review of the deep learning methods employed for wafer map defect recognition. A systematic literature review (SLR) has been conducted to determine how the semiconductor industry is leveraged by deep learning research advancements for wafer defects recognition and analysis. Forty-four articles from well-known databases have been selected for this review. The articles’ detailed study identified the prominent deep learning algorithms and network architectures for wafer map defect classification, clustering, feature extraction, and data synthesis. The identified learning algorithms are grouped as supervised learning, unsupervised learning, and hybrid learning. The network architectures include different forms of Convolutional Neural Network (CNN), Generative Adversarial Network (GAN), and Auto-encoder (AE). Various issues of multi-class and multi-label defects have been addressed, solving data unavailability, class imbalance, instance labeling, and unknown defects. For future directions, it is recommended to invest more efforts in the accuracy of the data generation procedures and the defect pattern recognition frameworks for defect monitoring in real industrial environments.

Silicon wafer as a direct material is one of the vital parts of a semiconductor product. Wastages on manufacturing plants that pulls the yield down should be addressed innovatively and accurately. This paper focused on the phenomenon of broken wafers at wafer taping process during wafer preparation. Using a wafer taper machine, silicon wafers are covered by an industrial tape as preparation for the next process. During processing and wafers are placed on wafer boat, unexpected phenomenon of broken wafers due to unwanted falling was encountered. Findings was due to the unintentional dragging of the machine’s robot arm after wafer processing. The problem is resolved through simulation and experiments using statistical analysis. As a result, an optimized machine parameter setting was defined to eliminate the said rejection. Statistical analysis was of a big help in resolving the said phenomenon and improved the process yield of the manufacturing.

Semiconductor Companies and Industries soar high as the trend for electronic gadgets and devices increases. Transition from “manual” to “fully automatic” application is one of the advantages why consumer adapt to changes and prefer electronic devices as one of daily answers. Individuals who admire these electronic devices often ask how they are made. As we look inside each device, we can notice interconnected microchips commonly called IC (Integrated Circuit). These are specially prepared silicon wafers where integrated circuit are developed. Commonly, each device is composed of numerous microchips depending on the design and functionality IC production is processed from “front-end” to “back-end” assembly. Front-end assembly includes wafer fabrication where electrical circuitry is prepared and integrated to every single silicon wafers. Back-end assembly covers processing the wafer by cutting into smaller individual and independent components called “dice”. Each dice will be placed into Leadframe, bonded with wires prior encapsulating with mold compounds. After molding, each IC will be cut through a process called singulation. Afterwards, all molded units are subjected for functional testing. Dice is central to each IC; it is where miniature transistor, resistor and capacitor are integrated to form complex small circuitry in microchips. Pre-assembly (Pre-assy) stations have the first hand prior to all succeeding stations. Live wafers are primary direct materials processed in these stations. Robust work instruction and parameter must be practiced during handling and processing to avoid gross rejection and possible work-related defects. The paper is all about the challenges to resolve and improved the backside chippings in 280um wafer thickness in mechanical dicing saw. The conventional Mechanical dicing process induce a lot of mechanical stress and vibration during the cutting process which oftentimes lead to backside chipping and die crack issues. However, backside chippings can mitigate with proper selection of parameter settings and understand the silicon wafer properties.

The rise of various Wafer technologies has been developed based on industries and applications requirement. Highest quality of material characterization is complex and requires specialized process equipment and manufacturing procedures to meet defined design standards. The paper presents distinctive glass wafer-level fabrication technology that will enhance its properties with respect to pattern recognition system (PRS) at back-end manufacturing for industrial applications. Feasibility of colored glass wafer has been built into proposed conception to manufacture wafer-level packaging. The idea from transparent to colored glass wafer came from manufacturing key challenges that cutting sequence during pattern recognition cannot be distinguished. The proposed solution will mitigate high risk of misaligned cut at wafer sawing and its potential attachment on leadframe during die attach. glass wafer dice, transparent in nature, intermittently encountered multiple PRS assist during Wafer sawing and die attach as it hardly recognizes its cutting positions. Since dependent of machine capability limitations, misaligned cut is inevitable and usually happen occasionally. Addressing its unrecognizable characteristic, proposed colored glass wafer and with visible outline and saw lane fabrication was conceptualized instead of seeking ideal and high equipment model that can differentiate its opaque feature. The colored glass wafer and with visible outline and saw lane naturally creates segmentation visibly and will not be parameter dependent during manufacturing.

Wafer test is carried out after integrated circuits (IC) fabrication to screen out bad dies. In addition, the results can be used to identify problems in the fabrication process and improve manufacturing yield. However, the wafer test itself may induce defects to otherwise good dies. Test-induced defects not only hurt overall manufacturing yield but also create problems for yield learning, so the source problems in testing should be identified quickly. In the wafer acceptance test process, dies are probed in a predetermined order, so test-induced defects, also known as site-dependent faults, exhibit specific patterns that can be effectively captured in test paths. In this paper, we analyze characteristics of test-induced defect patterns and define features that can be used by machine learning algorithms for the automatic detection of test-induced defects. Therefore, defective dies caused by the wafer test can be retested for yield improvement. Test data from six real products are used to validate the proposed method. Several machine learning algorithms have been applied, and experimental results show that our method is effective to distinguish between test-induced and fabrication-induced defects. On average, the prediction accuracy is higher than 97%.

Summary The extension of graphitic carbon nitride (g-CN) materials into optoelectronic applications beyond photocatalysis has long been anticipated due to their non-metallic composition, moderate electronic band gap, and excellent stability. However, large-scale synthesis of uniform two-dimensional (2D) g-CN films with high crystallinity and tunable thickness remains the bottleneck for their future applications in optoelectronic devices. Here, a vapor-phase transport-assisted condensation method has been developed for the wafer-scale synthesis of uniform 2D g-CN films with tunable thickness. First-principle calculations indicate the direct condensation from melem to heptazine-based carbon nitride enables the formation of high-quality g-CN films. A facile water-assisted transfer strategy is developed for subsequent fabrication on arbitrary substrate. A free-standing flexible photodetector array with strain-insensitive responsibility is demonstrated with the g-CN films as imaging pixels. This study provides a convenient route to wafer-scale growth of high-quality 2D g-CN films and paves the way to the g-CN-based electronic and optoelectronic devices.

Diabetic foot difficulties are the most usually occurring problems globally, resulting in economic disasters for the patients, families, and society. In patients with diabetes, the risk of emerging foot ulcers is 25% high. It has also been in the record that one lower limb amputation occurs every 30 seconds in patients with diabetes worldwide. Novel methods of drug delivery and wound dressing have to develop to solve the lower limb amputation crisis. One such novel method is "Lyophilized wafer formulation." It is an upcoming medicated dressing material that can enhance wound healing and the potential to ingest vast quantities of exudates from Chronic wounds. That can have been formulating by lyophilizing hydrogel of absorbent polymers such as Calcium Alginate, Carrageenan, Thiolated Chitosan, and plasticizer to enhance flexibility withstand the day to day mechanical stress, covered with some adhesive and protective backing layer. Unless it passes evaluation tests such as Fourier-transform infrared spectroscopy (FTIR), Differential scanning calorimetry (DSC), Scanning electron microscopy (SEM), Exudate handling property, Folding endurance, In-vitro, In-vivo drug release profile, and Gamma-irradiation sterilizes wafer formulation, and it should not administrate directly. Lyophilized wafer formulation will be the most acceptable medicated dressing material in the future that will be useful to treat the normal wound. The wound formation because of diabetic foot ulcer (DFU) infections as there will be site-specific delivery of the drug, packed with an advantage to self administer and easy termination of the drug that can achieve just by removing the wafer case of drug toxicity.

Nowadays, semiconductors and electronics are becoming part of our everyday activities. As the Integrated circuits become more useful to people, it also requires more function, which contain more complex and compact components. Aligned to this package requirement, the more challenging it become to package development as Silicon technology becomes more critical and complex from bare silicon to conventional MOS technology to Ultra Low-K, which requires a different strategy. The new process development in the Semiconductor industry is a necessity to cope up with these new technologies. Low-k devices always pose a big challenge in achieving good dicing quality. This is because of the weak mechanical properties of the low-k dielectric material used. Mechanical Sawing is the most popular cutting method for silicon, but with Ultra low-K technology, using mechanical sawing will lead to various sawing defects such as chippings and delamination [1,2]. These leads to the introduction of Laser Grooving to get rid of these dilemmas. Laser grooving uses heat to eradicate metals on this very thin metal wafer dicing saw streets in preparation for wafer saw process to prevent topside chippings and delamination/metal peel off [3]. These defects are not acceptable especially since the product application is a chip card. Since chip cards must be flexible and durable, they require higher die and package strength to serve its purpose. To achieve such package requirement, different method was evaluated such as standard mechanical dicing, standard Laser Grooving and the PI laser groove. The paper will discuss how we were able to achieve the quality requirement for Ultra Low-K and at the same time eliminating top reject contributor during startup of this device.

This article proposes a 3-D-based redundancy scheme for the stacked dynamic random-access memory (DRAM) systems, which enables highly efficient productivity with the wafer-on-wafer (WOW) technology. Vertically replaceable block scheme and redundantly added wafer stack(s) are the keys of this technique. Memory bank replacement of the vertical combinations is taken into consideration. Random defect yield loss, which is a fundamental barrier for both the WOW technology and the leading-edge technologies, is dealt with in this study. Not only 4, 8, and 12 layers, but also 17 (16+1), 25 (24+1), and 33 (32+1) layers can be targeted. Therefore, this technique makes the WOW technology as another system scaling enabler.

In every new technology developed and introduced to the manufacturing floor, particularly in the wafer preparation, entails problems that later induce defects affecting the wafer yield. This paper discusses the optimization of wafer preparation parameters, particularly the tensionless backgrinding tape lamination and DAF cut vacuum control, that mitigates wafer yield detractors such as edge cut, kerf shift and dice pop-out. Based on the evaluation results, tensionless backgrinding lamination affects the kerf shifting and edge cutting, and with proper vacuum control to attain zero dice pop-out process.

This study presents a novel structure for electrochemical discharge machining (WECDM) of nonconductive quartz wafers with continuous electrolyte flow. A small and stable insulating gas film was formed in the gap between the wire electrode and workpiece to achieve improved WECDM in a small area. A pulsed power supply and ultrasonic-assisted processing were combined to machine the quartz workpiece. This approach can considerably reduce unstable discharge phenomena and discharge heat generation. Furthermore, it can avoid easy breakage and subsequent loss of the wire electrode. The machining accuracy and the machining speed can be improved using appropriate WECDM parameters. Experimental results revealed that a minimum slot width of 0.208 mm was obtained at a voltage of 44 V, duration time of 100 μs, duty factor of 40%, feed rate of 20 μm/s, and ultrasonic power level of 2. Accordingly, the proposed design can obtain a smaller slot width, which improves processing accuracy.

This paper presents an innovative Through-Load element aimed at characterization applications at mm-wave frequencies. The proposed structure can behave as a Through connection or as a 50- $\Omega $ load depending on a DC control voltage. Among other potential applications, this system can be used to implement a transfer switch or an attenuator. A demonstrator was fabricated and measured in the STM 55-nm BiCMOS technology. Over a wide bandwidth, from 55 GHz up to 170 GHz, experimental measurements demonstrate a maximum 1.6-dB of insertion loss when behaving as a Through connection and a minimum 14-dB of insertion loss when behaving as a 50- $\Omega $ load. In both cases, the return loss is better than 10 dB. The insertion loss at 90 GHz is 0.6 dB for the Through connection and 20 dB for the 50- $\Omega $ load connection.

In this study we report chip fabrication process that allows the laser lift-off of the sapphire substrate for the transfer of the GaN based thin film flip chip to the carrier wafer. The fabrication process includes 365-nm ultraviolet flip chip LED wafer align bonding with through-AlN-via wafer and sapphire laser lift-off. n-holes with the diameter of 100 µm were etched on the GaN epilayers for accessing n-type GaN. Through-AlN-via size was 110-µm and filled by Cu electroplating method for the electrical connection. Mechanical stabilization to prevent the GaN epilayers cracking and fragmentation during laser lift-off was achieved by utilizing epoxy based SU-8 photoresist support.

Wafer map defect pattern recognition provides useful clues to yield learning. However, most wafer maps have no special spatial patterns and are full of noises, which make pattern recognition difficult. Especially, recognizing scratch and line types of defect patterns is challenging for process and test engineers. It takes a lot of manpower to identify such patterns, as hidden defective dies may exist on the scratch contour and become discontinuity points. Hidden scratch defective dies may suffer from latent and leakage faults, which usually deteriorate quickly and need to be screened by burn-in test to improve quality. A possible solution is to locate the obscure defective dies in scratch patterns and mark them as faulty. As a result, the quality and reliability of products is significantly improved and cost of final test is reduced. In this article, we propose a systematic methodology to search for potential hidden scratch/line defects in wafers. A five-phase method is developed to enhance wafer maps such that automatic hidden scratch defect pattern recognition can be carried out with high accuracy. Experimental results show the proposed method achieves higher than 89% recognition rate for scratch/line patterns, and higher than 94% for all common wafer defect pattern types.

Silicon (Si)-based composites have attracted extensive attention for photoelectrochemical (PEC) application. Herein, micropyramidal textured Si wafer was constructed by wet chemical etching method. Hydrothermally synthesized Fe3O4 nanospheres were further deposited on the micropyramids by a simple dip-coating approach. The integrated Fe3O4 nanospheres and Si micropyramids (denoted as Fe3O4@SiMPs) revealed 20 times of higher PEC efficiency than planar Si wafer, without obvious photocurrent decay and crystalline structure change during chronoamperometry test. The greatly enhanced PEC performance of Fe3O4@SiMPs is largely attributed to the seamless integration of Si micropyramids and Fe3O4 nanospheres. The micropyramidal textured structure can enhance light absorption by reducing the surface reflectance and enhancing the light trapping effect. The micropyramids and Fe3O4 nanospheres on the surface of planar Si wafer offer more specific surface area for the contact of electrode with electrolyte. The Fe3O4 nanospheres not only protect the micropyramids from corrosion, but also accelerate the PEC kinetics by promoting charge transfer between the electrode and the electrolyte. This study can inspire the optimal design of Si wafer-based nanocomposites as efficient PEC catalysts for overall water splitting.

Orthognathic surgery became a rapidly evolving procedure, innovations in virtual planning offers a potentially superior alternative to the conventional model surgery. The variation in techniques, virtual planning software’s, imaging machines and 3D printing options made virtual planning an appealing field, however, the accuracy of these methods remains subject to accuracy assessment. A virtual planning technique was elaborated and validated. Both intermediate a final wafer of seven orthognathic patients were tested revealing mean deviation in intermediate wafer group of 0.64±0.33 mm; while the mean deviation in final wafer group of 0.53±0.10 mm .The virtual technique adopted by our team for construction of occlusal wafers showed good fitting and almost no rocking or interference, minor interferences were caused by the remnants of the supports made during printed to support the 3D model during the process, these interferences were easily eliminated in the occlusal trial session with a finishing stone. In further model that complication was reduced by orienting the models during printing and relocating printing supports away from the fitting surface of the wafers.

Wafer identification (ID) is a serial number printed on the surface of wafer, which is used for indexing production process data in manufacture execution system. The automatic recognition of wafer ID is helpful to improve the level of automatic production. However, the existing equipment and methods mainly focus on single wafer-ID recognition, which require wafers to be taken out and placed on a specific platform, resulting in low efficiency. In this paper, we present a batch wafer-ID recognition method based on machine vision, including a specific designed image-acquisition system and recognition algorithms. Based on the priori information, we formulate a 3D model for the cassette and wafers to be registered with the features extracted from the image. Combined with image-processing techniques, the pose of wafers in the cassette is estimated to undistort the perspective deformation of wafer-ID characters, such that we can exploit a classic lightweight convolution neural network for character recognition. The proposed system can capture and recognize the whole image of a cassette of wafers at once, which does not need to take out the wafers from the cassette and avoids the risk of contamination. Extensive experiments were conducted to evaluate the performance of our proposed techniques by collecting the data set of wafer-ID images. The results show that our proposed 3D model-based rectification method can correct the character deformation effectively and enable the lightweight classifier to achieve high speed and high accuracy for batch wafer-ID recognition.

This paper reports a study of the effect of wafer tilt during dopant implantation on the performance of silicon PN phase shifter and traveling-wave Mach-Zehnder modulator. The PN phase shifter is designed and process simulated to include the effects of different fabrication processes in the device performance. The wafer tilt during implantation is varied from 0° to 3°, 5°, and 7°. The resulting crystal damage during dopant implantation to form the PN junction and the active concentration profile upon annealing, along with the formation of dopant–defect clusters, are discussed. Compared to 0° tilt, 7° tilt results in $1.58\times $ higher phase shift and better modulation efficiency. The overall phase shifter performance is improved using 5° wafer tilt for implantation resulting in $1.23\times $ lower absorption, $1.45\times $ better modulation efficiency, and $3.14\times $ higher 3 dB $RC$ modulation bandwidth for lumped-driven phase shifter. A traveling-wave electrode to enhance the modulation bandwidth is used, and the modulator performance for non-return-to-zero on-off-keying modulation with–2.5 V bias and 2.5 $\text{V}_{pp}$ drive signal across each arm is evaluated using a dual-arm push-pull drive. The sample with 5° tilt shows better traveling-wave and modulator high-speed characteristics compared to the other samples. Among the four samples with different wafer tilts, the sample with 0° tilt shows the worst phase shifter performance, and the sample with 3° tilt shows the worst modulator characteristics. The best overall performance is obtained for the sample with 5° tilt. Compared to the modulator with implantation at 0° tilt, the 5° tilted sample shows $2.3\times $ higher 6.4 dB electrical bandwidth and $1.36\times $ higher 3 dB electro-optic bandwidth at–2.5 V using a traveling-wave electrode with $1.48\times $ lower energy-per-bit for 5 km transmission at the KP4-forward-error-correction bit-error-rate threshold. The comparison of the effect of wafer tilt angles on various device metrics is presented and discussed.

In this work, we demonstrate the potential of a gallium nitride (GaN)-based visible-blind ultraviolet (UV) photodetector (PD) on a commercially viable 150-mm Si wafer. The influence of thermionic field emission (TFE) and Poole–Frenkel (PF) mechanisms on the current transport of the PD has been analyzed. Conduction due to the TFE mechanism dominates in the moderate electric fields (1.25 kV/cm ${ kV/cm), while the influence of PF is prominent at higher electric fields. A bulk trap energy level of 0.374 eV is obtained with PF conduction analysis. A high responsivity of 33.3 A/W at 15 V with a 362-nm incident wavelength has been achieved in the presence of an internal gain. The internal gain of the PD is also assisted by TFE and PF mechanisms. The PD exhibits a low dark current of 4.7 nA as well as high detectivity of $4.6\times 10^{12}$ Jones at the abovementioned bias. The demonstrated robustness and high performance show the promise of III–nitride PDs for commercial applications.

Inspired by the outstanding properties discovered in two-dimensional materials, the bottom-up generation of molecular monolayers is becoming again extremely popular as a route to develop novel functional materials and devices with tailored characteristics and minimal materials consumption. However, achieving a full-coverage over a large-area still represents a grand challenge. Here we report a molecular self-assembly protocol at the water surface in which the monolayers are strained by a novel solvent surface tension balance (SSTB) instead of a physical film balance as in the conventional Langmuir–Blodgett (LB) method. The obtained molecular monolayers can be transferred onto any arbitrary substrate including rigid inorganic oxides and metals, as well as flexible polymeric dielectrics. As a proof-of-concept, their application as ideal modification layers of a dielectric support for high-performance organic field-effect transistors (OFETs) has been demonstrated. The field-effect mobilities of both p- and n-type semiconductors displayed dramatic improvements of 1–3 orders of magnitude on SSTB-derived molecular monolayer, reaching values as high as 6.16 cm2 V–1 s–1 and 0.68 cm2 V–1 s–1 for pentacene and PTCDI-C8, respectively. This methodology for the fabrication of wafer-scale and defect-free molecular monolayers holds potential toward the emergence of a new generation of high-performance electronics based on two-dimensional materials.

Summary Two-dimensional (2D) graphdiyne (GDY) is a promising floating-gate material for flexible optoelectronic flash memory owing to its fascinating electrical and optical properties. However, research in GDY-based flash memory is still in its infancy owing to the huge challenge in the synthesis of large-area and ultrathin GDY films with high quality and uniformity. Here, an electric double-layer-confined strategy is proposed to synthesize a wafer-scale GDY film with thickness of 1 nm. Then, a two-terminal top-floating-gated optoelectronic memory with multibit storage capability is investigated using GDY as a photoresponsive top-floating gate. Benefiting from the excellent charge storage capability and high photoresponse of GDY, this device exhibits over 256 distinct storage levels (8 bits) with signal-to-noise ratios larger than 100. Moreover, the fully 2D material and two-terminal architecture endows the device with robust bending stability for over 1,000 bending circles, paving the way to develop wearable electronics.

Silicon carbide (SiC) is an important semiconductor material for a variety of electronic and optoelectronic applications owing to the unique combination of its superior electronic and physical properties. In order to continuously improve the crystal quality and improve device performance, obtaining a clear understanding of the defect types and their distribution and potential influence on device operation is of great importance. In this study, 6H-SiC crystals grown by physical vapor transport (PVT) have been characterized by synchrotron monochromatic beam x-ray topography (SMBXT). By recording six different $$11{\bar{2}},12$$ grazing incidence reflections and analyzing the contrast patterns of threading screw dislocations (TSDs), threading edge dislocations (TEDs), threading mixed dislocations (TMDs), and basal plane dislocations (BPDs) observed in conjunction with ray-tracing simulation, the Burgers vectors of these dislocations have been determined. This successfully demonstrated a direct Burgers vector determination approach for each type of dislocation. Understanding these dislocation types and their distributions in 6H-SiC wafers can provide crucial feedback for pursuing crystal quality enhancement during growth process. High-resolution x-ray diffraction (HRXRD) has been performed on the wafer to carry out the rocking curve analysis of areas with different degrees of lattice distortion.

The integration of gallium nitride (GaN) nanowire light-emitting diodes (nanoLEDs) on flexible substrates offers opportunities for applications beyond rigid solid-state lighting (e.g., for wearable optoelectronics and bendable inorganic displays). Here, we report on a fast physical transfer route based on femtosecond laser lift-off (fs-LLO) to realize wafer-scale top–down GaN nanoLED arrays on unconventional platforms. Combined with photolithography and hybrid etching processes, we successfully transferred GaN blue nanoLEDs from a full two-inch sapphire substrate onto a flexible copper (Cu) foil with a high nanowire density (~107 wires/cm2), transfer yield (~99.5%), and reproducibility. Various nanoanalytical measurements were conducted to evaluate the performance and limitations of the fs-LLO technique as well as to gain insights into physical material properties such as strain relaxation and assess the maturity of the transfer process. This work could enable the easy recycling of native growth substrates and inspire the development of large-scale hybrid GaN nanowire optoelectronic devices by solely employing standard epitaxial LED wafers (i.e., customized LED wafers with additional embedded sacrificial materials and a complicated growth process are not required).

As a kind of robotic cells, cluster tools are widely used for semiconductor wafer fabrication processes since they provide a reconfigurable and efficient environment. With recent advances in new semiconductor materials, the circuit line width has continuously being shrunk down, which brings new challenges for manufacturers. They require that a wafer should be moved away from a processing chamber as soon as possible after its processing is finished. To ensure high-quality integrated circuits in a wafer, its post-processing residency time must be minimized. It is also highly desirable to maximize the throughput of robotic cluster tools. This article aims at scheduling such tools with multiple objectives subject to wafer residency time constraints. To do so, new algorithms are proposed to calculate robot waiting time delicately upon the analysis of particular events of robot waiting for dual-blade robotic tools and optimally schedule such tools. The numerical results of industrial examples show that the proposed algorithms can provide an effective method to find schedules for dual-blade cluster tools such that multiple objectives are optimized.

Defect pattern recognition (DPR) of wafer maps is critical for determining the root cause of production defects, which can provide insights for the yield improvement in wafer foundries. During wafer fabrication, several types of defects can be coupled together in a piece of wafer, it is called mixed-type defects DPR. To detect mixed-type defects is much more complicated because the combination of defects may vary a lot, from the type of defects, position, angle, number of defects, etc. Deep learning methods have been a good choice for complex pattern recognition problems. In this article, we propose a deformable convolutional network (DC-Net) for mixed-type DPR (MDPR) in which several types of defects are coupled together in a piece of wafer. A deformable convolutional unit is designed to selectively sample from mixed defects, then extract high-quality features from wafer maps. A multi-label output layer is improved with a one-hot encoding mechanism, which decomposes extract mixed features into each basic single defect. The experiment results indicate that the proposed DC-Net model outperforms conventional models and other deep learning models. Further results of the interpretable analysis reveal that the proposed DC-Net can accurately pinpoint the defects areas of wafer maps with noise points, which is beneficial for mixed-type DPR problems.

In this article, Si (100) inks’ array is integrated on SiN/AlGaN/GaN substrate to demonstrate a zero deviation and wafer-scale Si–GaN monolithic integration by transfer printing and self-aligned etching technology. During the heterogeneous integration process, it does not depend on any equipment, such as metal–organic chemical vapor deposition (MOCVD) (epitaxial growth) and wafer bonding machine (wafer bonding) which are costly. The transferred Si and SiN/AlGaN/GaN substrates show an excellent interface morphology. Based on this material system, the monolithic integrated E-mode cascode FETs are demonstrated with good uniformity. The ${I}_{GS}$ is below 10−5 mA/mm within a large gate voltage swing of ±18 V. Threshold voltages of a series of cascode FETs are extracted as 2.2 V (±0.2 V). This novel low-cost technology shows great potential in monolithic heterogeneous integration.