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Reservoir computing (RC) possesses a simple architecture and high energy efficiency for time‐series data analysis through machine learning algorithms. To date, RC has evolved into several innovative variants. The next generation reservoir computing (NGRC) variant, founded on nonlinear vector autoregression (NVAR) distinguishes itself due to its fewer hyperparameters and independence from physical random connection matrices, while yielding comparable results. However, NGRC networks struggle with massive Kronecker product calculations and matrix‐vector multiplications within the read out layer, leading to substantial efficiency challenges for traditional von Neumann architectures. In this work, a hybrid digital‐analog hardware system tailored for NGRC is developed. The digital part is a Kronecker product calculation unit with data filtering, which realizes transformation of nonlinear vector of the input linear vector. For matrix‐vector multiplication, a computing‐in‐memory architecture based on resistive random access memory array offers an energy‐efficient hardware solution, which markedly reduces data transfer and greatly improve computational parallelism and energy efficiency. The predictive capabilities of this hybrid NGRC system are validated through the Lorenz63 model, achieving a normalized root mean square error (NRMSE) of 0.00098 and an energy efficiency of 19.42TOPS W−1. [ABSTRACT FROM AUTHOR]

Reservoir computing (RC) possesses a simple architecture and high energy efficiency for time‐series data analysis through machine learning algorithms. To date, RC has evolved into several innovative variants. The next generation reservoir computing (NGRC) variant, founded on nonlinear vector autoregression (NVAR) distinguishes itself due to its fewer hyperparameters and independence from physical random connection matrices, while yielding comparable results. However, NGRC networks struggle with massive Kronecker product calculations and matrix‐vector multiplications within the read out layer, leading to substantial efficiency challenges for traditional von Neumann architectures. In this work, a hybrid digital‐analog hardware system tailored for NGRC is developed. The digital part is a Kronecker product calculation unit with data filtering, which realizes transformation of nonlinear vector of the input linear vector. For matrix‐vector multiplication, a computing‐in‐memory architecture based on resistive random access memory array offers an energy‐efficient hardware solution, which markedly reduces data transfer and greatly improve computational parallelism and energy efficiency. The predictive capabilities of this hybrid NGRC system are validated through the Lorenz63 model, achieving a normalized root mean square error (NRMSE) of 0.00098 and an energy efficiency of 19.42TOPS W−1.

In this work, a machine learning‐assisted prediction model is proposed to analyze the reliability issues in the 28 nm resistive random access memory (RRAM) chip with raw data measured from RRAM test chip. The neural network of long‐short time memory (LSTM) is trained by the voltages and resistance during the endurance test (input vectors) and generates the output of the dichotomy states with a satisfied testing result >83.08%. According to the prediction results, the "real fail" state or "fake fail" state of the devices can get in the future. By collaborating with a well‐designed resurrection algorithm (RA), the percentage of real and fake failed cells dropped by 35% and 29%, respectively. Besides, the tail bits in retention significantly reduced from 33% to 14.6% due to the reduction of oxygen vacancies in the gaps of conducting filaments by applying ten consecutive cycles of RA. This intelligent prediction and repair module can prolong the lifetime of RRAM chips effectively in practical applications. [ABSTRACT FROM AUTHOR]

This article investigates resistive random access memory (ReRAM) crossbar memory arrays, which is a notable development in non-volatile memory technology. We highlight ReRAM's competitive edge over NAND, NOR Flash, and phase-change memory (PCM), particularly in terms of endurance, speed, and energy efficiency. This paper focuses on the architecture of crossbar arrays, where memristive devices are positioned at intersecting metal wires. We emphasize the unique resistive switching mechanisms of memristors and the challenges of sneak path currents and delve into the roles and configurations of selectors, particularly focusing on the one-selector one-resistor (1S1R) architecture with an insulator–metal transition (IMT) based selector. We use SPICE simulations based on defined models to examine a 3 × 3 1S1R ReRAM array with vanadium dioxide selectors and titanium dioxide film memristors, assessing the impact of ambient temperature and critical IMT temperatures on array performance. We highlight the operational regions of low resistive state (LRS) and high resistive state (HRS), providing insights into the electrical behavior of these components under various conditions. Lastly, we demonstrate the impact of selector presence on sneak path currents. This research contributes to the overall understanding of ReRAM crossbar arrays integrated with IMT material-based selectors. [ABSTRACT FROM AUTHOR]

This article investigates resistive random access memory (ReRAM) crossbar memory arrays, which is a notable development in non-volatile memory technology. We highlight ReRAM’s competitive edge over NAND, NOR Flash, and phase-change memory (PCM), particularly in terms of endurance, speed, and energy efficiency. This paper focuses on the architecture of crossbar arrays, where memristive devices are positioned at intersecting metal wires. We emphasize the unique resistive switching mechanisms of memristors and the challenges of sneak path currents and delve into the roles and configurations of selectors, particularly focusing on the one-selector one-resistor (1S1R) architecture with an insulator–metal transition (IMT) based selector. We use SPICE simulations based on defined models to examine a 3 × 3 1S1R ReRAM array with vanadium dioxide selectors and titanium dioxide film memristors, assessing the impact of ambient temperature and critical IMT temperatures on array performance. We highlight the operational regions of low resistive state (LRS) and high resistive state (HRS), providing insights into the electrical behavior of these components under various conditions. Lastly, we demonstrate the impact of selector presence on sneak path currents. This research contributes to the overall understanding of ReRAM crossbar arrays integrated with IMT material-based selectors.

Diabetic retinopathy (DR) is a leading cause of permanent vision loss worldwide. It refers to irreversible retinal damage caused due to elevated glucose levels and blood pressure. Regular screening for DR can facilitate its early detection and timely treatment. Neural network-based DR classifiers can be leveraged to achieve such screening in a convenient and automated manner. However, these classifiers suffer from reliability issue where they exhibit strong performance during development but degraded performance after deployment. Moreover, they do not provide supplementary information about the prediction outcome, which severely limits their widespread adoption. Furthermore, energy-efficient deployment of these classifiers on edge devices remains unaddressed, which is crucial to enhance their global accessibility. In this paper, we present a reliable and energy-efficient hardware for DR detection, suitable for deployment on edge devices. We first develop a DR classification model using custom training data that incorporates diverse image quality and image sources along with improved class balance. This enables our model to effectively handle both on-field variations in retinal images and minority DR classes, enhancing its post-deployment reliability. We then propose a pseudo-binary classification scheme to further improve the model performance and provide supplementary information about the model prediction. Additionally, we present an energy-efficient hardware design for our model using memristor-based computation-in-memory, to facilitate its deployment on edge devices. Our proposed approach achieves reliable DR classification with three orders of magnitude reduction in energy consumption over state-of-the-art hardware platforms.

Analog memory presents a promising solution in the face of the growing demand for energy-efficient artificial intelligence (AI) at the edge. In this study, we demonstrate efficient deep neural network transfer learning utilizing hardware and algorithm co-optimization in an analog resistive random-access memory (ReRAM) array. For the first time, we illustrate that in open-loop deep neural network (DNN) transfer learning for image classification tasks, convergence rates can be accelerated by approximately 3.5 times through the utilization of cooptimized analog ReRAM hardware and the hardware-aware Tiki-Taka v2 (TTv2) algorithm. A simulation based on statistical 14 nm CMOS ReRAM array data provides insights into the performance of transfer learning on larger network workloads, exhibiting notable improvement over conventional training with random initialization. This study shows that analog DNN transfer learning using an optimized ReRAM array can achieve faster convergence with a smaller dataset compared to training from scratch, thus augmenting AI capability at the edge. [ABSTRACT FROM AUTHOR]

Abstract In this work, a machine learning‐assisted prediction model is proposed to analyze the reliability issues in the 28 nm resistive random access memory (RRAM) chip with raw data measured from RRAM test chip. The neural network of long‐short time memory (LSTM) is trained by the voltages and resistance during the endurance test (input vectors) and generates the output of the dichotomy states with a satisfied testing result >83.08%. According to the prediction results, the “real fail” state or “fake fail” state of the devices can get in the future. By collaborating with a well‐designed resurrection algorithm (RA), the percentage of real and fake failed cells dropped by 35% and 29%, respectively. Besides, the tail bits in retention significantly reduced from 33% to 14.6% due to the reduction of oxygen vacancies in the gaps of conducting filaments by applying ten consecutive cycles of RA. This intelligent prediction and repair module can prolong the lifetime of RRAM chips effectively in practical applications.

Analog memory presents a promising solution in the face of the growing demand for energy-efficient artificial intelligence (AI) at the edge. In this study, we demonstrate efficient deep neural network transfer learning utilizing hardware and algorithm co-optimization in an analog resistive random-access memory (ReRAM) array. For the first time, we illustrate that in open-loop deep neural network (DNN) transfer learning for image classification tasks, convergence rates can be accelerated by approximately 3.5 times through the utilization of co-optimized analog ReRAM hardware and the hardware-aware Tiki-Taka v2 (TTv2) algorithm. A simulation based on statistical 14 nm CMOS ReRAM array data provides insights into the performance of transfer learning on larger network workloads, exhibiting notable improvement over conventional training with random initialization. This study shows that analog DNN transfer learning using an optimized ReRAM array can achieve faster convergence with a smaller dataset compared to training from scratch, thus augmenting AI capability at the edge.

Resistive switching devices are candidates to be used as weight for the future hardware realization of neuronal networks. Herein, these resistive switches base on oxygen vacancy migration and can be toggled between different resistance states. Internal processes lead to a variability over time in these states. To understand this, a dynamical model is developed, which links the internal physical mechanism to the current response. Thereby, the electronic current is calculated by tunneling processes over oxygen vacancies. The model allows to understand the physical transport properties and the current–voltage dependence. Integrating ionic hopping processes clarifies the variability in the electronic conduction. The derived model does not require empirical input parameters and only depends on the properties of the materials. This allows to use literature values and independently compare them to electrical measurements. The model predicts the experiments correctly. Thereupon, the physical properties of the conduction are investigated with respect to the transport over discrete energy levels, which change under the hopping of oxygen vacancies. Afterwards, the current level and variability are simulated for increasing oxygen vacancy concentrations to investigate analog switching, which is required for neuronal network layers. Finally, the variability is tested with multiple interacting cells in a neuronal layer. [ABSTRACT FROM AUTHOR]

Resistive switching devices are candidates to be used as weight for the future hardware realization of neuronal networks. Herein, these resistive switches base on oxygen vacancy migration and can be toggled between different resistance states. Internal processes lead to a variability over time in these states. To understand this, a dynamical model is developed, which links the internal physical mechanism to the current response. Thereby, the electronic current is calculated by tunneling processes over oxygen vacancies. The model allows to understand the physical transport properties and the current–voltage dependence. Integrating ionic hopping processes clarifies the variability in the electronic conduction. The derived model does not require empirical input parameters and only depends on the properties of the materials. This allows to use literature values and independently compare them to electrical measurements. The model predicts the experiments correctly. Thereupon, the physical properties of the conduction are investigated with respect to the transport over discrete energy levels, which change under the hopping of oxygen vacancies. Afterwards, the current level and variability are simulated for increasing oxygen vacancy concentrations to investigate analog switching, which is required for neuronal network layers. Finally, the variability is tested with multiple interacting cells in a neuronal layer.

Activation energy, bipolar resistance switching behavior, and the electrical conduction transport properties of ITOX:SiO2 thin film resistive random access memory (RRAM) devices were observed and discussed. The ITOX:SiO2 thin films were prepared using a co-sputtering deposition method on the TiN/Si substrate. For the RRAM device structure fabrication, an Al/ITOX:SiO2/TiN/Si structure was prepared by using aluminum for the top electrode and a TiN material for the bottom electrode. In addition, grain growth, defect reduction, and RRAM device performance of the ITOX:SiO2 thin film for the various oxygen gas flow conditions were observed and described. Based on the I-V curve measurements of the RRAM devices, the turn on-off ratio and the bipolar resistance switching properties of the Al/ITOX:SiO2/TiN/Si RRAM devices in the set and reset states were also obtained. At low operating voltages and high resistance values, the conductance mechanism exhibits hopping conduction mechanisms for set states. Moreover, at high operating voltages, the conductance mechanism behaves as an ohmic conduction current mechanism. Finally, the Al/ITOX:SiO2/TiN/Si RRAM devices demonstrated memory window properties, bipolar resistance switching behavior, and nonvolatile characteristics for next-generation nonvolatile memory applications. [ABSTRACT FROM AUTHOR]

Woven resistive random access memory (RRAM) is a promising subject in flexible wearable electronic devices. In this work, polyvinylammonium iodate (PVAm·HI) is added to the FAPbI3 perovskite precursor solution to fabricate a flexible fibrous woven RRAM array by improving the flexibility and stability of FAPbI3 perovskite. The long carbochain polymer backbone of PVAm serves as nucleation sites and a growth template to improve the perovskite crystallization process, and to in situ crosslink the perovskite grains at the crystal interface. The functional Al@FAPbI3:PVAm fibers are then prepared by solution dip-coating to assemble the fibrous crosspoint RRAM device with the structure of Al@FAPbI3:PVAm/Al by crossing bare aluminum (Al) fibers with functional fibers. Compared to a pristine device, the PVAm-modified devices exhibit a considerable improvement in the ON/OFF ratio and environmental stability. Specifically, the 2% PVAm-modified FAPbI3 RRAM devices show an evident bipolar resistive switching (RS) behavior with a high ON/OFF ratio of 109, which can easily achieve multilevel storage by setting the compliance current (Icc) to increase the storage density in the crosspoint array. Interestingly, a 100-times bent plastics-encapsulated device still exhibits a good RS behavior. This work provides a facile approach to achieve high-density storage in flexible wearable electronic devices. [ABSTRACT FROM AUTHOR]

Processing-in-memory (PIM) is a promising architecture to design various types of neural network accelerators as it ensures the efficiency of computation together with Resistive Random Access Memory (ReRAM). ReRAM has now become a promising solution to enhance computing efficiency due to its crossbar structure. In this paper, a ReRAM-based PIM neural network accelerator is addressed, and different kinds of methods and designs of various schemes are discussed. Various models and architectures implemented for a neural network accelerator are determined for research trends. Further, the limitations or challenges of ReRAM in a neural network are also addressed in this review. [ABSTRACT FROM AUTHOR]

Processing-In-Memory(PIM) has emerged as a high-performance and energy-efficient computing paradigm for accelerating convolutional neural network (CNN) applications. Resistive random access memory (ReRAM) has been widely used in PIM architectures due to its extremely high efficiency for accelerating matrix-vector multiplications through analog computing. However, because CNN training usually requires high-precision computation in the backward propagation (BP) stage, the limited precision of analog PIM accelerators impedes their adoption in CNN training. In this article, we propose ReHy, a hybrid PIM accelerator to support CNN training in ReRAM arrays. It is composed of Analog PIM (APIM) and Digital PIM (DPIM) modules. ReHy uses APIM to accelerate the feed-forward propagation (FP) stage for high performance, and DPIM to process the BP stage for high accuracy. We exploit the capability of ReRAM for Boolean logic operations to design the DPIM architecture. Particularly, we design floating-point multiplication and addition operators to support matrix multiplications in ReRAM arrays. We also propose a performance model to offload high-precision matrix multiplications to DPIM according to the data parallelism. Experimental results show that ReHy can speed up CNN training by 48.8× and 2.4×, and reduce energy consumption by 35.1× and 2.33×, compared with CPU/GPU architectures (baseline) and the state-of-the-art FloatPIM, respectively. [ABSTRACT FROM AUTHOR]

Activation energy, bipolar resistance switching behavior, and the electrical conduction transport properties of ITOX:SiO2 thin film resistive random access memory (RRAM) devices were observed and discussed. The ITOX:SiO2 thin films were prepared using a co-sputtering deposition method on the TiN/Si substrate. For the RRAM device structure fabrication, an Al/ITOX:SiO2/TiN/Si structure was prepared by using aluminum for the top electrode and a TiN material for the bottom electrode. In addition, grain growth, defect reduction, and RRAM device performance of the ITOX:SiO2 thin film for the various oxygen gas flow conditions were observed and described. Based on the I-V curve measurements of the RRAM devices, the turn on-off ratio and the bipolar resistance switching properties of the Al/ITOX:SiO2/TiN/Si RRAM devices in the set and reset states were also obtained. At low operating voltages and high resistance values, the conductance mechanism exhibits hopping conduction mechanisms for set states. Moreover, at high operating voltages, the conductance mechanism behaves as an ohmic conduction current mechanism. Finally, the Al/ITOX:SiO2/TiN/Si RRAM devices demonstrated memory window properties, bipolar resistance switching behavior, and nonvolatile characteristics for next-generation nonvolatile memory applications.

Artificial intelligence algorithms are being adopted to analyze medical data, promising faster interpretation to support doctors' diagnostics. The next frontier is to bring these powerful algorithms to implantable medical devices. Herein, a closed‐loop solution is proposed, where a cellular neural network is used to detect abnormal wavefronts and wavebrakes in cardiac signals recorded in human tissue is trained to achieve >96% accuracy, >92% precision, >99% specificity, and >93% sensitivity, when floating point precision weights are assumed. Unfortunately, the current hardware technologies for floating point precision are too bulky or energy intensive for compact standalone applications in medical implants. Emerging device technologies, such as memristors, can provide the compact and energy‐efficient hardware fabric to support these efforts and can be reliably embedded with existing sensor and actuator platforms in implantable devices. A distributed design that considers the hardware limitations in terms of overhead and limited bit precision is also discussed. The proposed distributed solution can be easily adapted to other medical technologies that require compact and efficient computing, like wearable devices and lab‐on‐chip platforms. [ABSTRACT FROM AUTHOR]

Reset-first resistive random access memory (RRAM) devices were demonstrated for off-stoichiometric Ni1−xO thin films deposited using reactive sputtering with a high oxygen partial pressure. The Ni1−xO based RRAM devices exhibited both unipolar and bipolar resistive switching characteristics without an electroforming step. Auger electron spectroscopy showed nickel deficiency in the Ni1−xO films, and X-ray photoemission spectroscopy showed that the Ni3+ valence state in the Ni1−xO films increased with increasing oxygen partial pressure. Conductive atomic force microscopy showed that the conductivity of the Ni1−xO films increased with increasing oxygen partial pressure during deposition, possibly contributing to the reset-first switching of the Ni1−xO films. [ABSTRACT FROM AUTHOR]

This article investigates the spatial tailoring of nitrogen vacancies by atomic layer annealing (ALA) on resistive random access memory (RRAM) devices with an AlN resistive switching layer. The ALA technique involves the in-situ layer-by-layer He/Ar plasma treatment in the cycle of atomic layer deposition for AlN. The AlN RRAM devices prepared with the ALA treatment near the TiN electrode have significantly superior uniformity of the operation voltages and the switching resistances, along with a lower cycle-to-cycle variation in endurance. This enhancement could be attributed to the relatively stable location of rupture and formation of conductive filaments, as a result of the film densification and the suppression of nitrogen vacancies in the AlN region treated with the ALA process. The AlN RRAM devices also demonstrate excellent retention of more than 106 seconds at 125°C. In addition, the ultra-thin 3.3 nm AlN switching layer contributes to low operation voltages of AlN RRAM. The outcomes manifest that the ALA technique could effectively improve the properties of nanoscale materials through precise spatial tailoring, with an accuracy up to atomic scale. [Display omitted] • ALA involves in-situ, layer-by-layer plasma treatment during AlN deposition by ALD. • ALA contributes to film densification and suppression of nitrogen vacancies in AlN. • The uniformity of AlN RRAM properties is improved by ALA near the TiN electrode. • Stable rupture and formation of conductive filaments due to ALA near TiN electrode. • Ultrathin (3.3 nm) AlN in RRAM exhibits low operation voltages and good retention. [ABSTRACT FROM AUTHOR]

Despite the great promises that the resistive random access memory (ReRAM) has shown as the next generation of non-volatile memory technology, its crossbar array structure leads to a severe sneak path interference to the signal read back from the memory cell. In this paper, we first propose a novel belief propagation (BP) based detector for the sneak path interference in ReRAM. Based on the conditions for a sneak path to occur and the dependence of the states of the memory cells that are involved in the sneak path, a Tanner graph for the ReRAM channel is constructed, inside which specific messages are updated iteratively to get a better estimation of the sneak path affected cells. We further combine the graph of the designed BP detector with that of the BP decoder of the polar codes to form a joint detector and decoder. Tailored for the joint detector and decoder over the ReRAM channel, effective polar codes are constructed using the genetic algorithm. Simulation results show that the BP detector can effectively detect the cells affected by the sneak path, and the proposed polar codes and the joint detector and decoder can significantly improve the error rate performance of ReRAM. [ABSTRACT FROM AUTHOR]

The physical unclonable function (PUF) is a promising low-cost hardware security primitive. Recent advances in nanotechnology have provided new opportunities for nanoscale PUF circuits. The resistive random access memory (RRAM) is extensively used in nanoscale circuits due to its low cost, non-volatility and easy integration with CMOS. This paper proposes a novel tristate hybrid PUF (TH-PUF) design based on a one-transistor-one-RRAM (1T1R) cell; this cell can be configured into two weak PUFs and a strong PUF using few control signals. To assess the proposed PUF design, a compact RRAM model at UMC 65 nm technology is employed. Simulation results show that the proposed TH-PUF achieves good uniqueness, reliability as well as a higher gate usability compared with an entire CMOS PUFs. The number of challenge response pairs (CRPs) of the proposed TH-PUF is larger than other RRAM-based PUFs. Moreover, the TH-PUF is more resistant to a modeling machine learning attack than traditional PUF designs.

Personalization of gait neuroprosthetics is paramount to ensure their efficacy for users, who experience severe limitations in mobility without an assistive device. Our goal is to develop assistive devices that collaborate with and are tailored to their users, while allowing them to use as much of their existing capabilities as possible. Currently, personalization of devices is challenging, and technological advances are required to achieve this goal. Therefore, this paper presents an overview of challenges and research directions regarding an interface with the peripheral nervous system, an interface with the central nervous system, and the requirements of interface computing architectures. The interface should be modular and adaptable, such that it can provide assistance where it is needed. Novel data processing technology should be developed to allow for real-time processing while accounting for signal variations in the human. Personalized biomechanical models and simulation techniques should be developed to predict assisted walking motions and interactions between the user and the device. Furthermore, the advantages of interfacing with both the brain and the spinal cord or the periphery should be further explored. Technological advances of interface computing architecture should focus on learning on the chip to achieve further personalization. Furthermore, energy consumption should be low to allow for longer use of the neuroprosthesis. In-memory processing combined with resistive random access memory is a promising technology for both. This paper discusses the aforementioned aspects to highlight new directions for future research in gait neuroprosthetics. [ABSTRACT FROM AUTHOR]

Fast and stable switching between states is one of the key factors for the success resistive random access memory (RRAM) development. In an array, wide reset efficiency variation in RRAM cells is found to link to the characteristics of its low frequency noise (LFN) in bit-cell current. Through Monte Carlo simulation on randomly placing conductive filaments (CF), LFN characteristics correspond to the densities of the CF in the RRAM film. Further correlations between LFN features and the reset efficiency are found. In addition, CF topography are found to change after long term cycling tests. A trimming process is proposed to minimize the impacts of stochastic CF generation, leading to increase reset speed.

Personalization of gait neuroprosthetics is paramount to ensure their efficacy for users, who experience severe limitations in mobility without an assistive device. Our goal is to develop assistive devices that collaborate with and are tailored to their users, while allowing them to use as much of their existing capabilities as possible. Currently, personalization of devices is challenging, and technological advances are required to achieve this goal. Therefore, this paper presents an overview of challenges and research directions regarding an interface with the peripheral nervous system, an interface with the central nervous system, and the requirements of interface computing architectures. The interface should be modular and adaptable, such that it can provide assistance where it is needed. Novel data processing technology should be developed to allow for real-time processing while accounting for signal variations in the human. Personalized biomechanical models and simulation techniques should be developed to predict assisted walking motions and interactions between the user and the device. Furthermore, the advantages of interfacing with both the brain and the spinal cord or the periphery should be further explored. Technological advances of interface computing architecture should focus on learning on the chip to achieve further personalization. Furthermore, energy consumption should be low to allow for longer use of the neuroprosthesis. In-memory processing combined with resistive random access memory is a promising technology for both. This paper discusses the aforementioned aspects to highlight new directions for future research in gait neuroprosthetics.

Resistive switching properties of nanoscale zirconium dioxide (ZrO2) thin film deposited by plasma-enhanced atomic layer deposition (PE-ALD) have been investigated. A resistive memory device has been formed with a 10-nm-thick ZrO2 film as an active switching layer sandwiched between an aluminum top electrode and a silver bottom electrode. Bipolar resistive switching characteristics were demonstrated by current–voltage measurements with a read memory window of 6.6 V, an ON/OFF current ratio of nearly 105 , and a retention time of 104 s. Current conduction at low resistance states follows Ohm's law while at a high-resistance state governed by space charge limited conduction. These indicate that the switching mechanism is attributed to filamentary conduction. A SPICE model was applied to model the device, with simulation measurement data in good agreement. This study proves the potential applications of PE-ALD ZrO2 for non-volatile resistive random access memories. [ABSTRACT FROM AUTHOR]

In this research, glucose was adopted as the switching layer of resistive random access memory (RRAM) for transient electronics. The fabricated glucose-based RRAM showed bipolar switching behavior with stable endurance (100 cycles) and retention (104 seconds) characteristics, without significant degradation, demonstrating its stable data storage capability and reliability. To investigate the switching mechanism of the glucose-based RRAM, various organic materials were prepared for the switching layer of RRAM. In addition, the dissolution characteristic of the glucose-based RRAM was evaluated to investigate the feasibility of its utilization for transient electronics, using a water-soluble substrate: a sodium carboxymethyl cellulose film. With this approach, a biocompatible glucose-based RRAM was successfully fabricated for future transient electronics.

Reset-first resistive random access memory (RRAM) devices were demonstrated for off-stoichiometric Ni1−xO thin films deposited using reactive sputtering with a high oxygen partial pressure. The Ni1−xO based RRAM devices exhibited both unipolar and bipolar resistive switching characteristics without an electroforming step. Auger electron spectroscopy showed nickel deficiency in the Ni1−xO films, and X-ray photoemission spectroscopy showed that the Ni3+ valence state in the Ni1−xO films increased with increasing oxygen partial pressure. Conductive atomic force microscopy showed that the conductivity of the Ni1−xO films increased with increasing oxygen partial pressure during deposition, possibly contributing to the reset-first switching of the Ni1−xO films.

We report an ReRAM-based pseudo-true random number generator (RNG) which can significantly improve the security feature of e-ReRAM chips at a very low cost. Combining the true randomness from stochastic behavior of ReRAM and the high output speed from a modified linear feedback shift register (LFSR), the proposed architecture can provide ultrahigh throughput random sequence following system clocks from several Mbit/sec to tens of Gbit/sec. The highly reliable, unpredictable, and unrepeatable ReRAM-based pseudo-true RNG circuit can pass NIST SP800-22 randomness tests at a high score. It is suitable for secure IoT and 5G applications. [ABSTRACT FROM AUTHOR]

Herein, we characterize resistive random access memory (RRAM) devices containing an oxygen-deficient layer. The RRAM devices consist of multiple layered NiO thin films that consist of an oxygen-deficient NiO 0.95 layer, within a NiO/NiO 0.95 /NiO layer structure. The NiO thin-film layers were deposited on Pt/Ta/SiO 2 /Si substrates by radio frequency magnetron sputtering. The stoichiometry and thickness of the NiO triple-layer thin films were determined by Auger electron spectroscopy. We fabricated RRAM capacitors with a structure of Pt/NiO/NiO 0.95 /NiO/Pt to investigate the resistive switching characteristics. The presence of an oxygen-deficient layer significantly lowers the forming and SET/RESET voltages compared to a Pt/NiO/Pt RRAM capacitor. This reduces the energy required to form conducting filaments in the oxygen-deficient layer. Moreover, the forming and SET/RESET voltages exhibit reduced dispersion due to the relatively high oxygen vacancy density in the oxygen-deficient NiO 0.95 layer. [ABSTRACT FROM AUTHOR]

The ever‐increasing processing power demands of digital computers cannot continue to be fulfilled indefinitely unless there is a paradigm shift in computing. Neuromorphic computing, which takes inspiration from the highly parallel, low‐power, high‐speed, and noise‐tolerant computing capabilities of the brain, may provide such a shift. Many researchers from across academia and industry have been studying materials, devices, circuits, and systems, to implement some of the functions of networks of neurons and synapses to develop neuromorphic computing platforms. These platforms are being designed using various hardware technologies, including the well‐established complementary metal‐oxide semiconductor (CMOS), and emerging memristive technologies such as SiOx‐based memristors. Herein, recent progress in CMOS, SiOx‐based memristive, and mixed CMOS‐memristive hardware for neuromorphic systems is highlighted. New and published results from various devices are provided that are developed to replicate selected functions of neurons, synapses, and simple spiking networks. It is shown that the CMOS and memristive devices are assembled in different neuromorphic learning platforms to perform simple cognitive tasks such as classification of spike rate‐based patterns or handwritten digits. Herein, it is envisioned that what is demonstrated is useful to the unconventional computing research community by providing insights into advances in neuromorphic hardware technologies.

Abstract By introducing a capacitor in series (CST), a self‐terminated (ST) operation scheme is proposed to achieve high‐parallel forming of resistive random access memory (RRAM) array with reduced time and energy consumption. Once the RRAM cell is switched to the low‐resistance state, the current is automatically cut off by the capacitor, which can significantly improve the parallelism and energy efficiency. The wire capacitance of interconnect (Cwire) can be utilized as CST, which means there is no addition circuit or process expense for the proposed ST scheme. After successful experimental verification of the proposed ST operation scheme in 1 kb RRAM array, the performance of 1 Gb RRAM memory is evaluated, which shows × 103 improvement in forming time (from 0.6 h to 0.84 s) and × 104 improvement in energy consumption. Moreover, by experimentally leveraging the operation scheme for array forming, the operation current is reduced in subsequent switching process without deteriorating the device reliability, which demonstrates the feasibility of the proposed ST operation scheme and its potential in low power applications.

Based on the electrical conductivity model built for graphene oxide, the thermal crosstalk effects of resistive random access memory (RRAM) with graphene electrode and Pt electrode are simulated and compared. The thermal crosstalk effects of Pt-RRAM with different metal oxides of TiOx, NiOx, HfOx, and ZrOx are further simulated and compared to guide its compatibility design. In the Pt-RRAM array, the distributions of oxygen vacancy density and temperature are obtained, and the minimum spacing between adjacent conduction filaments to avoid device operation failure is discussed. The abovementioned four metal oxides have different physical parameters such as diffusivity, electrical conductivity, and thermal conductivity, from which the characters of the RRAMs based on one of the oxides are analyzed. Numerical results reveal that thermal crosstalk effects are severe as the spacing between adjacent conduction filaments is small, even leading to the change of logic state and device failure.

We fabricated organic resistive random-access memory (RRAM) devices using a low-cost solution-process method. All the processes were performed at temperatures below 135 °C under ambient atmospheric conditions. The RRAM resistive switching layer was formed from a polymer-fullerene bulk heterojunction using poly(3-hexylthiophene-2,5-diyl) (P3HT) and (6,6)-phenyl C61 butyric acid methyl ester (PCBM). The fabricated organic RRAM device exhibited typical nonvolatile bipolar resistive switching behavior with an ON/OFF ratio of ∼40, but it provided a low endurance of 27 cycles. Therefore, for enhanced stability, simple UV–Ozone (UVO) treatment was applied to the P3HT:PCBM organic bulk heterojunction layer. The organic RRAM device with UVO treatment exhibited an enhanced performance with an ON/OFF ratio of ∼400 and an endurance of 47 cycles. In addition, complementary resistive switching behavior was observed. The conduction mechanisms of the organic RRAM device were investigated by fitting the measured I–V data to numerical equations, and Schottky emission and Ohmic conduction were the main conduction mechanisms for the high-resistance and low-resistance states for the RRAM device with or without UVO treatment.

To improve a pattern recognition accuracy of synaptic device-based neuromorphic system, we tried to obtain symmetric conductance changes between conductance increase process (potentiation) and conductance decrease process (depression). By utilizing compensational voltage division, we achieved more gradual conductance changes during the depression, which led to the symmetric conductance changes between the potentiation and depression. On the basis of the achieved symmetric conductance changes, obviously improved pattern recognition accuracy was obtained on a multilayer perceptron structural simulation.

Programmable metallization cell is one of important threshold switching selectors. We first performed a study on the selector based on amorphous chalcogenide material (Si0.4Te0.6) because of the rigid structure applied in ovonic threshold switch. In the meantime, annealing process is implemented to improve the performance. Results show that devices without annealing process demonstrate a minor threshold switching characteristic, revealing the potential as selector for cross-point memristor array. After implementing annealing process, threshold voltage (Vth), selectivity and endurance of selectors improve. Meanwhile, requirements of high current and a low holding voltage (Vh) for an ideal selector are fulfilled. Using the Ag filament formed during motion of Ag ions, a steep-slope (1.7 mV/dec) for threshold switching with high selectivity (~104) could be achieved. Owing to the faster diffusivity of Ag atoms in solid-electrolytes, the resulting Ag filament easily dissolved under low current regime. It is deduced that performance improvement is due to the defect reduction within annealing process. Finally, time characteristics of selector devices are tested to verify fast switching and recovery speed for practical applicability.

Photograph response in transparent devices has been a hot area of investigation, with several material systems being used to generate a response to illumination. In this study, we propose an ITO/MgO/HfO2/ITO bilayer (BL) transparent resistive switching (RS) device that exhibits a photograph response through defect engineering in the switching layer, which resulted in a subsurface active RS location in the formed conductive filament, thus reducing the loss of oxygen through the polycrystalline electrode. We observe that the switching performance is enhanced in the ITO/MgO/HfO2/ITO BL device as compared to the ITO/HfO2/ITO single-layer device with the insertion of MgO layer between the ITO top electrode and HfO2 RS layer. The device shows excellent ON/ OFF ratio (~107), high and stable dc electrical set and optical reset endurance (>1000 cycles without degradation), excellent retention (>104 s at 85 °C), high transparency (>85% transmittance in the visible spectrum), and a response time of 30 μs for the optical reset. This study lays the foundation for future work involving oxide defect-based optical functionalization in RS devices with the possibility for being used in photograph sensing. [ABSTRACT FROM AUTHOR]

The ever‐increasing processing power demands of digital computers cannot continue to be fulfilled indefinitely unless there is a paradigm shift in computing. Neuromorphic computing, which takes inspiration from the highly parallel, low‐power, high‐speed, and noise‐tolerant computing capabilities of the brain, may provide such a shift. Many researchers from across academia and industry have been studying materials, devices, circuits, and systems, to implement some of the functions of networks of neurons and synapses to develop neuromorphic computing platforms. These platforms are being designed using various hardware technologies, including the well‐established complementary metal‐oxide semiconductor (CMOS), and emerging memristive technologies such as SiOx‐based memristors. Herein, recent progress in CMOS, SiOx‐based memristive, and mixed CMOS‐memristive hardware for neuromorphic systems is highlighted. New and published results from various devices are provided that are developed to replicate selected functions of neurons, synapses, and simple spiking networks. It is shown that the CMOS and memristive devices are assembled in different neuromorphic learning platforms to perform simple cognitive tasks such as classification of spike rate‐based patterns or handwritten digits. Herein, it is envisioned that what is demonstrated is useful to the unconventional computing research community by providing insights into advances in neuromorphic hardware technologies. [ABSTRACT FROM AUTHOR]

In this article, the development history and the technical hurdles of phase-change memory (PCM) are reviewed and recent progress and future directions are discussed. Prospects of PCM for storage-class memory (SCM) are discussed in terms of the technical challenges to satisfy the market requirements, mainly for the performance and cost effectiveness. For a more in-depth discussion, PCM is segmented into the memory part, the access device part, and the sensing scheme part. In the memory part, Set (crystallization)–Reset (amorphization) write characteristics and thermal disturbance (TDB) will be reinterpreted in terms of power consumption and performance of SCM. In the access device part, the application history of various devices, such as the transistor, the diode, and the two-terminal selector, will be reviewed and explained based on the process integration issues and area efficiency. In the next part, various sensing schemes used to make a lower read latency, multilevel cell (MLC), and cross point (X-point) are summarized. Thereafter, future directions and possible evolution pathways of 3-D structures, including X-point and vertical X-point (VXP), will be discussed for the first time. Finally, the feasibility of PCM for neuromorphic application will be followed. [ABSTRACT FROM AUTHOR]

In this research, glucose was adopted as the switching layer of resistive random access memory (RRAM) for transient electronics. The fabricated glucose-based RRAM showed bipolar switching behavior with stable endurance (100 cycles) and retention (104 seconds) characteristics, without significant degradation, demonstrating its stable data storage capability and reliability. To investigate the switching mechanism of the glucose-based RRAM, various organic materials were prepared for the switching layer of RRAM. In addition, the dissolution characteristic of the glucose-based RRAM was evaluated to investigate the feasibility of its utilization for transient electronics, using a water-soluble substrate: a sodium carboxymethyl cellulose film. With this approach, a biocompatible glucose-based RRAM was successfully fabricated for future transient electronics. [ABSTRACT FROM AUTHOR]

Abstract The HfO2/TiO2/HfO2 trilayer-structure resistive random access memory (RRAM) devices have been fabricated on Pt- and TiN-coated Si substrates with Pt top electrodes by atomic layer deposition (ALD). The effect of the bottom electrodes of Pt and TiN on the resistive switching properties of trilayer-structure units has been investigated. Both Pt/HfO2/TiO2/HfO2/Pt and Pt/HfO2/TiO2/HfO2/TiN exhibit typical bipolar resistive switching behavior. The dominant conduction mechanisms in low and high resistance states (LRS and HRS) of both memory cells are Ohmic behavior and space-charge-limited current, respectively. It is found that the bottom electrodes of Pt and TiN have great influence on the electroforming polarity preference, ratio of high and low resistance, and dispersion of the operating voltages of trilayer-structure memory cells. Compared to using symmetric Pt top/bottom electrodes, the RRAM cells using asymmetric Pt top/TiN bottom electrodes show smaller negative forming voltage of −3.7 V, relatively narrow distribution of the set/reset voltages and lower ratio of high and low resistances of 102. The electrode-dependent electroforming polarity can be interpreted by considering electrodes’ chemical activity with oxygen, the related reactions at anode, and the nonuniform distribution of oxygen vacancy concentration in trilayer-structure of HfO2/TiO2/HfO2 on Pt- and TiN-coated Si. Moreover, for Pt/HfO2/TiO2/HfO2/TiN devices, the TiN electrode as oxygen reservoir plays an important role in reducing forming voltage and improving uniformity of resistive switching parameters.

Abstract This paper reports a novel full logic compatible 4T2R non-volatile static random access memory (nv-SRAM) featuring its self-inhibit data storing mechanism for in low-power/high-speed SRAM application. With compact cell area and full logic compatibility, this new nv-SRAM incorporates two STI-ReRAMs embedded inside the 4T SRAM. Data can be read/write through a cross-couple volatile structure for maintaining fast accessing speed. Data can be non-volatilely stored in new SRAM cell through a unique self-inhibit operation onto the resistive random access memory (RRAM) load, achieving zero static power during data hold.

Abstract A controllable transformation from interfacial to filamentary switching mode is presented on a ZrO2/ZrO2 − x /ZrO2 tri-layer resistive memory. The two switching modes are investigated with possible switching and transformation mechanisms proposed. Resistivity modulation of the ZrO2 − x layer is proposed to be responsible for the switching in the interfacial switching mode through injecting/retracting of oxygen ions. The switching is compliance-free due to the intrinsic series resistor by the filaments formed in the ZrO2 layers. By tuning the RESET voltages, controllable and stable multistate memory can be achieved which clearly points towards the capability of developing the next-generation multistate high-performance memory.

Abstract Resistive switching devices based on oxides have outstanding properties, making them a promising candidate to replace today's transistor‐based computer memories as non‐volatile valence change memories, and can even find future application in neuromorphic computing. To date, the scientific discussion is so far mainly restricted to oxygen vacancy contributions disregarding the role of protonic defects on resistive switching. In this work, the effect of moisture and protonic contributions on resistive switching by changes in the surface to bulk ratio and oxide surface exposure of the oxide SrTiO3 is studied. Here, a linear to exponential SET current density dependency, when changing the film thickness by a factor of four, is found, whereby the surface‐to‐bulk ratio of the oxide is significantly changed. This behavior is discussed in terms of differences in total concentration of oxygen vacancies and their interplay with moisture. For classic memristor applications, this study demonstrates that protonic defects need to be accounted for memristor characteristics, as they crucially influence the switching characteristics, and give new opportunities as an additional handle to actively tune the switching performance. This memristive dependency on protonic defects opens a whole plethora of new modulatable sensor characteristics like creating humidity sensors using the property of memristance.