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Compounds 2-5, incorporating various elements of the 3,4′- bis(piperidine) core associated with the sponge-derived alkaloid haliclonacyclamine A (HA, 1), have been prepared through, inter alia, aldol-type reactions of N-substituted piperidin-4-ones and

A series of enantiomerically pure C8cC15 monoseco analogues, 2330, of the alkaloids cryptopleurine (1) and julandine (2) have been prepared using cinnamyl chloride 37 and (S)- or (R)-2-methylpiperidine as key building blocks. Two related compounds, 31 and 32, have also been synthesized. Each of these analogues has been subjected to various biological evaluations and most of them show dramatically reduced cytotoxicity compared with parent system 1. Nevertheless, they are potent anti-angiogenic agents. The formation and single-crystal X-ray analysis of the spirocyclic dienone 54, a by-product arising from attempts to prepare analogue 32, is also described.

Four enantiomerically pure monoseco-analogues, 5, 7, 9, and 11, of the phenanthroquinolizidine alkaloid julandine (1) and four of congener cryptopleurine (2), viz. compounds 6, 8, 10, and 12, have been prepared and subjected to preliminary biological evaluation. These analogues show dramatically reduced cytotoxicity compared with the parent system 2 but they are, nevertheless, potent anti-angiogenic agents.

Tuberose (Polianthes tuberosa L. cv. Double) corms at the vegetative, early floral initiation, and flower bud differentiation stages were assayed for free indole-3-acetic acid (IAA), esterified IAA, and peptidyl IAA. The corms in the vegetative stage contained higher free IAA than those from the early floral initiation stage. Free IAA in corm tissues increased 2.7-fold at flower bud differentiation as compared to the vegetative stage. In the vegetative corms, a marked promotion of leaf differentiation was recorded. In contrast, corms from the early floral initiation stage contained less free IAA, whereas esterified IAA and peptidyl IAA increased dramatically. It is concluded that the level of free IAA in vegetative corms is correlated with leaf differentiation, and that the early floral initiation stage is correlated with a reduction in free IAA and an increase in IAA conjugates in the corms. Moreover, increases in free IAA and decreases in IAA conjugates in the floral differentiation stage, as compared to the early floral initiation stage, indicates that free IAA is correlated with flower development.

Due to the advances in the integrated circuit (IC) technology, more and more components are being fabricated into a tiny IC chip. Since the number of pins on each chip is limited by the physical size of the chip, the problem of testing becomes more difficult than ever, especially in the VLSI (Very Large Scale Integration) chips. This problem is aggravated by the fact that, in nearly all cases, integrated circuit manufacturers are not willing to release the detailed circuit diagram of the IC chip to the users. Yet, as users of the IC chips, to make sure that the implemented system is reliable, we need to test the IC chips and the systems made of the interconnection of these chips. The purpose of this project is to find efficient algorithms for testing LSI/VLSI chips and LSI/VLSI-based systems. This report is organized into two chapters. Chapter 1 presents the state-of-the-art for the functional testing of LSI/VLSI devices with special emphasis on microprocessor testing. Chapter 2 reports our new research results. We present three algorithms to test the instruction decoding function of microprocessors.

Due to the advances in the integrated circuit (IC) technology, more and more components are being fabricated into a tiny IC chip. Since the number of pins on each chip is limited by the physical size of the chip, the problem of testing becomes more difficult than ever, especially in the VLSI(Very Large Scale Integration) chips. This problem is aggravated by the fact that, in nearly all cases, integrated circuit manufacturers are not willing to release the detailed circuit diagram of the IC chip to the users. Yet, as users of the IC chips, to make sure that the implemented system is reliable, we need to test the IC chips and the systems made of the interconnection of these chips. The purpose of this project is to find efficient algorithms for testing LSI/VLSI chips and LSI/VSLI-based systems. As a result of the rapidly increasing complexity of modern digital LSI/VLSI systems, functional testing is attracting more attention than ever not only in the computer manufacturing industry but also in the diversified potential applications. Functional testing uses a representation of a digital system higher than the gate-level testing. In functional testing, functional faults with respect to the functional specification (e.g., addition operation in a processor) are tested instead of a signal faults (e.g., a line stuck-at logical 0) in the circuit representation. The purpose of functional testing is to validate correct functional operations of digital systems according to their specifications.

This paper presents three algorithms to test the instruction decoding function of microprocessors. The algorithms are based on the knowledge of some timing and control information available to users through microprocessor manuals and data sheets. The tests are functional in nature. The authors establish the order of complexity of the algorithms presented in this paper. As an example, the test complexity for a microprocessor is computed and the results are compared with a known algorithm.

Functional testing is a feasible solution for LSI/VLSI test generation and design verification. In this paper, we present a systematic way to perform functional testing using an advanced symbolic execution technique. Symbolic execution is a very useful and powerful software engineering technique mainly used in program analysis including test generation. Often a single symbolic execution of a program may represent a large number of normal test runs.

This paper presents a number of algorithms to test the instruction decoding function of microprocessors based on some timing and control information available to users. Keywords: Register Transfer Language; Digital Networks.