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A quantum-dot cellular automata(QCA) latch is an elementary building block, which can be used to build shift registers and logic devices for clocked QCA architectures. The operation of a QCA latch and a shift register, are discussed, and the analysis and presentation of the types and properties of errors encountered in their operation are presented.

Recent work on fabricating metal-insulator-metal (MIM) single electron transistors (SETs) using deposited dielectrics shows promise for becoming a manufacturable process due to compatibility with modern CMOS processes. This process, the "rib-SET" process [V. Joshi, A. O. Orlov, and G. L. Snider, J. Vac. Sci. Technol. B 26, 2587 (2008); G. Karbasian, A. O. Orlov, and G. L. Snider, J. Vac. Sci. Technol. B 33 (2015)], features a self-aligned island and should allow for scaling SETs below 10 nm. However, one of the biggest roadblocks in realizing a high-quality SET with this process has been difficulties in developing high-quality, low-noise, MIM tunnel junctions. In this work, the authors report Pt-SiO2-Pt MIM SETs with tunnel barriers deposited by e-beam evaporation as an alternative to atomic layer deposition. There are some challenges in the formation of tunnel barriers via e-beam evaporation that are addressed. It is expected that platinum has a negligible native oxide; however, there is a substantial resistance in as-deposited Pt-SiO2-Pt structures that can be reduced by over 5 orders of magnitude by subjecting the finished devices to an anneal in a hydrogen plasma, suggesting the presence of an interfacial platinum oxide. It is shown that this treatment not only increases the conductance through the SET, but that it is necessary for forming high conductance tunnel barriers that are desired for making low-noise SETs. [ABSTRACT FROM AUTHOR]

Single electron transistors are nanoscale electron devices that require thin, high-quality tunnel barriers to operate and have potential applications in sensing, metrology and beyond-CMOS computing schemes. Given that atomic layer deposition is used to form CMOS gate stacks with low trap densities and excellent thickness control, it is well-suited as a technique to form a variety of tunnel barriers. This work is a review of our recent research on atomic layer deposition and post-fabrication treatments to fabricate metallic single electron transistors with a variety of metals and dielectrics. [ABSTRACT FROM AUTHOR]

This work describes the fabrication of single electron transistors using electron beam lithography and atomic layer deposition to form nanoscale tunnel transparent junctions of alumina (Al2O3) on platinum nanowires using either water or ozone as the oxygen precursor and trimethylaluminum as the aluminum precursor. Using room temperature, low frequency conductance measurements between the source and drain, it was found that devices fabricated using water had higher conductance than devices fabricated with ozone. Subsequent annealing caused both water- and ozone-based devices to increase in conductance by more than 2 orders of magnitude. Furthermore, comparison of devices at low temperatures (~4K) showed that annealed devices displayed much closer to the ideal behavior (i.e., constant differential conductance) outside of the Coulomb blockade region and that untreated devices showed nonlinear behavior outside of the Coulomb blockade region (i.e., an increase in differential conductance with source-drain voltage bias). Transmission electron microscopy cross-sectional images showed that annealing did not significantly change device geometry, but energy dispersive x-ray spectroscopy showed an unusually large amount of oxygen in the bottom platinum layer. This suggests that the atomic layer deposition process results in the formation of a thin platinumsurface oxide, which either decomposes or is reduced during the anneal step, resulting in a tunnel barrier without the in-series native oxide contribution. Furthermore, the difference between ozone- and water-based devices suggests that ozone promotes atomic layer depositionnucleation by oxidizing the surface but that water relies on physisorption of the precursors. To test this theory, devices were exposed to forming gas at room temperature, which also reduces platinum oxide, and a decrease in resistance was observed, as expected. [ABSTRACT FROM AUTHOR]

The authors report the use of plasma-enhanced atomic layer deposition (PEALD) to fabricate single-electron transistors (SETs) featuring ultrathin (≈1 nm) tunnel-transparent SiO2 in Ni-SiO2- Ni tunnel junctions. They show that, as a result of the O2 plasma steps in PEALD of SiO2, the top surface of the underlying Ni electrode is oxidized. Additionally, the bottom surface of the upper Ni layer is also oxidized where it is in contact with the deposited SiO2, most likely as a result of oxygen-containing species on the surface of the SiO2. Due to the presence of these surface parasitic layers of NiO, which exhibit features typical of thermally activated transport, the resistance of Ni- SiO2-Ni tunnel junctions is drastically increased. Moreover, the transport mechanism is changed from quantum tunneling through the dielectric barrier to one consistent with thermally activated resistors in series with tunnel junctions. The reduction of NiO to Ni is therefore required to restore the metal-insulator-metal (MIM) structure of the junctions. Rapid thermal annealing in a forming gas ambient at elevated temperatures is presented as a technique to reduce both parasitic oxide layers. This method is of great interest for devices that rely on MIM tunnel junctions with ultrathin barriers. Using this technique, the authors successfully fabricated MIM SETs with minimal trace of parasitic NiO component. They demonstrate that the properties of the tunnel barrier in nanoscale tunnel junctions (with <10-15 m2 in area) can be evaluated by electrical characterization of SETs. [ABSTRACT FROM AUTHOR]