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Titanium-based contacts are envisioned for the integration of III–V device contacts on a 300-mm platform, such as photodetectors, semiconductor optical amplifiers (SOAs), and III–V silicon hybrid lasers. For the first time, the impact of the thermal budgets of process integration, back-end of line (BEOL), and long-term thermal stress on the electrical characteristics of the Ti/p-In0.53Ga0.47As and Ti/n-InP contacts has been investigated. Additional physical characterizations have been used to supplement the electrical properties on both systems. Results have indicated that, given a thermal budget between 350 °C and 450 °C during 60 s right after metal deposition, 1) Ti as a contact metal has led to contact resistivity in low $10^{-{5}}\,\,\Omega \cdot \text {cm}^{{2}}$ for p-contacts and in mid $10^{-{5}}\,\,\Omega \cdot \text {cm}^{{2}}$ for n-contacts, which is in accordance with the device requirements; and 2) process integration, BEOL, and long-term thermal stress will not induce any change of the electrical properties. In the scope of III–V silicon hybrid laser contact integration, Ti has hence been evidenced as a suitable candidate for both p- and n-contacts.

Thin films of superconducting V$_3$Si were prepared by means of RF sputtering from a compound V$_3$Si target at room temperature onto sapphire and oxide-coated silicon wafers, followed by rapid thermal processing under secondary vacuum. The superconducting properties of the films thus produced are found to improve with annealing temperature, which is ascribed to a reduction of defects in the polycrystalline layer. Critical temperatures ($T_\text{c}$) up to $15.3\,$K were demonstrated after thermal processing, compared to less than $1\,$K after deposition. The $T_\text{c}$ was found to always be lower on the silicon wafers, by on average $1.9(3)\,$K for the annealed samples. This difference, as well as a broadening of the superconducting transitions, is nearly independent of the annealing conditions. In-situ XRD measurements reveal that the silicide layer becomes strained upon heating due to a mismatch between the thermal expansion of the substrate and that of V$_3$Si. Taking into account the volume reduction due to crystallization, this mismatch is initially larger on sapphire, though stress relaxation allows the silicide layer to be in a relatively unstrained state after cooling. On oxidized silicon however, no clear evidence of relaxation upon cooling is observed, and the V$_3$Si ends up with an out-of-plane strain of 0.3\% at room temperature. This strain increases as the sample is cooled down to cryogenic temperatures, though the deformation of the polycrystalline layer is expected to be highly inhomogeneous. Taking into account also the reported occurrence of a Martensitic transition just above the critical temperature, this extrapolated strain distribution is found to closely match an existing model of the strain dependence of A-15 superconducting compounds., 7 pages, 5 figures

The development of Complementary Metal Oxide Semiconductor (CMOS)-compatible contact technology on III–V materials based on Ti for electronics or photonics applications was studied. In this framework, solid-state reactions between Ti thin films (20 nm) and In0.53Ga0.47As layers grown on InP substrates were studied from the as-deposited state up to 550 °C using a combination of advanced X-ray diffraction (in-plane reciprocal space mapping), Auger electron spectroscopy and transmission electron microscopy analyses. The phase formation sequence was solved. At low temperature, an amorphous Ti–Ga–As intermixing layer coexists with the Ti film. As of 250 °C, the first crystalline phase to form is Ti 2 Ga 3 . At 300 °C, a new crystalline phase appears, namely TiAs 2 . On the other hand, TiAs and metallic In form at 350 °C and Ti is completely consumed between 450 and 500 °C. The diffusion of the various species lead to the formation of a non-nominal Ga-rich In x Ga 1−x As layer and at 550 °C to the formation of polycrystalline GaAs. Ti was found to be the main diffusing species at low temperature whereas III and V elements are the dominant diffusing species at higher temperatures. The nature of the phases formed above and below the original Ti/InGaAs interface might explain the In accumulation at the interface, the TiAs phase acting as a diffusion barrier.

International audience; Using a metal-organic tungsten based precursor, a fluorine-free tungsten thin film has been obtained. The process deposition recipe includes a plasma-enhanced CVD (PECVD) step and atomic layer deposition (ALD) cycles. A set of physicochemical characterizations including X-ray reflectivity (XRR), in-plane X-ray diffraction (XRD), wavelength dispersive X-ray fluorescence (WDXRF), plasma profiling time of flight mass spectrometry (PPTOFMS) and microscope observations has been realized in order to study the W thin film structure and properties. The film is perfectly conformal whatever the structure size investigated (from tens of nanometers to micrometers wide). It was also highlighted that the F-free W film exhibits the lowest electrical resistivity phase (α-W) but is not pure. Indeed, in addition to a top surface oxidation, a layer located at the W film / substrate interface is present. This interface layer (IL) contains impurities, including carbon and oxygen, due to ligand decomposition. This IL might be deposited during the soak step or during the PECVD step. The W liner with thicknesses ranging from 3 to 4 nm has been implemented on PCRAM structures in order to evaluate its impact on contact plug resistivity. First electrical results are promising and demonstrate the interest of using a F-free low resistance W liner. At the aspect ratio studied, the gain in terms of contact plug resistivity is about 20% compared to the process of reference using a TiN liner. Modeling shows that this benefit is mainly due to the reduction of interface resistances.

In the context of the development of silicon photonics, various Ti- and Ni-based alloyed metallizations have been investigated for the purpose of forming low resistivity and Si CMOS-compatible contacts to n-InP. The innovative Ni2P metallization combined with an in situ Ar+ preclean represents the most suitable available solution for the formation of ohmic contacts with a specific contact resistivity as low as $4.3 \times 10^{-6}~\Omega ^{2}$ on such a semiconductor. The latter additionally presents the advantage of being stable at least up to 350 °C and could therefore withstand additional integration processes conducted at this temperature.

Silicon photonics has generated an amazing interest for many years to address the challenges of numerous applications including optical communications, sensing, and quantum information to name few. A review of the main building blocks to emit, guide, modulate, and detect light on silicon chip is described and a special focus is given on the large possibilities offered by the hybrid integration on silicon photonics platform for the development of reliable and efficient on-chip functionalities.

Phosphorus diffusion and its distribution during the solid-state reactions between Ni0.9Pt0.1 and implanted Si substrates are studied. Silicidation is achieved through a first rapid thermal annealing followed by a selective etching and a direct surface annealing. The redistribution of phosphorus in silicide layers is investigated after the first annealing for different temperatures and after the second annealing. Phosphorus concentration profiles obtained thanks to time of flight secondary ion mass spectrometry and atom probe tomography characterizations for partial and total reactions of the deposited 7 nm thick Ni0.9Pt0.1 film are presented. Phosphorus segregation is observed at the Ni0.9Pt0.1 surface and at Ni2Si interfaces during Ni2Si formation and at the NiSi surface and the NiSi/Si interface after NiSi formation. The phosphorus is evidenced in low concentrations in the Ni2Si and NiSi layers. Once NiSi is formed, a bump in the phosphorus concentration is highlighted in the NiSi layer before the NiSi/Si interface. Based on these profiles, a model for the phosphorus redistribution is proposed to match this bump to the former Ni2Si/Si interface. It also aims to bind the phosphorus segregation and its low concentration in different silicides to a low solubility of phosphorus in Ni2Si and in NiSi and a fast diffusion of phosphorus at their grain boundaries. This model is also substantiated by a simulation using a finite difference method in one dimension.

International audience; The metallurgical properties of the Ti/InP system meet a great interest for its use as a contact in the scope of various applications such as the Si Photonics. The investigations conducted on this system highlight the initiation of a reaction between the Ti and the InP substrate during the deposition process conducted at 100 °C. The simultaneous formation of two binary phases, namely, Ti$_2$In$_5$ and TiP, is attributed to the compositional gradient induced in the InP by the wet surface preparation and enhanced by the subsequent $in situ$ Ar$^+$ preclean. Once formed, the TiP layer acts as a diffusion barrier inhibiting further reaction up to 450 °C in spite of the presence of an important Ti reservoir. At higher temperature, however, i.e., from 550 °C, the reaction is enabled either by the enhancement of the species diffusion through the TiP layer or by its agglomeration. This reaction gives rise to the total consumption of the Ti$_2$In$_5$ and Ti while the TiP and In phases are promoted.

The integration of III-V/Si hybrid lasers on a 300 mm platform for photonic applications requires the development of dedicated CMOS-compatible contacts, for which nickel-based ones are very good candidates. In this scope, this work presents and compares the impact of in situ preclean based on argon (Ar) or helium (He) plasma on the surface integrity of InP prior to the nickel (Ni) contact deposition. The resulting surface morphology, element distribution, phase formation sequence of the Ni/InP system, and electrical behavior of Ni/n-InP contacts are detailed using morphological, structural, and electrical characterizations. The results show that Ar preclean significantly damages the InP surface by generating high roughness and creating indium (In) dots on the top surface, while He preclean seems to induce lighter damages and no In dots. Although the phase sequence of the Ni/InP system is overall the same for each preclean, the electrical behavior differs depending on the nature of the preclean. On one hand, Ni/n-InP Ar-precleaned contacts exhibit nonohmic behavior for each investigated thermal budget. On the other hand, He-precleaned contacts features ohmic behavior for the as-deposited state and thermal anneals up to 350 ° C for 60 s. They, however, become nonohmic after anneals of 400 and 450 ° C for 60 s. These results, hence, suggest that the difference of electrical behavior obtained between Ar and He-precleaned Ni/n-InP contacts is due to differences in the state surface and morphology.The integration of III-V/Si hybrid lasers on a 300 mm platform for photonic applications requires the development of dedicated CMOS-compatible contacts, for which nickel-based ones are very good candidates. In this scope, this work presents and compares the impact of in situ preclean based on argon (Ar) or helium (He) plasma on the surface integrity of InP prior to the nickel (Ni) contact deposition. The resulting surface morphology, element distribution, phase formation sequence of the Ni/InP system, and electrical behavior of Ni/n-InP contacts are detailed using morphological, structural, and electrical characterizations. The results show that Ar preclean significantly damages the InP surface by generating high roughness and creating indium (In) dots on the top surface, while He preclean seems to induce lighter damages and no In dots. Although the phase sequence of the Ni/InP system is overall the same for each preclean, the electrical behavior differs depending on the nature of the preclean. On one han...

International audience; The solid-state reaction between Ni and In In$_{0.53}$Ga$_{0.47}$As on an InP substrate was studied by X-ray diffraction (XRD) and scanning transmission electron microscopy-energy-dispersive X-ray spec-troscopy techniques. Due to the monocrystalline structural aspect of the so-formed intermetallic, it was necessary to measure by XRD a full 3D reciprocal space mapping in order to have a complete overlook over the crystalline structure and texture of the intermetallic. The formation of the inter-metallic was studied upon several different Rapid Thermal Annealings on the as-deposited samples. Pole figures analysis shows that the intermetallic features a hexagonal structure (P6$_3$$/mmc$) with an NiAs-type (B8) structure. Although only one hexagonal structure is highlighted, the intermetallic exhibits two different domains characterized by different azimuthal orientations, axiotaxial relationship, and lattice parameters. The intermetallic phases seem to present a rather wide range of stoichiometry according to annealing temperature. The texture, structure, and stoichiometry of the intermetallic are discussed along with the evolution of lattice parameters of the Ni-InGaAs phase.

Auteur correspondant: "philippe.rodriguez@cea.fr"; International audience; In this work, we studied the solid-state reaction between a Ni$_{0.9}$Co$_{0.1}$ film and a silicon substrate. NiCo silicide is considered to substitute Ni-and NiPt-based silicides in 3D integration in order to extend the bottom transistor thermal stability. Thanks to the combined analysis of sheet resistance data, X-ray reflectivity spectra modelling, X-ray diffraction and wavelength dispersive X-ray fluorescence analyses on Ni$_{0.9}$Co$_{0.1}$ /Si samples annealed at various temperatures, we were able to describe the phase sequence of the NiCo silicide formation.

International audience; Silicon photonics is of great interest as it opens the way to large bandwidth and high data rates. A pioneer Silicon photonics scheme consists in integrating III-V lasers on the SOI substrates containing the passive components. However, key developments are necessary to co-integrate III-V devices with CMOS very large scale integration (VLSI). In this paper we propose a CMOS-compatible integration scheme of contacts (i.e. semiconductor metallization and plug) on III-V surfaces taking into account the limitations fixed by the operating laser device. Based on metallurgical, morphological, optical and electrical studies, processes are submitted and reviewed for the purpose of forming stable and reproducible contacts with low resistivity in a 200 millimeters fab line.

International audience; In this work, we studied the pretreatment of InGaAs layers by employing Ar-and He-based direct plasmas and NH$_3$ , H$_2$ , NF$_3$ /NH$_3$ remote plasmas. All the remote plasmas involved in this study were inadequate to remove the InGaAs native oxides. Moreover, for NF$_3$ /NH$_3$ exposed samples, we noticed the addition of undesirable In–F and Ga–F bonds. Concerning Ar and He direct plasmas, investigations exhibited that both seem to be efficient for removing arsenic oxides whereas the elimination of indium oxides is more effective with Ar plasma. We also studied the addition of hydrogen into He direct plasma and we demonstrated that increasing the H2 content leads to decreasing the removal of arsenic oxides. The impact on indium oxides is also notable as we observed a reducing effect of hydrogen on indium and the emergence of In–In type bonds. Finally, whatever the plasma pretreatment, no degradation of surface morphology and roughness was observed by AFM. The RMS values obtained after surface treatments are similar with the ones acquired for reference samples.

We have investigated the impact of various plasma treatments on InGaAs layers. Argon- and helium-based direct plasmas are more efficient than remote plasmas for the removal of InGaAs native oxides. We have demonstrated that the nature of direct plasma influences the InGaAs oxides removal efficiency. Indeed, both types of plasma seem to be efficient for removing arsenic oxides whereas the elimination of In oxides is more effective with Ar plasma. Hydrogen addition in He plasma impacts the removal of InGaAs oxides and appears to have a reducing effect on indium atoms. Whatever the nature of the pretreatment, the surface morphology and roughness of InGaAs layers were not significantly impacted.

International audience; In this work we introduce the use of physical plasmas (e.g. Ar-and He-based plasmas) in order to study the in situ cleaning (prior to metal deposition) of InGaAs layers dedicated to the realisation of self-aligned contacts. For the characterisation of cleaning efficiency, we performed surface analyses like X-ray photoelectron spectroscopy and Fourier transform infrared spectroscopy in attenuated total reflection mode. The first results described in this work are encouraging. We have found efficient processes for removing totally or partially III-V native oxides.

We studied the solid-state reaction of Ni thin films with InGaAs layers grown on InP or Si substrates. The inter-metallics obtained carried an hexagonal structure, but yielded a difference in orientation regarding either the substrates or the annealing temperature.

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Scalability in the fabrication and operation of quantum computers is key to move beyondthe NISQ era. So far, superconducting transmon qubits based on aluminum Josephson tunnel junctions have demonstrated the most advanced results, though this technologyis difficult to implement with large-scale facilities. An alternative “gatemon” qubit has recently appeared, which uses hybrid superconducting/semiconducting (S/Sm) devices as gate-tuned Josephson junctions. Current implementations of these use nanowires however, of which the large-scale fabrication has not yet matured either. A scalable gatemon design could be made with CMOS Josephson Field-Effect Transistors as tunableweak link, where an ideal device has leads with a large superconducting gap that contacta short channel through high-transparency interfaces. High transparency, or low contact resistance, is achieved in the microelectronics industry with silicides, of which some turnout to be superconducting. The first part of the experimental work in this thesis covers material studies on two such materials: V3Si and PtSi, which are interesting for their high Tc, and mature integration, respectively. The second part covers experimental results on 50nm gate length PtSi transistors, where the transparency of the S/Sm interfaces is modulated by the gate voltage. At low voltages, the transport shows no conductance at low energy, and well-defined features at the superconducting gap. The barrier height at the S/Sm interface is reduced by increasing the gate voltage, until a zero-bias peak appears around zero drain voltage, which reveals the appearance of an Andreev current.The successful gate modulation of Andreev current in a silicon-based transistor represents a step towards fully CMOS-integrated superconducting quantum computers., L’évolution de la fabrication et l’exploitation des ordinateurs quantiques est essentielle pour dépasser l’ère NISQ. Jusqu’à présent, les qubits transmon supraconducteurs basés sur des jonctions tunnel Josephson en aluminium ont donné les résultats les plus avancés, bien que cette technologie soit difficile à mettre en oeuvre dans des installations à grande échelle.Un autre qubit "gatemon" est apparu récemment, qui utilise des dispositifs hybrides supraconducteurs/semiconducteurs (S/Sm) comme jonctions Josephson accordées par un contrôle électrostatique. Cependant, les implémentations actuelles de ces dispositifs utilisent des nanofils, dont la fabrication à grande échelle n’a pas encore atteint sa maturité. Une conception évolutive de gatemon pourrait être réalisée avec des transistors à effet de champ Josephson CMOS comme lien faible accordable, où un dispositif idéal est constitué de réservoirs supraconducteurs qui contactent un canal court par des interfaces à haute transparence. Une transparence élevée, ou une faible résistance de contact,est obtenue dans l’industrie de la microélectronique avec des siliciures, dont certains s’avèrent être supraconducteurs. La première partie du travail expérimental de cette thèse couvre les études de matériaux sur deux de ces matériaux : V3Si et PtSi, qui sont intéressants pour leur Tc élevé, et leur intégration mature. La deuxième partie couvre des résultats expérimentaux sur des transistors PtSi de longueur de grille 50nm, où la transparence des interfaces S/Sm est modulée par la tension de grille. A basse tension,le transport ne montre aucune conductance à basse énergie, et des pics de cohérence bien définis au niveau du gap supraconducteur. La hauteur de la barrière à l’interfaceS/Sm est réduite en augmentant la tension de grille, jusqu’à ce qu’un pic de conductance apparaisse autour d’une tension de drain nulle, ce qui révèle l’apparition d’un courant d’Andreev. La modulation du courant d’Andreev par une grille dans un transistor à base de silicium, représente une étape vers des ordinateurs quantiques supraconducteurs entièrement intégrés en CMOS.