42 results on '"Shamiryan, D."'
Search Results
2. Integrated diffusion–recombination model for describing the logarithmic time dependence of plasma damage in porous low- k materials
3. In-line control of Si loss after post ion implantation strip
4. Effect of top power on a low- k film during oxygen strip in a TCP etch chamber
5. Dry etching process for bulk finFET manufacturing
6. Oxygen chemiluminescence in He plasma as a method for plasma damage evaluation
7. Charging of submicron structures during silicon dioxide etching in one- and two-frequency gas discharges
8. Plasma etching: From micro- to nanoelectronics
9. Diffusion of solvents in thin porous films
10. Spacer defined FinFET: Active area patterning of sub-20 nm fins with high density
11. Implementation of high- k and metal gate materials for the 45 nm node and beyond: gate patterning development
12. Low-k dielectric materials
13. Simulations of diffusion barrier deposition on porous low- k films
14. Pinhole density measurements of barriers deposited on low- k films
15. Optimization of low-k UV Curing: Effect of Wavelength on Critical Properties of the Dielectrics
16. Comparative study of PECVD SiOCH low-k films obtained at different deposition conditions
17. Investigation of barrier and slurry effects on the galvanic corrosion of copper
18. Improving mechanical robustness of ultralow-k SiOCH plasma enhanced chemical vapor deposition glasses by controlled porogen decomposition prior to UV-hardening.
19. Growth and characterization of atomic layer deposited WC[sub 0.7]N[sub 0.3] on polymer films.
20. Low dielectric constant materials for microelectronics.
21. Factors affecting an efficient sealing of porous low-k dielectrics by physical vapor deposition Ta(N) thin films.
22. Record ION/IOFF performance for 65nm Ge pMOSFET and novel Si passivation scheme for improved EOT scalability.
23. Integration challenges for multi-gate devices.
24. Demonstration of recessed SiGe S/D and inserted metal gate on HfO/sub 2/ for high performance pFETs.
25. Demonstration of Ni fully germanosilicide as a pFET gate electrode candidate on HfSiON.
26. Controlling STI-related Parasitic Conduction in 90 nm CMOS and Below.
27. Metrology for Implanted Si Substrate Loss Studies.
28. Effects of He Plasma Pretreatment on Low-k Damage during Cu Surface Cleaning with NH3 Plasma.
29. Effect of energetic ions on plasma damage of porous SiCOH low-k materials.
30. SELECTIVE REMOVAL OF HIGH-K GATE DIELECTRICS.
31. Using Ellipsometry for Assessment of TIN Surface Roughness after Plasma Etch.
32. Influence of crystallographic orientation on dry etch properties of TiN.
33. Diffusion barrier integrity evaluation by ellipsometric porosimetry.
34. Comparative study of SiOCH low-k films with varied porosity interacting with etching and cleaning plasma.
35. Characterization of Cu surface cleaning by hydrogen plasma.
36. Bulk FinFET fabrication with new approaches for oxide topography control using dry removal techniques.
37. Optimization of etching and stripping chemistries for Z3MS/sup TM/ Low-k.
38. Physical and electrical characterization of silsesquioxane-based ultra-low k dielectric films.
39. 8Å Tinv gate-first dual channel technology achieving low-Vt high performance CMOS.
40. Metal Inserted Poly-Si (MIPS) and FUSI dual metal (TaN and NiSi) CMOS integration.
41. 25% drive current improvement for p-type multiple gate FET (MuGFET) devices by the introduction of recessed Si0.8Ge0.2 in the source and drain regions.
42. Charging of submicron structures during silicon dioxide etching in one- and two-frequency gas discharges
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.