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This work studies differential pair circuits designed with Line tunnel field effect transistors (TFETs), comparing their suitability with conventional Point TFETs. Differential voltage gain (Ad), compliance voltage and sensitivity to channel length mismatch are analyzed experimentally for different temperatures. The first part highlights individual characteristics of Line TFETs, focusing on behaviors that affect analog circuits. In comparison to Point TFETs, Line TFETs present higher drive current, better transconductance and worse output conductance. In the second part, differential pairs are studied at room temperature for different dimensions and bias conditions. Line TFETs present the highest Ad, while Point TFET decrease the susceptibility to channel length mismatch. In the last part, the temperature impact is investigated. Based on the activation energy, the impact of band-to-band tunneling and trap-assisted tunneling is discussed for different bias conditions. A general equation is proposed, including the technology and the susceptibility to temperature and dimensions. It was observed that Line TFETs are a good option to design differential pairs with higher Ad and ON-state current than Point TFETs. [ABSTRACT FROM AUTHOR]

In this letter, we show that conventional III–V MOSFETs with moderate/high In content channels (In0.53Ga0.47As or In0.70Ga0.30As) at scaled nodes are incompatible with mobile SoC designs, which often operate at intermediate/high V{\mathrm {dd}} (0.7 V to $\geq 1$ V) to achieve high frequency including during burst-mode. The incompatibility is due to conventional III–V FETs having too small bandgap, and thus too high leakage when operated at the increased voltages. We show that FETs with a more optimal lower In content, In0.35Ga0.65As, have the necessary combination of larger bandgap (~Si) and sufficiently high injection velocity (~2.5 times Si) to enable both low leakage and high performance (versus Si), across the entire V{\mathrm {dd}} range of mobile SoC operation. We report for the first time the growth and characterization of ultra-thin In0.35Ga0.65As FETs with a standard 1nm EOT gate dielectric. Calibrated models show that In0.35Ga0.65As enables the highest performance at very low leakages at intermediate/high V{\mathrm {dd}} in short channel FETs. [ABSTRACT FROM PUBLISHER]

InGaAs homojunction Tunnel FET devices are demonstrated with sub-60 mV/dec Sub-threshold Swing (SS) measured in DC. A 54mV/dec SS is achieved at 100 pA/μm over a drain voltage range of 0.2-0.5 V. The SS remains sub-60 mV/dec over 1.5 orders of magnitude of current at room temperature. Trap-Assisted Tunneling (TAT) is found to be negligible in the device evidenced by low temperature dependence of the transfer characteristics. Equivalent Oxide Thickness (EOT) is found to play the major role in achieving sub-60 mV/dec performance. The EOT of the demonstrated devices is 0.8 nm. [ABSTRACT FROM AUTHOR]

When processing Si nanowire based Tunnel Field Effect Transistors (TFETS's), a significant reduction of B diffusion with decreasing nanowire diameter is observed and attributed to reduced transient enhanced diffusion close to the nanowire surface caused by the recombination and out-diffusion of excess self-interstitials. In this study, Ultra High Voltage Electron Microscopy (UHVEM) is used to study in situ the formation of self-interstitial clusters in nanowire based TFET containing samples prepared by Focused Ion Beam (FIB) thinning. Si nanowires with diameters ranging from 40 to 500 nm are irradiated in an UHVEM using different fluxes of 2 MeV electrons at temperatures between room temperature and 375 °C. A strong dependence of defect formation on nanowire radius and on dopant concentration and type is observed. The UHVEM observations are compared with simulations based on quasi-chemical reaction rate theory and with two dimensional dopant concentration distributions determined with high-vacuum Scanning Spreading Resistance Microscopy (SSRM). (© 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [ABSTRACT FROM AUTHOR]

Si nanowire-based Tunnel-Field Effect Transistor (TFET) characteristics are intensively studied as function of nanowire diameter and doping. A significant reduction of B diffusion with decreasing nanowire diameter is e.g. observed and attributed to reduced transient enhanced diffusion close to the nanowire surface caused by the recombination and out-diffusion of excess self-interstitials. In an Ultra High Voltage Electron Microscope (UHVEM), the formation of self-interstitial clusters can be studied in situ while varying e-beam flux, irradiation temperature, impurity concentration and capping layers surrounding the nanowires. Results are presented on {113}-defect formation in Si nanowires with diameters between 40 and 500 nm. The Si nanowires are embedded in SiO2 and are etched into an epitaxial Si stack on a heavily As doped Si substrate. The top layer of the epitaxial stack is in situ B doped or B implanted. In situ UHVEM studies are performed on focused ion beam prepared cross-section samples, irradiating with different fluxes of 2 MeV electrons between room temperature and 375 °C. A strong dependence of {113}-defect formation on nanowire radius and doping is observed. The observations are compared with simulations based on quasi-chemical reaction rate theory. (© 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [ABSTRACT FROM AUTHOR]