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The growing utilization of neural networks has led to a heightened focus on the hardware implementation of such networks. Security concerns associated with these implementations pose a significant challenge in this regard. Among these problems, the vulnerability of these networks against side-channel attacks such as power attacks can be mentioned. This paper presents a technique to enhance the resilience of hardware implementations of neural networks, particularly Hopfield neural networks, to mitigate the risks posed by power attacks. In addition to the fact that the proposed method makes it impossible to attack the network, it also reduces the power consumption of the entire circuit by reducing the leakage currents. The simulation results demonstrate that the proposed approach also achieves about a 10% reduction in energy consumption while concurrently improving the accuracy of the implemented associative memory by 1.1%. [ABSTRACT FROM AUTHOR]

BiFeO3 (BFO), Mn-doped-BFO (BFMO), Ti-doped-BFO (BFTO), and (Mn,Ti)-codoped-BFO (BFMTO) thin films are fabricated on the Pt/TiO2/SiO2/Si substrates via a sol–gel method combined with spin-coating and the subsequent layer-by-layer annealing technique. Compared with BFO film, the BFMTO film exhibits the lowest leakage current density (∼ 1 0 − 4 A/cm2@290 kV/cm). Notably, the polarization–electric field (P–E) loop of BFMTO film exhibits a positive displacement along the x-axis due to the existence of internal bias electric field, which is in agreement with the results of the PFM phase and amplitude curves. Especially, a very prominent inverse piezoelectric constant of d 3 3 ∼ 1 6 0 pm/V was obtained, which overcomes other related thin films. The internal bias electric field of BFMTO film can be caused by the different work functions of the thin film and the bottom electrode, accumulation of oxygen vacancies and the formation of defect dipoles. Besides, the internal bias electric field of BFMTO film has a good stability at the same electric field after experiencing the test cycle from low electric field to high electric field (400–1900 kV/cm). These results indicate that self-polarized BFMTO film can be integrated to devices without additional polarization process, and have a wide range of application in microelectromechanical systems. [ABSTRACT FROM AUTHOR]

This research presents a comprehensive investigation and optimization of the Pt/AlN Schottky Barrier diode (SBD) using technology computer-aided design (TCAD) modeling. The study explores the electrical characteristics of AlN SBDs with various metal contacts, including Aluminum (Al), Silver (Ag), Tungsten (W), Gold (Au), Nickel (Ni), and Platinum (Pt). Through the comparative analyses of different metal/AlN Schottky contacts, the Pt/AlN structure emerges as the most promising due to its superior barrier height and lower leakage current. At 3 0 0 ∘ K, the diode demonstrates a barrier height of 2.72 V, a nearly ideal leakage current of 0.046 pA, and a breakdown voltage of 363 V. The research extends to examining the temperature-dependent electrical behavior of Pt/AlN Schottky diodes, particularly for high-power and high-temperature applications. Analysis carried out across temperatures ranging from 3 0 0 ∘ K to 5 5 0 ∘ K reveals a trend of increasing ON resistance and consistently lower leakage current with rising temperature. Importantly, the study indicates that the impact of temperature on the barrier height and breakdown voltage of the diode is negligible, thus rendering it suitable for high-temperature operation. Leveraging the unique properties of AlN as an ultra-wide bandgap material within the III-V compound semiconductor family, this research provides valuable insights into the potential applications of Pt/AlN Schottky contact. The study highlights that the Pt/AlN Schottky contact is effective not only for high-power, high-temperature SBDs but also as superior metal/semiconductor gate contacts for field-effect transistors (FETs). Their suitability is attributed to their ability to handle high voltages, minimize reverse leakage current, and demonstrate improved thermal stability. [ABSTRACT FROM AUTHOR]

Since the leakage currents are dramatically increasing while the MOS transistors scale down to deep-submicron processes, the I – V characteristic of the channel is varied unintentionally. As a result, the analog integrated circuit (IC) designs based on it (at above 100-nm technologies) will malfunction. In this paper, a novel low-leakage double-body MOSFET (LLDB-M), as a circuit-level scheme in answering to the need for the current-mode analog IC design in deep-submicron processes, is proposed. In this technique, the sub-threshold and gate-oxide tunneling leakage currents (as two major parts) are reduced via lowering the gate-source voltage and increasing the threshold voltage of the MOS transistor. An LLDB-M consists of two typical transistors — the first one is the main transistor and the latter implements the shift-voltage to reduce the gate-source voltage and floor of the channel leakage currents. The drain, gate, and body of the main transistor as well as the body and source of the second one, organize the terminals of an LLDB-M. The proposed LLDB-M transistors are replaced with large-leakage transistors in a translinear loop in the weak inversion region and then the commonly-used circuits such-as the current mirror, one-quadrant multiplier-divider (at both up-down and stack topologies), the true RMS-DC converter, and the log-domain low-pass-filter are designed. The effectiveness and performance of the proposed LLDB-M technique and circuits are evaluated using HSPICE software in 22-nm BSIM4 CMOS process and Cadence Virtuoso tool in 65-nm TSMC CMOS technology. Post-layout simulation results show that the proposed circuit-level method by considerably reducing leakage currents could ensure the effective function of the current-mode analog IC designs in deep-submicron technologies. Also, comprehensive simulations have been performed to prove the robustness and reliability of the proposed circuits against process, voltage and temperature (PVT) changes. [ABSTRACT FROM AUTHOR]

Field effect transistors (FETs) in plasmonic regimes of operation could detect terahertz (THz) radiation and operate as THz interferometers, spectrometers, frequency-to-digital converters and THz modulators and sources. We report on the development of compact models for Si MOS (Metal-Oxide-semiconductor) and heterostructure-based plasmonic FETs (or TeraFETs) suitable for circuit design in the THz range and based on the multi-segment unified charge control model. This model accounts for the electron inertia effect (by incorporating segmented Drude inductances), for the ballistic field effect mobility, which is proportional to the channel length, for parasitic resistances and capacitances and for the leakage current. It is validated by comparison with experimental data and TCAD simulation results. The model can be used for simulation and optimization of sub-THz and THz detectors. Our simulations use up to 200 segments in the device channel. The results are also in good qualitative agreement with the hydrodynamic simulations. Applications of our model could dramatically reduce astronomical design costs of nanoscale VLSI reaching US$1.5 billion for the 3 nm technological node. [ABSTRACT FROM AUTHOR]

In this paper, the combination of a high step-up boost converter with extended voltage multiplier cell and isolated SEPIC converter with a series output module is presented. Since these converters use the same current source in their inputs, they can share the common parts, so the structure of the proposed converter is simple. In this converter, the high frequency transformer used in the SEPIC converter and the inductor of the extended voltage multiplier cell are coupled, so the volume of the magnetic parts is reduced. In addition, an active-clamp circuit is used to solve the problem of leakage inductor and achieve to Zero Voltage Switching (ZVS) turn on/off for switches and ZCS for diodes. Compared to its high step-up counterpart, the proposed converter has the following: (1) distributed voltage stress on the diodes and voltage of the output capacitors are fair. (2) Higher voltage gain. (3) Voltage stresses on the diodes are lower and the reverse-recovery problem of the diodes is eliminated. (4) Minimum root mean square (RMS) leakage inductor current. The operational principle and characteristics of the proposed converter are presented, and in order to verify the proposed converter, a 200 W, 20–400 V prototype converter is implemented and experimental results are provided. [ABSTRACT FROM AUTHOR]

Static random access memory (SRAM) is a sort of RAM where information is not permanently stored and does not require routine updating. To reduce leakage power without sacrificing performance, a variety of approaches have been applied to SRAM cells. In this study, we suggest a new 16T SRAM design that can function in active, park, standby, or hold modes. A fully static mode of operation for SRAM is made possible by the 16T SRAM structure, which also enhances write margin (WM) and removes charging conflict between devices during read and write operations. The key objectives of the suggested architecture are to retain logic state in park mode while maintaining stability and reducing standby time in active mode, as well as to reduce leakage current in standby mode. This is done by removing feedback from the back-to-back inverters during write operations via the data-dependent supply block. This makes it possible for the suggested bitcell to considerably increase the WM. A novel SRAM cell with 16 transistors is created with subthreshold operation and enhanced data stability. By using an equalized bit line technique to avoid leakage due to enhanced data pattern and RBL detection, the suggested single-ended SRAM cell with dynamic feedback control lowers the static noise margin for ultra-low power transfer. A sleep transistor is incorporated into the architecture to save power consumption when the system is in standby mode due to inefficient voltage transmission. Tanner EDA tool V.14.1 on 45-nm CMOS was used for design and simulation. The outcomes demonstrate a considerable decrease in no-load current and power loss. [ABSTRACT FROM AUTHOR]

Soft errors are the most common aspect of errors that are incurred in the memory devices during transmission. The common and fundamental reason of these soft errors is radiation that produces leakage of current and results in misleading information which is sent to various transmission stations via satellite and microwave communication. In this paper, the real-time embedded system is designed and implemented to mitigate the soft error using hybrid Hamming code. The work also develops the hardware system for soft error mitigation. The designed system is compared with the other coding schemes that are commonly available for error mitigation. The performance of real-time embedded system for soft error mitigation is carried out using signal-to-noise ratio and other performance metrics. The timing diagram analysis is the key metrics of the paper that defined the performance of the designed soft error mitigation design using the proposed technique. Furthermore, the results of the designed systems are demonstrated using bit error probability, Pb and channel symbol error probability (CSEP). The impact of the designed system will be that from now onwards using the proposed system, the soft error produced due to radiation and other reasons would not affect too much on transmission and reception of important data via satellite and microwave communication. [ABSTRACT FROM AUTHOR]

Currently, static circuit power is becoming a major concern, dominating the total power consumption due to the scaling down of CMOS technology. The smaller sizes drastically affect the leakage current, which integrated circuit designers attempt to overcome this issue. Hence, several methods and technologies have been proposed to prevail this phenomenon. One of these methods is using memory structures in logic designs. A Hybrid MTJ/CMOS circuit is one of these promising techniques to design low-power nonvolatile circuits with power gating ability and low overhead for reconfigurable possibilities. In this paper, we have proposed a fully nonvolatile, low-power Full-Adder based on MTJs that uses the spin transfer torque method assisted by the spin hall effect. Simulation results of these designs by HSPICE show that they can work fast with low-power consumption compared to other state-of-the-art nonvolatile full-adders. [ABSTRACT FROM AUTHOR]

Lead-free ( K 0. 5 Na 0. 5 )NbO3 (KNN) and Li 0. 0 6 ( K 0. 5 Na 0. 5 ) 0. 9 4 NbO3 (LKNN) thin films were fabricated by a sol-gel method. The effects of Li substitution on crystal structure, microstructure and electrical properties of KNN film were systematically studied. Li doping can enhance the ferroelectric and piezoelectric properties of KNN film. Compared with pure KNN film, the LKNN film possesses larger remanent polarization ( P r ∼ 9.3 μ C/ cm 2 ) and saturated polarization ( P s ∼ 41.2 μ C/ cm 2 ) and lower leakage current density (∼ 1 0 − 5 A/ cm 2 at 200 kV/cm). Meanwhile, a typical butterfly shaped piezoelectric response curve is obtained in the LKNN film with a high piezoelectric coefficient ( d 3 3 ∼ 105 pm/V). Excellent fatigue resistance (∼ 1 0 9 switching cycles) and aging resistance (∼ 180 days) demonstrate the long-term working stability of LKNN film. These findings indicate that KNN-based lead-free piezoelectric films have a broad application prospect in microelectromechanical systems (MEMS). [ABSTRACT FROM AUTHOR]

Most widely used dielectrics for MLCC are based on BaTiO3 composition which inevitably shows performance degradation during the application due to the migration of oxygen vacancies ( V o ⋅ ⋅ ). Here, the BaTiO3, ( Ba 0. 9 7 Ca 0. 0 3 )TiO3, Ba( Ti 0. 9 8 Mg 0. 0 2 )O3, ( Ba 0. 9 7 Ca 0. 0 3 )( Ti 0. 9 8 Mg 0. 0 2 )O3, ( Ba 0. 9 6 Ca 0. 0 3 Dy 0. 0 1 )( Ti 0. 9 8 Mg 0. 0 2 )O3 ceramics (denoted as BT, BCT, BTM, BCTM and BCDTM, respectively) were prepared by a solid-state reaction method. The core-shell structured grains (∼ 200 nm) featured with 10-20 nm wide shell were observed and contributed to the relatively flat dielectric constant-temperature spectra of BTM, BCTM and BCDTM ceramics. The TSDC study found that the single/ mix doping of Ca 2 + , especially the Mg 2 + , Mg 2 + /Ca 2 + and Mg 2 + /Ca 2 + /Dy 3 + could limit the emergence of V o ⋅ ⋅ during the sintering and suppress its long-range migration under the electric-field. Because of this, the highly accelerated lifetimes of the ceramics were increased and the value of BCDTM is 377 times higher than that of BT ceramics. The p − n junction model was built to explain the correlation mechanism between the long-range migration of V o ⋅ ⋅ and the significantly increased leakage current of BT-based dielectrics in the late stage of HALT. [ABSTRACT FROM AUTHOR]

In this paper, a new structure using dual junctions in the source and drain regions is proposed to improve the electronic characteristics of the doping less carbon nanotube FET. To simulate the proposed structure, the Poisson–Schrodinger equation self-consistent solution method through the nonequilibrium Green's function (NEGF) procedure has been used. The proposed structure is formed by dividing the source and drain regions into two parts with the same lengths and different work function for each part. The simulation results show that the short channel effects (SCEs) including the sub-threshold swing (SS) and the drain-induced barrier lowering (DIBL) are improved. Also, OFF current has a significant reduction, which in turn increases the current ratio. Besides, improving the ambipolar behavior and leakage current are other benefits of the proposed structure. [ABSTRACT FROM AUTHOR]

This paper proposes a novel method to control leakage and noise in domino circuits for wide fan-in OR logic with low power consumption, low process variation, and higher noise margin under the similar delay condition. In the proposed method, output and dynamic nodes are isolated from the PDN (Pull-Down Network) to improve the noise immunity and reduce switching activity. Further, with the aid of a transistor in the stack, the sub-threshold current is reduced. Thus, the proposed domino is applicable for high-speed and low-power applications in deep sub-micro-range. Simulation results show that the proposed domino improves the noise immunity and figure of merit (FOM) by factors of 1.95 and 2.34, respectively, with respect to the conventional domino with a footer. Along with this improvement, 26% reduction is also observed in power consumption. The entire simulations for all the domino circuits are done at 45-nm CMOS technology by using SPECTRE simulator under the Cadence Virtuoso environment. [ABSTRACT FROM AUTHOR]

Due to the exponential increase of transistor leakage currents, especially in the technologies lower than 90 nm, the static power consumption has dramatically increased. So, it is regarded as one of the main problems of the CMOS circuits. The spintronic devices, such as magnetic tunnel junction (MTJ), have notable advantages including low-static power consumption, nonvolatility, high endurance, compatibility with the CMOS transistors and the possibility of fabrication in high scales. Hence, the hybrid MTJ/CMOS circuits are considerable options to mitigate the problem of high-static power consumption in CMOS circuits. In this paper, a nonvolatile and low-power hybrid MTJ/CMOS full adder is proposed for implementation of in-memory computing. The drawback of existing full adders is their low-speed and high-power consuming for MTJ switching, which terribly affect the performance of multi-bit adders using these full adders. In this work, a new full adder is designed by eliminating the MTJ and transistor related to the input carry bit and modifying the tree structure of the MTJ network associated with the other inputs. In the proposed full adder, the effect of carry propagation has drastically decreased and its power consumption is also improved. [ABSTRACT FROM AUTHOR]

In this paper, studies of structural as well as electrical characteristics of the double perovskite material FeTiVO6 (iron titanium vanadate), synthesized by a high-temperature mixed oxide reaction method have been discussed. The room temperature X-ray diffraction analysis confirms the formation of a single-phase orthorhombic structure without any secondary phase. All the electrical characteristics (i.e., dielectric, impedance, conductivity and modulus) of the sample, studied at various temperatures (25–300°C) and frequencies (1 kHz–1 MHz), provide many remarkable characteristics of the material. The dielectric parameters as a function of frequency explain the presence of different polarization mechanisms based on the Maxwell–Wagner double-layer model. Impedance analysis describes the grain (bulk) and grain boundary (bulk interior) effect on the material using the equivalent RQC-RC circuits. The presence of non-Debye type of relaxation behavior in the material is confirmed by the depressed semicircles of Nyquist plots. The conductivity study provides information about the CBH and OLPT type of conduction phenomenon. The temperature dependence of leakage current behavior follows the Ohmic (semiconductor) and space charge limited conduction mechanisms at a different range of applied fields. The occurrence of the room temperature hysteresis loop obtained from the PE loop tracer confirms the ferroelectric behavior of the studied compound. [ABSTRACT FROM AUTHOR]

A wide-dynamic range high-efficiency differential RF-to-DC power converter for wireless power transfer (WPT) applications is presented. The architecture offers high power conversion efficiency (PCE) over a wide range of input powers by employing cross-coupled high-threshold rectifying devices with stacking diodes. The proposed rectifier uses the adaptive biasing technique to control the rectifying devices' conduction and minimizes the leakage current of the feedback diodes by utilizing the dynamic body biasing. Compared to the conventional cross-coupled rectifier, the proposed rectifier has a 9. 4 × better dynamic range. A prototype of the proposed rectifier is implemented in 65-nm CMOS technology and occupies an area of 0.0148 mm2. The rectifier achieves − 1 8. 1 dBm sensitivity for 1 V output and a 79.4% peak PCE. A dynamic range of 17.3 dB is achieved at the 433 MHz in the Industrial Scientific Medical band (ISM band) with a 100-K Ω load. Furthermore, the proposed design offers a peak PCE of 62.6% and a wide dynamic range of 16.1 dB at the UHF 900 MHz band with a load resistance of 100-K Ω. [ABSTRACT FROM AUTHOR]

This paper presents a novel low-leakage 10T SRAM cell along with its new read circuitry. It utilizes isolated read path for the read operation that enhances the read stability of the cell as compared to conventional 6T SRAM cell. The proposed cell has been introduced for IoT applications where low power devices are the primary requirement in order to enhance the battery life. To minimize the leakage current, the PMOS transistor has been employed at the read circuitry which assists to minimize the leakage current due to induced stacking effect. The leakage current is 37.66%, 40.11% and 67.39% less as compared to 6T SRAM, 8T SRAM and RDPFC 9T SRAM cells, respectively. The read delay for the proposed cell is 39.80%, 89.13% and 42.33% less as compared to 6T SRAM, 8T SRAM and RDPFC 9T SRAM cells, respectively. Also, the results depict the speed improvement of 48.60%, 52.49% and 55.71% during write "0" and 46.97%, 57.5% and 54.52% improvement during write "1" operation as compared to 6T SRAM, 8T SRAM and RDFC 9T SRAM cells, respectively. The RSNM of the proposed cell is 649 mV that shows enhanced read stability over conventional 6T SRAM cell. The proposed cell proves its robustness against worst-case process variations. All the simulation work has been completed on the Cadence Virtuoso environment at 180 nm technology node. [ABSTRACT FROM AUTHOR]

This paper presents the proposed inductorless RF-Symmetrical DC energy harvester for low power biosensor transceiver. It is designed to benefit from the symmetrical power supply to reduce the low noise amplifier power consumption of the biosensor reception part. Several techniques are used in this work to design a high efficiency RF-DC harvester with minimum number of stages as: the use of the diode-connected CMOS transistor which its bulk is related to its drain to minimize the leakage current and to reduce the threshold voltage for more energy harvesting, and the use of the Greinacher voltage multiplier to decrease the effect of the voltage drop between the drain and the source of the CMOS transistor. The impedance matching circuit between the antenna and the energy converter is designed without inductors to gain more power and space. Conceived under the 0.18 μ m TSMC MOS technology with only four stages, the harvester simulation results show a high efficiency of 56% which the minimal voluntary received power is about 0dBm required by the IEEE 802.15.4 standard. The symmetrical DC output voltage is of 1/ − 1V as expected in the specifications. Therewith, its delivered power is equal to 1mW for storage capacity about 20 nF. [ABSTRACT FROM AUTHOR]

MIM devices fabricated with 10-nm thickness of Al2O3 high- k thin film deposited using plasma-enhanced atomic layer deposition (PEALD) system on Al-coated Si substrate were investigated. The structural, morphological and electrical properties of Ti/Al2O3/Al/Si MIM capacitors as-deposited and post-deposition annealed (PDA) at different temperatures were studied and compared. Al2O3 thin films were investigated using atomic force microscopy (AFM) and X-ray diffraction (XRD) and Ti/Al2O3/Al/Si MIM capacitors were characterized by current–voltage (I – V) and capacitance–voltage (C – V) measurements. The stable phase formation of Ti/Al2O3/Al/Si MIM capacitor provides the lowest leakage current density in the range of nA/cm2 for as-deposited and annealed films. [ABSTRACT FROM AUTHOR]

In the proposed work, a differential write and single-ended read half-select free 12 transistors static random access memory cell is designed and simulated. The proposed cell has a considerable reduction in power dissipation with better stability and moderate performance. This cell operates in subthreshold region and has a higher value of read static noise margin as compared to conventional six transistors static random access memory cell. A power cut-off technique is utilized between access and pull-up transistors during the write operation. It results in an increase in write static noise margin as compared to all considered cells. In the proposed cell, read and write access time is improved along with a reduction in read/write power dissipation as compared to conventional six transistors static random access memory cell. The bitline leakage current in the proposed cell is reduced which improves the Ion/Ioff ratio of the cell under subthreshold region. The proposed cell occupies less area as compared to considered radiationhardened design 12 transistors static random access memory cell. The computed electrical quality metric of proposed cell is better among considered static random access memory cells. Process variation analysis of read stability, access time, power dissipation, read current and leakage current has been performed with the help of Monte Carlo simulation at 3,000 points to get more soundness in the results. All characteristics of static random access memory cells are compared at various supply voltages. [ABSTRACT FROM AUTHOR]

This paper introduces a device performance optimization approach for the FinFET through optimization of the gate length. As a result of reducing the gate length, the leakage current (Ioff) increases, and consequently, the stress along the channel enhances which leads to an increase in the drive current (Isat) of the PMOS. In order to sustain Ioff, work function is adjusted to offset the effect of the increased stress. Changing the gate length of the transistor yields different drive currents when the leakage current is fixed by adjusting the work function. For a given device, an optimal gate length is found to provide the highest drive current. As an example, for a standard performance device with Ioff = 1 nA/um, the best performance Isat = 856 uA/um is at L = 34 nm for 14 nm FinFET and Isat = 1130 uA/um at L = 21 nm for 7 nm FinFET. A 7 nm FinFET will exhibit performance boost of 32% comparing with 14 nm FinFET. However, applying the same method to a 5 nm FinFET, the performance boosting is out of expectance comparing to the 7 nm FinFET, which is due to the severe short-channel-effect and the exhausted channel stress in the FinFET. [ABSTRACT FROM AUTHOR]

Leakage power reduction of an SRAM-based look-up table (LUT) in field-programmable gate array (FPGA) has been achieved in this work by implementing an efficient and dynamic power gating technique. The logic of gating is based on the theory of automatically shutting down the power supply to the inactive blocks of LUT during runtime, contrary to all previous works which involved manual intervention for the implementation of power gating. Two techniques of power gating are introduced in this work, PG1 and PG2. PG1 results in more power savings than PG2, however, PG2 has an advantage of low area overhead. Simulation has been carried out for all possible input combinations of LUT, designed in Cadence Virtuoso tool at 45nm technology. The results indicate a leakage power reduction of up to 50% in PG1 technique, with an average area overhead of 14.15%. The power savings in PG2 is up to 38%, with a minimal increase in area of 1.76%. The power bounce noise is also analyzed for the proposed techniques and reported. [ABSTRACT FROM AUTHOR]

Comparative assessment of graded channel gate stack (GCGS) DG MOSFET structure is done by using two-dimensional (2D) Sentrausu TCAD simulator for different high K oxide thickness. This novel device includes gate stack (GS) engineering (high K) and nonuniformly channel engineering (GC) to suppress the short channel effects and improve the device performance. This novel device can be a better alternative for the future high speed switching and low power circuit applications. It has the advantage of improved breakdown voltage, reduced leakage current, low output conductance and reduced bipolar parasitic effects. The given device must be properly investigated with respect to the variation of different high K oxide thickness on different parameters such as drain induced barrier lowering (DIBL), subthreshold slope (SS), /, roll off before fabrication to have better reliability. The 2D Sentrausu TCAD simulator using drift-diffusion model was used to simulate the developed structure and good agreement is obtained with respect to already published result in the sub-threshold regime. The result indicates that there is a need to be optimize the DC parameters for specific circuit applications. In this work, we studied the DC and SCEs of the Graded Channel Gate Stack-DG MOSFETs with variation of high-K oxide thickness for different channel length with the help of TCAD simulator. The study gives us an idea that proper optimization of high-K oxide thickness for specific channel length is essential for specific DC applications and also to limit the short channel effects. This novel device can be a better alternative for the future high speed switching and low power circuit applications. [ABSTRACT FROM AUTHOR]

A new model for efficiency droop in InGaN/GaN light-emitting diodes (LEDs) is proposed, where the primary nonradiative recombination mechanisms, including Shockley-Read-Hall (SRH), Auger and carrier leakage, are considered. A room-temperature external quantum efficiency (EQE) measurement was performed on our designed samples and analyzed by the new model. Owing to advantages over the common ' model', the 'new model' is able to effectively extract recombination coefficients and calculate the leakage currents of the hole and electron. From this new model, we also found that hole leakage is distinct at low injection, while it disappears at high injection, which is contributed to the weak blocking effect of electron in quantum wells (QWs) at low injection. [ABSTRACT FROM AUTHOR]

This paper presents the modeling of saturated dual stator induction generator (DSIG) for analysis of its transient and dynamic behavior for stand-alone operation. In the analytical model, the effect of common mutual leakage reactance between the two three-phase winding sets and the cross saturation have been considered. For this purpose, a detailed description of a procedure to introduce magnetic saturation in found models is presented. Paper also discusses the possibility of DSIG for supplying two individual loads by presenting the results of analytical and experimental study of transient behavior under various operating conditions. Use of such models leads to more accurate predictions in industrial drives, especially wind driven power generation systems. This is verified by experimental lab tests. [ABSTRACT FROM AUTHOR]

Wide fan-in dynamic logic OR gate has always been an integral part of high speed microprocessors. However, low noise immunity of wide fan-in dynamic logic gate is always an issue of concern. For maintaining high noise immunity, various large sized PMOS keeper-based dynamic OR gates are proposed in the literature. These designs allow large leakage through them for maintaining high noise immunity which unnecessarily increases the power dissipation. This can be a critical issue for microprocessors used in battery operated devices. Independent gate (IG) FinFET devices are known to reduce leakage current through them using back gate biasing technique. In this paper, a novel FinFET-based wide fan-in dynamic OR gate has been proposed with effective leakage control and high noise immunity. This work reports a maximum leakage power reduction up to 70% while maintaining up to 90% higher noise immunity as compared to standard dynamic OR gate at low keeper size. This work also mathematically illustrates the effective leakage reduction capability of FinFET as compared to CMOS and hence proves its preference over CMOS in wide fan-in dynamic OR gate. [ABSTRACT FROM AUTHOR]

In this paper, a 1 mm × 1 mm fully integrated wideband dual-stage power amplifier (PA) for long-term evolution (LTE) band 1 (1920-1980 MHz) is presented. Fabricated in a 2 μm hetero-junction bipolar transistor (HBT) process, the operating gain is observed to be 31.3 dB. The PA meets the minimum adjacent channel leakage ratio (ACLR) requirement of -30 dBc for LTE with 20 MHz wide channel bandwidth up to an output power of 30 dBm with the aid of a novel dual stage linearizer. Biased at low quiescent current of less than 100 mA with a headroom consumption of 3.5 V, the power added efficiency (PAE) is observed to be 38.29% at 30 dBm. With this high linear output power, the stringent requirement of antenna path loss is nullified. PA serves to be the first reported work to achieve 30 dBm linear output power at supply voltage of 3.5 V. [ABSTRACT FROM AUTHOR]

In this paper, a novel power gating method has been proposed with the combination of complementary metal oxide semiconductor (CMOS) logic and FinFET for better sub-threshold leakage current minimization. Sub-threshold leakage currents take the paramount part in overall contribution to total power dissipation which comprises of scaling and power reduction. Power gating technique takes up priority among the different leakage current reduction mechanisms. The novel approach has been applied to a CMOS inverter and a two input CMOS NAND gate. The inverter simulated with high threshold voltage metal oxide semiconductor field effect transistor (MOSFET), VGOT MOSFET and fin field effect transistor (FinFET) as sleep transistor reduces the sub-threshold leakage current by 45.529%, 47.265% and 86.431%, respectively, when compared with inverter in absence of sleep transistor. This proves substantial improvement as compared to the planar CMOS inverter. Further, these techniques applied for a two input NAND gate resulted in reduction of leakage current by 20.536%, 23.955% and 99.942%, respectively. [ABSTRACT FROM AUTHOR]

Polycrystalline Bi0.975La0.025Fe0.975Ni0.025O3 (BLFNO) film is fabricated on Pt/Ti/SiO2/Si(111) substrate by sol-gel method. It is found that the well-crystallized BLFNO film is polycrystalline, and the Pt/BLFNO/Pt capacitor possesses good ferroelectric properties with remnant polarization of 74 μC/cm2 at electric field of 833 kV/cm. Moreover, it is also found measurement temperature ranging from 100 to 300 K. The leakage density of the Pt/BLFNO/Pt capacitor satisfies space-charge-limited conduction (SCLC) at that the leakage current density of the Pt/BLFNO/Pt capacitor increases with the increase of higher electric field and shows little dependence on voltage polarity and temperature, but shows polarity and temperature dependence at lower applied electric field. With temperature increasing from 100 to 300 K at lower applied electric field, the most likely conduction mechanism is from Ohmic behavior to SCLC for positive biases, but no clear dominant mechanism for negative biases is shown. [ABSTRACT FROM AUTHOR]

Standby switch can strongly turn off all the high threshold voltage transistors, which enhances the effectiveness of a dual threshold voltage CMOS technology to reduce sub-threshold leakage current. Sub-threshold leakage currents are especially important in burst mode type integrated circuits where the system is in an idle mode in the majority of the time. The standby switch allows a domino system to enter and leave a low leakage standby mode within a single clock cycle. In addition, we combine domino dynamic logic with pass transistor XNOR and pass transistor NAND gates to achieve logic 1 output during its precharge phase without affecting circuits operation in its evaluation and standby phase. The required process for dual threshold voltage circuit configuration involves only one additional ion implant step to provide an extra threshold voltage. SPICE simulation for our proposed circuits is made using a 0.18 μm CMOS processes from TSMC, with 10 fF capacitive loads in all output nodes, and parameters for typical process corner at 25°C. Layout is designed, wafer is fabricate and measured. The measurement results of fabricated chips are listed and verify that our designed 8-bit carry look-ahead adders (CLAs) reduced power consumption and propagation delay time by more than 15% and around 20%, respectively, when compared with the prior work. [ABSTRACT FROM AUTHOR]

The intention of this paper is to reduce power and area of 2:1 multiplexer (MUX) while maintaining the competitive performance. The various configurations are designed using different topology of 2:1 MUX such as CMOS-based MUX, transmission gate and pass transistor using fin-shaped field effect transistor (FINFET). The mobility was enhanced in devices with taller fins due to increase tensile stress. In DG, FINFET can be efficiently used to develop performance and reduce power consumption. In noncritical paths self-determining gate control can be used to join together parallel transistors. We have estimated the optimum power, optimum current, leakage power, leakage current, operating power, operating current and delay in voltage supply 0.7 V at different temperature such as 10°C, 27°C and 50°C, respectively. A 20 ns access time and frequency 0.5 GHz provide 45 nm CMOS process technology with 0.7 V power supply is employed to carry out different topology of 2:1 MUX using FINFET. [ABSTRACT FROM AUTHOR]

CMOS technologies are suffering from increased variability due to process, supply voltage and temperature (PVT) variations as we enter the tens-of-nanometer regime. Analog and mixed-signal circuits have failed to effectively exploit the high-speed and low-noise properties that deep scaled CMOS technologies provide due to marginality issues. Large variations in leakage current and threshold voltage also make highly integrated digital designs challenging. In addition, device aging introduces a temporal dimension to variations in circuit performance. Consequently, there is an increasing need for a new design methodology that can provide high yield and reliability under severe parametric variations. Although several post-silicon calibration and repair strategies have been proposed to address the PVT variations, no coherent design strategy for a SoC has been developed so far. We espouse a self-healing technique based on real-time sensing and built-in feedback due to its inherent advantage of dynamic adaptation to temporal variations. This tutorial paper outlines our vision of improving marginalities in deep scaled CMOS technologies using a generic and systematic self-healing design including a system-level auto-correction algorithm. It also illustrates this methodology with design examples. [ABSTRACT FROM AUTHOR]

10-nm-thick amorphous 3 film was deposited on n-type (001) substrate at 600°C by magnetron sputtering and then annealed in 2 ambience at 300°C for 2 min using a rapid thermal annealing furnace. Grazing incidence X-ray diffraction analyses indicated that the post-annealed 3 film was still amorphous. The root-mean-square roughness of the post-annealed sample is a little smaller than that of the as-grown sample, which could stem from the densification of 3 film after post-annealing. No obvious hysteretic behavior was observed in the capacitance-voltage measurement and the dielectric constant of 3 film was estimated to be 16.7. Due to the deficiency of oxygen vacancy after post-annealing, the low leakage current density of the post-annealed film with EOT of 2.33 nm is about 5.52 × 10-5 A/cm2 at +1 MV/cm. Moreover, it is found that both the as-grown and post-annealed capacitors satisfy Ohmic conduction behavior at the whole positive measured electric fields. [ABSTRACT FROM AUTHOR]

Due to the regularity of implementation, multiplexers are widely used in VLSI circuit synthesis. This paper proposes a technique for decomposing a function into 2-to-1 multiplexers performing area-power tradeoff. To the best of our knowledge this is the first ever effort to incorporate leakage into power calculation for multiplexer-based decomposition. With respect to an initial ROBDD (reduced ordered binary decision diagram)-based representation of the function, the scheme shows more than 30% reduction in area, leakage and switching for the LGSynth91 benchmarks without performance degradation. It also enumerates the trade-offs present in the solution space for different weights associated with these three quantities. [ABSTRACT FROM AUTHOR]

An isolated high step-up DC-DC converter with a continuous input current is proposed. The proposed converter consists of two converter cells - a boost converter cell at the input stage for a low input current ripple and a DC-DC converter cell for high voltage gain. Zero-voltage-switching of power switches are achieved and the leakage inductance of the transformer alleviates the reverse-recovery problems of the output diodes. Therefore, the proposed converter achieves high efficiency. Detailed analysis and design of the proposed converter are carried out. A prototype of the proposed converter is developed, and its experimental results are presented for validation. [ABSTRACT FROM AUTHOR]

Dimensions of metal-oxide-semiconductor field effect transistor (MOSFET) have been scaled down for decades to maintain the performance. So, as a result of aggressive scaling, gate oxide thickness approaches its manufacturing and physically limiting value of less than 2 nm in nano regime. Under such circumstances, gate leakage (tunneling) current has become a critical problem in nano domain as compared to subthreshold leakage current. Consequently, accurate quantitative understanding of gate tunneling leakage current is very important especially in context of low power VLSI application. In this work, gate tunneling currents have been modeled including the inevitable nano scale effects for a MOSFET having different high-k dielectric spacer such as SiO2, Si3N4, Al2O3, HfO2. The gate current model is compared and contrasted with santaurus simulation results and reported experimental result to verify the accuracy of the model. The agreement found was good, thus validating the developed analytical model. It is observed that neglecting nano scale effects may lead to large error in the calculated gate current. It is found in the results that gate leakage current decreases with the increase of dielectric constant of the gate spacer. Further, it is also reported that the spacer materials impact the threshold voltage, on current, off current, drain induced barrier lowering, and subthreshold slope of the device. [ABSTRACT FROM AUTHOR]

In this paper, a newly improved dynamic current mode logic (I-DyCML) is proposed to achieve low power dissipation. The principle used in I-DyCML is the reduction of the leakage current by turning the part of the circuit to "standby mode", when not in use, while achieving lower dynamic power during the active mode. HSpice simulations show that I-DyCML saves up to 15–30% of the total power dissipation when compared to Dynamic Current mode logic. [ABSTRACT FROM AUTHOR]

The high leakage current in deep submicron regimes is becoming a significant contributor to the power dissipation of CMOS circuits as the threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for the estimation and reduction of leakage power, especially in the low power applications. This paper explores the various transistor intrinsic leakage mechanisms including the weak inversion, the drain-induced barrier lowering, the gate-induced drain leakage, and the gate oxide tunneling. [ABSTRACT FROM AUTHOR]

There is a growing need to analyze and optimize the stand-by component of power in digital circuits designed for portable and battery-powered applications. Since these circuits remain in stand-by (or sleep) mode significantly longer than in active mode, their stand-by current, and not their active switching current, determines their battery life. Hence, stringent specifications are being placed on the stand-by (or leakage) current drawn by such devices. As the power supply voltage is reduced, the threshold voltage of transistors is scaled down to maintain a constant switching speed. Since reducing the threshold voltage increases the leakage of a device exponentially, leakage current has become a dominant factor in the design of VLSI circuits. In this paper, we describe a method that uses simultaneous dynamic voltage scaling (DVS) and adaptive body biasing (ABB) to reduce the total power consumption of a processor under dynamic computational workloads. Analytical models of the leakage current, dynamic power, and frequency as a function of supply voltage and body bias are derived and verified with SPICE simulation. Given these models, we show how to derive an analytical expression for the optimal trade-off between supply voltage and body bias, given a required clock frequency and duration of operation. The proposed method is then applied to a processor and is compared with DVS alone for workloads obtained using real-time monitoring of processor utilization for four typical applications. [ABSTRACT FROM AUTHOR]