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Your search keyword '"Yuzuru Ohji"' showing total 22 results
Start Over Author "Yuzuru Ohji" Publisher the japan society of applied physics
22 results on '"Yuzuru Ohji"'

6. Vertical Scaling of Metal/High-k Gate Stacked MOSFETs for Hp45 and Beyond

Author

Takahisa Eimori, M. Nakamura, Takanobu Watanabe, Takashi Onizawa, Motoyuki Sato, Takeo Matsuki, Yasuo Nara, Yuzuru Ohji, T. Morooka, and Masaru Kadoshima

Subjects
Metal, Materials science, visual_art, Vertical scaling, visual_art.visual_art_medium, Nanotechnology, Engineering physics, High-κ dielectric
Published
2008

12. Systematic studies on Fermi level pining of Hf-based high-k gate stacks

Author

Kenji Shiraishi, Heiji Watanabe, Yasuo Nara, Kenji Ohmori, Kizuku Yamada, Y. Akasaka, Kikuo Yamabe, Masaru Kadoshima, G. Nakamura, Toyohiro Chikyow, and Yuzuru Ohji

Subjects
symbols.namesake, Materials science, Condensed matter physics, Fermi level, Gate stack, symbols, Nanotechnology, High-κ dielectric
Published
2007

16. Low-Noise and High-Frequency 0.10μm body-tied SOI-CMOS Technology with High-Resistivity Substrate for Low-Power 10Gbps Network LSI

Author

Tatsuhiko Ikeda, Masahide Inuishi, Shigeto Maegawa, Harufusa Kondoh, Daniel Chen, Yasuo Inoue, Toshiaki Iwamatsu, Yuzuru Ohji, Tsutomu Yoshimura, Yuuichi Hirano, Takashi Ipposhi, Toshihide Oka, Hiroyuki Takashino, Takuji Matsumoto, and Mikio Tujiuchi

Subjects
High resistivity, Materials science, business.industry, Soi cmos technology, Optoelectronics, Substrate (printing), business, Low noise, Power (physics)
Published
2003

17. W-Polymetal Gate with Low W/Poly-Si Interface Resistance for High-Speed/High-Density Embedded Memory

Author

Tomohiro Yamashita, Yuzuru Ohji, Y. Nishida, Takahisa Eimori, Masahide Inuishi, and Kiyoshi Hayashi

Subjects
Contact process, Materials science, business.industry, Contact resistance, Transistor, General Engineering, General Physics and Astronomy, law.invention, CMOS, Gate oxide, law, Logic gate, Electrode, MOSFET, Optoelectronics, business, Ohmic contact
Abstract

A new W-polymetal gate electrode with the structure of W/WN/WSi/poly-Si is proposed. The W-polymetal gate is suitable for high-density memories since it has low resistance and is compatible with the self-aligned contact process. In our study, however, it is found that the interface of W and poly-Si has non-ohmic and quite high resistance in the case wherein only WN is used as a barrier film. This resistance increases the delay in complementary metal-oxide-semiconductor (CMOS) logic circuits and prevents high-speed operation. Our new process includes the deposition of thin WSi on poly-Si, followed by rapid thermal annealing, which results in ohmic and sufficiently low contact resistance between W and poly-Si. It is also demonstrated that selective gate reoxidation is successfully applied for this new structure, and the insertion of thin WSi does not cause any adverse effect on the electrical characteristics of metal-oxide-semiconductor field-effect transistor (MOSFET). This process is promising for high-speed and high-density embedded memory.

Published
2003

19. Highly Reliable N2O-Oxynitrided Tunnel Oxides for Flash Memory

Author

Takashi Nishida, Masahiro Ushiyama, Tetsuo Adachi, Toshiyuki Mine, Kiyoshi Ogata, Masataka Kato, Naoki Miyamoto, Hitoshi Kume, and Yuzuru Ohji

Subjects
Materials science, business.industry, Optoelectronics, business, Flash memory
Published
1994

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