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With the slowing down of Moore’s law, related to conventional scaling of integrated circuits, alternative technologies will require research effort for pushing the limits of new generations of electronic or photonic devices. Perovskite oxides with the ABO3 chemical formula have a very wide range of interesting intrinsic properties such as metal-insulator transition, ferroelectricity, pyroelectricity, piezoelectricity, ferromagnetic and superconductivity. For the integration of such oxides, it is of great interest to combine their properties with traditional electronic, memory and optical devices on the same silicon-based platform. In the context of high-speed chip-to-chip optical interconnects, compact high-resolution beam steering and video-rate RGB hologram generation require the integration of fast and efficient optical modulators on top of silicon CMOS devices. For these applications the integration of high quality electro-optical materials A defect-free material-stack deposition on silicon wafers is hence required. Among the possible materials options, barium titanate (BaTiO3) is one promising candidate due to its large intrinsic Pockels coefficients that can be obtained. In a first part of the talk, we will review the different options to integrate BaTiO3 on Silicon substrate though different templates to control the polarization direction and discuss the influence on the physical, electrical and optical properties. Then in the second section we will discuss the use of perovskites oxide in the field of topological based qubits which is one of the promising methods for realizing fault-tolerant computations. It is recognized that superconductor/topological insulator heterostructure interfaces may be a perfect host for the exotic “Majorana” particles. These have relevant topological protection nature as required for processing information. Therefore, the physics at the superconductor/topological insulator heterostructure interface need to be studied further, starting at the material level. In this work, a candidate material Barium Bismuthate (BBO) is studied utilizing the Oxide Molecular Beam Epitaxy (MBE) process. The perovskite structure provides opportunity for easily tailored functionality through substitutional doping. Incorporation of potassium into the lattice of BBO results in a superconducting phase with Curie temperature as high as ~ 30K. In addition, BBO is according to DFT based studies, predicted to form topological surface states when doped with Fluorine. In our work, we integrate BBO perovskite on Si(001) substrate, using an epitaxially grown strontium titanate (STO) single-crystalline buffer layer and discuss the structural and chemical properties of the heterostructure will be established by utilizing physical characterization techniques such as AFM, and TEM in later stages. This will go hand in hand with the understanding of the ARPES studies and related surface reconstruction of BBO observed by RHEED as a criterion for the high-quality films. This project has received funding from the European Research Council (ERC) under the European Union’s Horizon 2020 research and innovation program (grant agreements No 864483 and 742299)”.

aalso at E.E. Dept. KU Leuven, Kasteelpark Arenberg 10, B-3001 Leuven, Belgium Since the 45 nm CMOS node, high-k gate dielectrics and strain engineering go hand in hand to further boost the transistor performance. An example of a so-called global strain platform relies on a thin strained-silicon (sSi) layer on top of a strain-relaxed Si1-xGex buffer (SRB) (Fig. 1). In addition, replacing thermally grown SiO2 by a deposited dielectric opens the door for the implementation of so-called high-mobility channel materials (Ge – pMOS; InxGa1-xAs – nMOS;...), which can be grown hetero-epitaxially on a silicon substrate. Due to the lattice mismatch of most of these materials with silicon, strain relaxation will occur above a certain critical thickness, leading to the introduction of both misfit and threading dislocations (TDs). It is well-known that dislocations introduce a one-dimensional band of states in the band-gap and hence are electrically active [1],[2]. The aim of the present review is to address the impact of such extended defects on the electrical performance of simple devices (p-n junctions, MOSFETs,...) for various high-mobility materials. A first example which will be discussed is the impact of TDs on the current-voltage (I-V) characteristics of p-n junctions fabricated in sSi and relaxed-Ge-on-Si substrates. As can be derived from Fig. 1, the depletion region mainly extends in the SiGe SRB, so that the electrical activity of the dislocations in this layer will be probed. It is clear from Fig. 2 that the reverse current IR of the diodes more or less proportionally increases with the density of TDs [3]. The same applies for the recombination and generation lifetime. Similar studies have been carried out for p-n junctions fabricated in a Si0.2Ge0.8 SRB and in relaxed Ge-on-Si epi layers. Summarizing all these results in Fig. 3, one can observe that the area leakage current density increases proportionally with the density of TDs and exponentially with the Ge content [4]. The latter can be explained by considering the impact on the band gap, yielding an exponential increase of the intrinsic carrier density. Comparing with Fig. 3b, it is clear that there exists a trade-off between leakage current density and epi layer thickness: thinner relaxed Ge layers on silicon will have a higher equilibrium TD density [5] and, hence, leakage current. However, considering a typical SRAM cell design, it can be concluded that for typical TDD values of 107-108 cm-2, the contribution to the off-state leakage is negligible compared with the contribution of the perimeter. A second example investigates the impact of anti-phase boundaries (APBs) on the reverse current of p-n junctions fabricated in GaAs (Fig. 4a) will be discussed. As can be derived from Fig. 4b, there is a modest increase of IRbetween on-axis junctions with a high APB density and off-axis diodes. Overall, it has been concluded that APBs are not so efficient leakage generators in GaAs. Finally, the impact of TDs on other device parameters, like the mobility or the threshold voltage of a MOSFET will be discussed. References [1] W. Schröter and H. Cerva, Solid State Phenomen., 85-86, p. 67 (2002). [2] E. Simoen et al., J. Electrochem. Soc., 158, p. R27 (2011). [3] G. Eneman et al., Appl. Phys. Lett., 87, p. 192112 (2005). [4] E. Simoen et al., J. Electrochem. Soc., 157, p. R1 (2010). [5] G. Wang et al., Appl. Phys. Lett., 94, p. 102115-1 (2009). Figure 1

Driven by fabrication cost reduction and device performance improvement, the Silicon semiconductor industry continues its never-ending pursuit of new approaches for fabricating integrated circuits. Monolithic integration of III-V semiconductors epitaxially grown on Si substrate have been attracting much attention as building blocks for next-generation electronics and photonics due to their potential intrinsic properties. Direct heteroepitaxy of III-V compound semiconductors on Si has traditionally represented a formidable challenge, due to the extensive lattice mismatch of 8% between the Si substrate and high mobility III-V compounds, such as In0.53Ga0.47As/InP heterostructure. The defect confinement technique has recently attracted great interest due to the possibility of obtaining high quality III-V based active layers on Si. Using this approach we integrate III-V materials monolithically on Si through the epitaxial growth of III-V materials into a pre-patterned structure by Selective Area Metal-Organic Vapor Phase Epitaxy. We report here on the growth of InP on STI patterned Si wafers using the defect confinement technique while focusing on scaled trench widths (W < 50 nm). We demonstrate the impact of the crystalline alignment of the InP layer with the underlying substrate by exploring as starting geometry at the bottom in between the STI either a rounded etch pit covered with a Ge buffer layer versus a crystalline V-groove structure in Si. We show the large impact of the main layer growth temperature and the growth pressure on the trench filling, the growth uniformity and the crystal quality which we could correlate with changes in resistivity and the presence of impurity diffusion in the III-V layer. Moreover, we derived a fundamental understanding and theoretical modeling of the growth mechanisms in STI trenches and the determining role of the nucleation layer. This lead to a strong enhancement of the crystalline quality and growth uniformity of the InP semiconductor. As a conclusion, this study of III-V selective area growth brings some elements for the optimization of the heteroepitaxy of III-V compounds on (001) oriented Si substrates. The demonstration of a clear reduction in defect density along the trench orientation is original and obviously confirm the potential of this heterogeneous integration option for high mobility logic devices, and photonic applications on a common Si platform.

The low-frequency noise is studied in planar InGaAs channel nMOSFETs, with Al2O3 gate dielectric in combination with different pre- and post-gate treatments, namely, pre-gate TMA exposure or post-gate Forming Gas Annealing (FGA). It is shown that the oxide trap density is reasonably uniform in the gate stack between 1 and 2 nm from the interface, whereby a FGA yields a lower noise power spectral density compared with the TMA or untreated devices.

The electrical activity of a defect in a semiconductor material is usually expressed in terms of the Shockley-Read-Hall (SRH) theory which provides an expression for the generation or recombination lifetime. Along the same lines, one can calculate the leakage current generated by a single defect in the depletion region of a junction, as shown in Fig. 1 [1]. It is clear that for III-V based ternary alloys, like the InxGa1-xAs system, the generation current depends proportionally on the intrinsic carrier concentration ni (see equation in Fig. 1). However, equally important is also the variation of the defect energy level ET as a function of the In content x: for ET pinned to the intrinsic Fermi level Ei(x), the leakage current will follow ni. On the other hand, when ET is pinned to either the valence or conduction band, the leakage current will decrease exponentially with the difference |ET-Ei| [2]. It is thus important to derive the variation of ET with alloy composition x for a certain type of defect and to establish what could be consideredas a kind of Vegard’s law for specific deep levels. In addition, when integrating III-V compounds on a silicon CMOS platform, extended defects will be inevitably introduced [3]; for a sufficiently high density, they will govern the reverse current [3,4]. It is thus of vital importance to study the electrical parameters of extended defects in III-V-on-silicon materials and their evolution with composition x. The aim of the this work is to review what is known about the electrical activity of extended defects in InxGa1-xAs-based hetero-epitaxial layers. Results will be described about a combined p-n diode current-voltage (I-V) and lifetime analysis on a set of nearly strain-free layers where x=0.53 with varying densities of extended defects [5]. Based on this, it is demonstrated that for an extended defect density exceeding ~2×107 cm-2 the SRH lifetime becomes dominated by a near mid-gap trap level, associated with them. A detailed Deep-Level Transient Spectroscopy (DLTS) analysis provides further information about the electrical activity of these extended defects and confirms the presence of a dominant electron trap. The corresponding activation energy is represented in Fig. 2 versus x and compared with available literature data. In addition, it is shown that this deep level indeed belongs to an extended defect, based on the electron capture behavior, varying approximately logarithmically with the capture time [4]. Moreover, it can be shown that the electron traps belong to a one-dimensional band-of-states, associated with a ‘perfect’ extended defect. According to Fig. 2, this level appears to follow approximately Ei(x), so that it will dominate the leakage current of a p-n junction over a wide composition range, at least up to 0.53, when present in a sufficient density. Moreover, the defects will become more efficient leakage centers for increasing x. Finally, the implications of the band-like nature of the energy states of extended defects on the carrier generation/recombination will be discussed. [1] J. Vanhellemont and E. Simoen, J. Electrochem. Soc, 154, H572 (2007). [2] E. Simoen, J. Lauwaert and H. Vrielinck, Semiconductors and Semimetals, Eds. L. Romano, V. Privitera and C. Jagadish, 91, pp. 205-250, Elsevier 2015. [3] E. Simoen, “Impact of defects on the performance of high-mobility semiconductor devices”, In: High Mobility Materials for CMOS Applications, Ed. N. Collaert, Elsevier, Ch. 5, July 2018. [4] C. Claeys et al., ECS J. Solid State Sci. and Technol., 5, P3149 (2016). [5] P.-C. Hsu et al., J. Appl. Phys., 124, 165707 (2018). Figure 1

Deep levels associated with extended and point defects in MOS capacitors fabricated on unintentionally doped GeSn epitaxial layers on Ge-on-Si substrates have been studied by Deep Level Transient Spectroscopy (DLTS). A 9nm layer of Al2O3 is deposited as high-k gate dielectric by Molecular Beam Epitaxy. The trap kinetics and origin of defect states is discussed. Also, it is shown that the dislocation cores in relaxed p-Ge are associated with band-like donor-like states in the lower half of forbidden band gap, and act as carrier trapping and recombination centers. In addition, slow and fast oxide interface traps are observed.

The effective passivation of germanium surfaces and interfaces has been claimed to be the key to a substantial progress in developing Ge-based microelectronic devices. This paper compares the currently most promising passivation routes, i.e. oxidation and sulfidation, focusing on the underlying atomic scale processes and highlighting similarities and discrepancies between both approaches. The effect of oxidation and sulfidation on electrically active defects is addressed, and the chemical and structural properties of the passivated surfaces are described in detail.

As post-Si era for digital device is incipient, In0.53Ga0.47As is good candidate among n-type active channels with high electron mobility but - unlike Si - it lacks a well-established technology for dielectric gating which may bear aggressive device scaling. Here we propose a viable route for the atomic layer deposition (ALD) of high-κ dielectrics taking advantage from the well-known self-cleaning effect of the trimethylaluminum (TMA) precursor on the III-V compound surfaces. In this respect, the incorporation of Al2O3 cycles both as pre-conditioning surface treatment and inside the ALD growth of a MO2 host matrix (M=Zr, Hf) is here investigated. Al:MO2/In0.53Ga0.47As heterojunctions have been scrutinized by in situ spectroscopic ellipsometry and ex situ chemical depth-profiling analysis which validate a good physical quality of the oxide and elucidate the effect of the pre-conditioning cycles at the interface level. The resulting MOS capacitors have been characterized by means of multifrequency capacitance-voltage measurements and conductance analysis therein yielding a permittivity of 19{plus minus}1 both for Al:HfO2 and Al:ZrO2 and similar electrical quality of the interfaces. On the other hand, Al:HfO2 appears to be electrically more robust against leakage and endowed with a lower frequency dispersion in accumulation.

We report two approaches to integrate high quality III-V templates with low defectivity on Si wafers by epitaxial growth. The first approach is based on blanket, InGaAs-based Strain Relaxed Buffers grown by MOVPE on 200mm Si, and the second on the selective area MOVPE of InP in Shallow Trench Isolation structures patterned on 300mm Si. Both structures are characterized structurally and show the efficient trapping and annihilation of defects propagating from the Si/III-V interface. We believe these two approaches represent viable alternatives towards the realization of CMOS-compatible III-V templates and stacks for high-performance devices monolithically integrated on Si.

Deep levels present in MOS capacitors, fabricated on GeSn epitaxial layers on Ge-on-Si substrates have been studied by Deep-Level Transient Spectroscopy (DLTS). The gate dielectric is composed of 9 nm Al2O3 deposited by Molecular Beam Epitaxy (MBE) on two different types of Interfacial Oxide Layers (IOL). It is shown that the density of interface traps (Dit) near the valence band edge is significantly reduced for GeSn epilayers compared with the same gate stack on a Ge cap. At the same time, several deep-level traps in the germanium depletion region have been observed, whereof the origin is discussed.

Si CMOS technology is currently changing with the introduction of strain and new materials (Ge, III/V) to increase carrier mobility and devicesaturationcurrent.Recently,excellentGe-basedpMOSchannel performance has been demonstrated with intrinsic hole mobilities far above the universal Si mobility curve which is reflected in a clear increase in device current. 1‐4 However, while relaxed Ge exhibits significantly higher intrinsic hole mobilities than relaxed Si, it does not out-perform the current “state of the art” uniaxially strained Si pMOS devices. For Ge channel pMOS devices, compressive uni-axial and/or bi-axial strain implementation seems essential to substantially increase carriers velocity and to outperform current Si- and Si1-yGeybased devices, which is confirmed by theoretical calculations of the carrier mobility and device current. 5‐7 Ge1-xSnx offers schemes to implement the required strain types and levels in the active part of the device. Recent breakthroughs in low temperature hetero-epitaxial Ge1-xSnx and SiyGe1-x-ySnx growth on Si substrates as e.g. reported in references 8‐14 have triggered the assessment of this material system for such electrical device applications. In this contribution we discuss the use of Ge1-xSnx for future (electrical) device applications and its fabrication with a special attention on recent achievements from imec.

We report on the fabrication on InGaAs/InP implant free quantum well (IFQW) n-MOSFET devices on 200mm wafers in a Si CMOS processing environment. The starting virtual InP substrates were prepared by means of the aspect-ratio-trapping technique. Post CMP these substrate resulted in a planar substrate with a rms roughness of 0.32 nm. After channel and gate processing source drain regions were formed by the selective epitaxial growth of Si doped InGaAs. Contact to the source/drain regions was made by a standard W-plug/metal 1 process. The contact resistance was estimated to be on the order of 7x10-7 Ω.cm2. Fully processed devices clearly showed gate modulation albeit on top of high levels of source to drain leakage. The source of this leakage was determined to be the result of the unintentional background doping of the InP buffer layer. Simulations show that the inclusion of the p-InAlAs between the InP and InGaAs can effectively suppress this leakage. This work is a significant step towards the integration of InGaAs based devices on a standard CMOS platform.

The semiconductor ICT industry continues its neverending pursuit of new approaches for fabricating integrated circuits to reduce device cost and improve device performance. For future device generations, many different approaches are considered, for which the efficient engineering of new materials and architectures are the main challenge to improve device performance. InP is one of these new materials, which is considered to be used as virtual substrate for III-V based nMOS devices.

We discuss the selective epitaxial growth of InP on patterned Si (001) substrates with Shallow Trench Isolation using a thin Ge buffer to facilitate InP nucleation. The main focus is the defect formation mechanism during epitaxial growth and to develop solutions to reduce defect density so that device-quality III-V virtual substrates can be realized on large-scale Si substrates. We compare the InP growth on on-axis and off-axis Si substrates. In the case of off-axis wafers, the formation of stacking faults / twins cannot be avoided, at least not at one of the four STI side-walls. The formation of antiphase domain boundaries is reduced (but not yet completely eliminated) by engineering the local Ge surface profile. Further, the high density of Ge surface steps promotes step-flow growth mode instead of 3D growth during the growth of the InP seed layer. Finally, high aspect ratios (>2) allow to confine threading dislocations in the bottom of the trench.

The integration of high carrier mobility materials into future CMOS generations is presently being studied in order to increase drive current capability and to decrease power consumption in future generation CMOS devices. If III-V materials are the candidates of choice for n-type channel devices, antimonide-based semiconductors present high hole mobility and could be used for p-type channel for quantum well devices. In this work we first investigated building blocks such as passivation and contact resistances on both GaSb and InAs epilayer in order to define the optimal heterostructure for the quantum well device. In a second part, we focused on the growth studies of the complex heterostructure made with "6.1" semiconductors as well as the importance of the interface engineering with TEM. Finally, the properties of the optimized quantum well stack have been studied by means of photoluminescence and high resolution X-ray diffraction.

Three advanced architectures for ultimate progress in Ge p-Metal Oxide Semiconductor Field Effect Transistors are discussed in this paper. Different routes for stress implementations in Ge channels, either biaxial or uniaxial, are proposed by advanced selective Chemical Vapor Deposition techniques. Selective SiGe Strained Relaxed Buffer growth in Shallow Trench Isolation is first discussed to implement biaxial compressive strained Ge Quantum Wells on top of it. Next, innovative GeSn chemical vapor deposition technique is described in order to build either uniaxial strained Ge channel with GeSn Source/Drain stressors or compressively biaxial strained GeSn Quantum Well channels on Ge buffer layers.

CMOS scaling for sub-12 nm nodes will need high-mobility channel semiconductors such as III-V materials to be integrated on large diameter Si substrates. A way to overcome lattice mismatch is to confine defects resulting from strain relaxation on the sidewalls of trenches made by etch-back of Si in standard Shallow-Trench-Isolation (STI) structures. The surface of the InP layers, grown as buffer material in these trenches by selective epitaxy, is planarized by means of CMP, after which it needs to be recessed to allow for the deposition of the III-V channel stack. We have developed an in-situ HCl etching process allowing a close control of the recess depth down to a few nm and leaving a clean and planar InP surface well suited for subsequent III-V epitaxial growth. The process development was carried out in a commercial Aixtron Crius MOCVD reactor on standard SiO2 STI patterned 200 mm Si (001) wafers.

We will present the defect density at In0.53Ga0.47As and InP interfaces with ALD Al2O3 derived by use of the conductance method and from simulation of low frequency CV-curves. Consequences of the interface state distribution for MOS transistor device operation will be highlighted through 1-dimensional electrostatic simulations. The simulation results will be compared as much as possible to different state-of-the-art transistor results presented in literature.

The use of Ge and III/V materials for future CMOS applications is investigated. Passivation of the Ge surface can be obtained by either GeO2 or a thin Si layer. Short channel Ge pMOS devices with low EOT are fabricated. The passivation of III/V materials is a very challenging topic. Some critical issues and passivation schemes are investigated and the performance of inversion channel MOSFET's on In0.53Ga0.47As with ALD Al2O3 is discussed.

Different selective epitaxial growth processes to deposit buried SiGe channels with Ge contents in the range of 25-55% and with an ultra thin Si capping layer have been successfully developed and implemented in pMOS device flows. Relatively low deposition temperatures assure the absence of SiGe islands and enable high quality strained SiGe layers. The required low growth temperature governed the choice of precursors used. In this contribution we review in detail the developed SiGe processes together with the deposition of the ultra thin Si cap layer. Electrical data obtained on the devices with incorporated Si0.75Ge0.25 and Si0.55Ge0.45 buried channels are presented as well.

We will shortly review the basic physics of charge carrier trapping and emission from trapping states within the bandgap of a semiconductor in order to show that high temperature CV-measurements are necessary for GaAs MOS characterization. The mid-gap trapping states in GaAs have characteristic emission times of the order of 1000 seconds, which makes them extremely complicated to measure at room temperature. Higher substrate temperatures fasten these emission times, which makes measurements of the mid-gap traps possible with standard CV-measurements. CV-characterizations of GaAs/Al2O3, GaAs/Gd2O3, GaAs/HfO2 and In0.15Ga0.85As/Al2O3 interfaces show the existence of four interface state peaks, independent of the gate oxide deposited: a hole trap peak close to the valence band, a hole trap peak close to mid-gap energies, an electron trap peak close to mid-gap energies and an electron trap peak close to the conduction band.

Since the advent of non-planar metal-oxide-semiconductor (MOS) transistors, embodied by the three-dimensional fin field-effect transistors (finFETs), there has been a rising need for fast in-line metrology solutions for the electrical characterization of nanometer-wide trenches filled with semiconducting materials. Indeed, on such narrow structures, conventional four point probe fails, mostly due to the challenging alignment of the four millimeter-sized and -spaced probes to the nanoscale trenches. Subsequently, at the expense of extra processing cost and time, the electrical characterization of these state-of-the-art devices is now performed at metal-1 on fins connected by metal contacts in Kelvin resistor or transmission line structures [1]. However, a very promising technique to solve the need for electrical resistance measurements of narrow fins without the need for metal contacts is the micro four-point probe. This four-point probe technique where the probes and probe distance have been downscaled to a few micrometer size has been successfully applied to a myriad of blanket materials, ranging from multilayered metal stacks [2] to semiconductors [3], two-dimensional materials [4] and even single nanowires [5]. Advantageously, micro-probes have allowed a smaller sampling volume and a minimized sensitivity to junction leakage in blanket samples [6] but they are also much easier to align to nanoscale trenches. In this contribution, we evaluate the capabilities of micro four-point probe, as implemented in the fully automatic microHALL®-A300 tool of CAPRES A/S, for the in-line resistance measurement of single oxide-isolated nanoscale fin-like structures. We start by showing that this tool is capable of contacting the four probes with single fins with widths down to 20 nm, i.e. three orders of magnitude smaller than the total 24 μm distance between the two outermost pins. Next, we investigate the measured resistance values to evaluate whether the measured resistance values can be correctly attributed to the semiconducting material located inside the trench. Many parasitic conduction paths could indeed still lead to the underestimation of the actual resistance of these narrow features. In this paper, we evaluate how to minimize the possible contribution of the two most probable parasitic resistances. First of all, we consider the contribution of multiple fins which could be contacted in parallel when the distance between two consecutive fins is shorter than the size of the probe contacts. To minimize this first contribution, we use atomic force microscopy (AFM) to measure the lateral extent of the probe imprints and only focus on arrays where the fin distance is larger than the imprint. Second and most important of all, for very high fin resistances (e.g. narrow fins made of lowly doped material), current may significantly leak into the substrate [2,6]. This second contribution is investigated in two different manners. Since the impact of such parasitic resistances rises as the feature width decreases, we study the resistance-to-width correlation in fins with widths ranging from 20 nm to 10 μm. Also we investigate the resistances measured in the different available configurations (A, B and C) as their ratio offers valuable information on the dimensionality of the current path (one-dimensional in the trench and two-dimensional in the substrate) [4]. Our study concludes on recommendations targeting the accurate resistance measurement of sub-50-nm fins. [1] D. K. Schroder, Semiconductor material and device characterization, 3rd ed., Chap I, Wiley-Interscience (2006) [2] D.C. Worledge et al., Appl. Phys. Lett. 83, 84 (2003) ; D. Kjaer, et al., Meas. Sci. Technol. 26, 045602 (2015). [3] D. H. Petersen et al., J. Vac. Sci. Technol. B 28, C1C27 (2010); T. Clarysse, et al., Mater. Sci. and Eng. B 154, 24 (2008); T. Clarysse et al., J. Vac. Sci. Technol. B 28, C1C8 (2010) [4] J.D. Buron, et al., Nano Lett. 12, 5074 (2012); J.D. Buron, et al., Nano Lett. 14, 6348 (2014). [5] R. Lin, et al., Nanotechnology 15, 1363 (2004) ; [6] R. Lin et al., AIP Conf. Proceedings 1496, 175-178 (2012); C.L. Petersen, et al., RTP 2006 (IEEE NY, 2006), 153-157; T. Clarysse et al., Mater. Res. Soc. Symp. Proc. 912, 197 (2006).

Driven by fabrication cost reduction and device performance improvement, the Silicon semiconductor industry continues its never-ending pursuit of new approaches for fabricating integrated circuits. In this context, the monolithic integration of III-V semiconductors epitaxially grown on Si substrate have been attracting much attention as building blocks for next-generation electronics and photonics due to their potential intrinsic properties. Direct heteroepitaxy of III-V compound semiconductors on Si has traditionally represented a formidable challenge, due to the high material mismatch (lattice parameter, polarity, thermal coefficient, ...) between Si and III-V semiconductors generating high density of defect density during the epitaxial process. To overcome this, selective area growth of III-Vs in a pre-patterned Si substrate by Selective Area Metal-Organic Vapor Phase Epitaxy allow the possibility to obtain high quality and reduced defect density III-V based active layers onto standard Si(001) substrate. Using this approach we integrate III-V materials monolithically on Si while focusing on both ultimate trench widths (W < 20 nm) scaling as well as relaxed trench dimension in function of the targeted application. We report here on the heteroepitaxy of InP buffer on initiated from a V-groove Si surface and discuss the unique relaxation mechanism of such compound with respect to Si substrate. We derived a fundamental understanding and theoretical modeling of the growth mechanisms in STI trenches as well as the determining role of the InP nucleation layer. The subsequent growth approach of InGaAs active layer, used for both nFET or Laser applications, is further studied. Finally, III-V based electronic and photonic devices realized using selective area growth technique are presented and benchmarked to the current state of the art.

Due to energy-filtering by band-to-band quantum mechanical carrier tunneling, Tunnel FETs promise the possibility of steeper subthreshold swings (SS < 60 mV/dec) than MOSFETs. Even if the ideal material combination is still unclear, simulations show that for a confined channel (width We first present the pseudomorphic growth of n+InAs(Si)-p+GaSb(Si) Esaki diode on a (001) p+ GaSb substrate (ED1). We particularly show the influence of the InAs/GaSb interface nature on both structural and electrical quality. After choosing the right interface stoichiometry between InAs and GaSb, the growth of n+InAs(Si)-p+GaSb(Si) Esaki diode on GaAs is investigated (ED2). In here, 90° misfit dislocations (MDs) array at the GaSb/GaAs interface is used to accommodate the mismatch strain between GaSb and GaAs. After presenting the influence of the growth conditions on the MDs array formation, the electrical results of ED2 are compared to the ones of ED1. This learning is crucial to study the effect of dislocations on BTBT behavior in tunneling devices. In the last step, the integration of n+InAs(Si)-p+GaSb(Si) Esaki diode on (001) Si is presented (ED3) using a 300 mm GaAs on Si template grown by MOCVD. After presenting the detailed growth stack, we demonstrate a high quality n+InAs(Si)-p+GaSb(Si) growth on exactly oriented (001) Si substrate exhibiting a RMS surface roughness of 1.4 nm and a dislocation density (TD) of 9x107/cm2 , as determined by XRD analysis. In summary, this study gives a broad insight on the influence of different types of defects on the tunneling current. We demonstrate that this learning is crucial for the integration of TFETs onto large area commercial Si substrates.

With the growing need to pack more functionality into a smaller form-factor while providing significant power-performance benefits, future electronics will need fairly disruptive solutions to overcome the mounting limits of Si CMOS scaling. At the core of the hardware innovations will be new process technologies that not allow for more power-efficient CMOS transistors but also specialized devices to enable new on-chip functionality, E.g. Near-Threshold Logic, High-speed I/O, Optoelectronics, etc. Heterogeneous integration ranging from TSV-based chip stacking to monolithic 3-D integration are active areas of R&D with the common aim to enhanced chip density and functionality. In order to leverage the dense Si CMOS logic and memory fabric, most, if not all approaches also require the integration to be compatible, to different extent, with large-scale 300mm CMOS processes, and potentially >300mm wafers, in the future. At the finest grain, co-integration of different beyond-Si crystalline material (E.g. III-V, Ge, SiGe, etc.) with Si require significant innovations in defect, stress, and process thermal-budget management. With the maturation of epitaxy process technology, the ability to combine materials of large lattice mismatch is becoming possible with lowering defectivity. Through defect engineering, we will soon have options to integrate IIIV and Ge-based material on Si at different scale, from global wafer level to fine-grain local levels of the order of circuits and devices (Figs. 1 and 2). This opens up possibilities to integrate heterogeneous devices that leverage the unique properties offered by epitaxial combination of materials. Besides high-channel carrier mobility, integrating compound semiconductors heterostructures into multi-gated nano-devices like FinFETs (Fig. 3) combines Fin structural confinement with quantum well confinement enhancing the electrostatics of FinFET structures (Fig. 4). Due to the intrinsic lower band-gap of high-mobility channels (InGaAs, Ge, etc.), which leads to increase band-to-band tunneling leakage, there may be a need to co-integrate wider band-gap devices to address the low-leakage components (Eg. Low-standby leakage circuits, High-density SRAM, etc.) at the system level. Hence, a method of integrating different channel materials on the same die is called for. With the flexibility to direct heteroepitaxy on Si, the possibility to build hybrid systems of novel devices and MOSFETs become real. For example for an ultra-low Vdd Tunnel-FET (for ultra-low Vdd logic) process may be achieved by a grow-and-etch approach or by an epitaxy replacement process on Si. For example, with source replacement, asymmetric vertical device structures can be integrated in the form of TFETs (Fig. 7). Polarity and performance of TFETs can be selectively modulated by the source material replacement process (Fig. 8). The mix and match of different devices and circuits will need careful considerations of circuit layouts, which bring new parasitic factors (Fig. 9) which will need to be overcome. Extending beyond integration of 3-D semiconductors, further heterogeneity with emerging materials like 2-D Transition metal dichalcogenides crystals and spintronics offer even richer possibilities for future on-a-chip electronic systems. This paper will look into the materials, process, device and circuit considerations to enable monolithically-integrated heterogeneous materials, devices, and systems. Figure 1

Introduction III-V fin-shaped field-effect transistors (FinFETs) are considered to be attractive candidates for high-performance n-type FETs, thanks to both the light electron effective mass and to the improved electrostatic control. III-V FinFETs integrated on a Si substrate are advantageous with respect to their cost effectiveness. Aspect Ratio Trapping (ART) is one of the possible integration roads to be followed to achieve the growth of non-silicon channels on a Si substrate by reducing the density of defects obtained in the filled trenches [1]. In the ART process, the III-V fin is grown inside trenches of SiO2by using a metal organic vapor phase epitaxy (MOVPE) process, which implies that the precursors interact not only with the semiconductors but also with the oxides. The reaction of the precursors with the oxides could lead to the formation of defects around the interface which could be responsible for the degradation of the electrical reliability of III-V FinFETs. In this study, we report the evaluation of the formation of defects due to the reactions between the precursors and the oxides using first-principles simulations. Methodology The formation enthalpies [2] of the defects are calculated using the Quantum Espresso package [3] based on density functional theory. The lower the formation enthalpy is, the more likely the reaction is to occur. We used the Perdue-Burke-Ernzerhof exchange-correlation potential [4] combined with ultrasoft pseudopotentials to compute the energetics of the reactions. The charge states of the defects are assumed to be neutral. One of the considered reactions consists into the formation of interstitial defects in SiO2 due to the diffusion of the III-V components and of the doping atoms from the precursors. The list of considered precursors and oxides are summarized in Table 1. Mg and Zn could be used as acceptor doping sources for the III-V compounds. For the SiO2, an amorphous model is used, built from classical molecular dynamics simulations with the LAMMPS package [5]. Results and Discussion Fig. 1 shows the calculated formation enthalpies. For the precursors, we also envisaged some intermediate atomic configurations that correspond to the transition products active during the MOVPE process. Our simulations show that the initial states of the precursors have high formation enthalpies, indicating that there is no driving force to promote the diffusions of the III-V elements and of the dopants into the STI. However, as the growth proceeds and that the precursors begin losing their organic ligands, the formation enthalpies are significantly reduced. Zn and Mg have the lowest formation enthalpies of all of the reactants considered, which suggests that the diffusion of doping sources into SiO2 could be favored. In order to confirm the latter for the Mg case, secondary ion mass spectrometry measurements (SIMS) were performed on a SiO2 blanket exposed to the Mg-precursors (see Fig. 2). The diffusion of Mg is clearly observed near the SiO2surface, which is consistent with the theoretical picture (Fig. 1). In order to prevent these defect-related issues, it will be important to understand a risk of formation of defects using the ab initio approaches. Acknowledgment This work has been supported by the IMEC core partners and IMEC Industrial Affiliation Programs (IIAP). References [1] C. Merckling et al., J. Appl. Phys. 115, 023710 (2014). [2] C. G. Van de Walle et al., J. Appl. Phys. 95, 3851 (2004). [3] P. Gianozzi et al., J. Phys.: Condens. Matter 21, 395502 (2009). [4] J. P. Perdew et al., Phys. Rev. Lett. 77, 3865 (1996). [5] S. Plimpton, J. Comp. Phys. 117, 1 (1995).

The integration of III/V materials onto Si substrates is of significant interests for microelectronic and optoelectronic applications. The utilization of the selective epitaxial growth (SEG) on patterned Si substrates by metalorganic vapor phase epitaxy (MOVPE) is proved as a valuable solution for the heteroepitaxy of III-V semiconductors on Si thanks to the “defect trapping” by sidewalls. The demonstration of successful integration by the SEG in wide trenches (above 100nm) is extensively available in the literatures.[1-6] However, following scaling rules for Logic CMOS devices, new challenges are imposed on the heteroepitaxy inside nano-scaled trenches (i.e. sub-50nm trenches for FinFET devices). Therefore, in this study, the influence of trench width on nucleation behavior based on InP SEG in “V-groove” trenches[7,8] as an example, is discussed and analyzed via the proposal of a nucleation model according to the ex-situ morphology observation in the experiments. The evolution of morphology for the selective growth of InP in submicron “V-groove” trenches on on-axis Si(001) substrates is characterized by SEM and AFM. Due to the high lattice mismatch between InP and Si, the typical evolution of 3D islands growth mode in both wide and narrow trenches is identified. The comparison of nominally 40nm to both 150nm and 500nm wide trenches indicates that there is an evolution lag for islands coalescence in narrower trenches. This is the reason for discontinuous topology and highly defective layers obtained in sub-50nm trenches. We believe that one possible mechanism attributing to this lag is induced by greater inter-island distance in narrower trenches. Therefore, we propose a nucleation model to evaluate the influence of trench width on the inter-island distance, suggesting that the scaling relationship between the critical inter-island distance and trench width is theoretically predicted as L* ~W-1/(2i*+4) if W≤2L*in the surface-diffusion limited regime. This understanding is of critical importance for the uniform growth inside nano-trenches for the heteroepitaxy of mismatched III/V compounds onto Si substrates, where the 3D island growth mode dominates in most cases. ACKNOWLEDGMENTS This work is supported by IMEC Industrial Affiliation Program. The present authors would like to thank the Logic Program and Management, partners. References 1 W.J. Choi and P. Daniel Dapkus, J. Cryst. Growth 195, 495 (1998). 2 G. Wang, M.R. Leys, N.D. Nguyen, R. Loo, G. Brammertz, O. Richard, H. Bender, J. Dekoster, M. Meuris, M.M. Heyns, and M. Caymax, J. Electrochem. Soc. 157, H1023 (2010). 3J.Z. Li, J. Bai, J.M.Hydrick, J.G. Fiorenza, C.Major, M. Carroll, Z. Shellenbarger and A. Lochtefeld, ECS Trans. (2009), pp. 887–894. 4 C. Merckling, N. Waldron, S. Jiang, W. Guo, O. Richard, B. Douhard, a. Moussa, D. Vanhaeren, H. Bender, N. Collaert, M. Heyns, a. Thean, M. Caymax, and W. Vandervorst, J. Appl. Phys. 114, 033708 (2013). 5 S. F. Cheng, L. Gao, R. L. Woo, a. Pangan, G. Malouf, M.S. Goorsky, K.L. Wang, and R.F. Hicks, J. Cryst. Growth 310, 562 (2008). 6 Y. Dong, Y.L. Okuno, and U.K. Mishra, J. Cryst. Growth 260, 316 (2004). 7M. Paladugu, C. Merckling, R. Loo, O. Richard, H. Bender, J. Dekoster, W. Vandervorst, M. Caymax, and M. Heyns, Cryst. Growth Des.12(10), 4696 (2012). 8 C. Merckling, N. Waldron, S. Jiang, W. Guo, N. Collaert, M. Caymax, E. Vancoille, K. Barla, a. Thean, M. Heyns, and W. Vandervorst, J. Appl. Phys. 115, 023710 (2014).

GeSn has emerged as an interesting channel material for beyond 14 nm node devices, in CMOS as well as TFET configurations [1-3]. However, the advantages of sub-60mV/decade subthreshold swing (SS) due to the increased band to band tunneling in small direct-bandgap tensile-strained GeSn and higher carrier mobilities are dwarfed by the presence of traps in the gate stack. For GeSn devices, Al or Hf based high-k dielectrics have been recognized as candidates for advanced gate stacks [4-6], where the presence of the interlayer oxide (IL) has shown to decrease the interface state density, Dit [7]. However, the border traps, known to be present in the vicinity of the GeSn/Oxide interface within a few nm, can exchange charge carriers with the underlying GeSn epitaxial layer via direct tunneling of injected charge, [8-9] thus reducing the mobility and increasing SS. A detailed characterization of these border traps has not been reported so far for GeSn gate stacks. In this work, two techniques, Fourier transform deep level transient spectroscopy (FT-DLTS) and temperature derivative admittance spectroscopy (TDAS) have been used to investigate the distribution of border traps in GeSn MOS capacitors. A 40 nm nominally thick compressively strained, un-intentionally doped Ge0.092Sn0.08 layer is grown using chemical vapor deposition on a thick Ge buffer layer on Si. The GeSn surface is baked at 5000C for 30 min to remove native oxide. A complete de-oxidation is confirmed by RHEED analysis. Plasma oxidation at 1500C is then carried out for 1 nm of GeSnOx IL formation, followed by 9 nm of Al2O3 deposition at -500C. Ni dots are deposited for gate contact, followed by forming gas anneal. A broad peak at higher temperatures (~235 K) was observed in conventional FT-DLTS measurements, when MOS capacitors are pulsed from depletion (Ur=2V) to accumulation (Up=-1.5V) as shown in Figure 1a. This peak originates from traps present at the oxide interface and is absent when the device is pulsed from deep depletion to depletion (positive pulse bias). The peak corresponds to a maximum in energetic distribution of border traps, found to be present at (ΔEa = 0.36± 0.02 eV) from the valence band edge (figure 1b). The capture kinetics is studied by means of pulse filling measurement using isothermal DLTS, which exhibits an s-shaped profile. A capture cross-section, σp of ~5e-17 /cm2 is estimated. With an assumption of all states being unoccupied or occupied at the beginning of the trap filling process, the density of border trap, the tunneling depth of the traps in the oxide and the trap energy are determined. Similar results are obtained for Al2O3/GeO2/GeSn capacitors. Figure 1: (a) Conventional FT-DLTS Spectrum at quiescent reverse bias (Ur) of 2 V, trap filling pulse duration (Tp) of 100 µs, emission period width (Tw) of 51.2 ms and varying filling pulse amplitude(Up). The solid curve shows de-convoluted peaks with a Gaussian distribution for the curve corresponding to Up = -1 V. The peak at ~235K corresponds to border traps with a background distribution. The peaks at lower temperature represent bulk traps in GeSn/Ge epitaxial layers[10]. (b) Temperature derivative Admittance spectrum [11], at gate bias(Vg) of -1V. An Arrhenius plot of ln(ωpeak/T2) vs 1/kT is used to obtain activation energy of 0.36 eV from the valence band edge where ωpeak is the frequency at peak position and k is the Boltzmann constant. In conclusion, FT-DLTS and TDAS of MOS capacitors on GeSn epitaxial layers are used to study the frequency and temperature dispersion observed in the accumulation region of capacitance curves. The results are described by means of the assumption of spatially and energetically distributed states, present in the depth of the oxide which interact by tunneling and thermally activated transitions of carriers. [1] S. Wirths et al., Appl. Phys. Lett. 102, 192103(2013). [2] S. Gupta et al., VLSI Technology (VLSIT), 2012 Symposium on. IEEE, 2012. [3] Y. Yang et al., Electron Devices Meeting (IEDM), 2012 IEEE International. IEEE, 2012. [4] Y. Yang et al., Electron Devices, IEEE Transactions on 60.12 (2013): 4048-4056. [5] S. Gupta et al., Electron Devices Meeting (IEDM), 2012 IEEE International. IEEE, 2012. [6] X. Gong et al., VLSI Technology (VLSIT), 2012 Symposium on. IEEE, 2012. [7] M. Zhao et al., Appl. Phys. Lett., APL 102.14 (2013): 142906. [8] H. D. Lakhdari et al., Physical Review B, 38.18 (1988): 13124. [9] P. Van Staa et al., J. Appl. Phys., JAP 54.7 (1983): 4014-4021. [10] S. Gupta et al., ECS Transactions 53.1 (2013): 251-258. [11] V. Jian Li et al., J. Appl. Phys., JAP 109.8 (2011): 083701.

Driven by fabrication cost reduction and device performance improvement, the Silicon semiconductor industry continues its never-ending pursuit of new approaches for fabricating integrated circuits. The heterogeneous integration of III-V high mobility semiconductors on a silicon platform in a 3D architecture such as Fin-Field-Effect-Transistor is a winning combination to further boost the performance of future CMOS devices. Direct heteroepitaxy of III-V compound semiconductors on Si has traditionally represented a formidable challenge, due to the extensive lattice mismatch of 8% between the Si substrate and high mobility III-V compounds, such as In0.53Ga0.47As/InP heterostructure. The defect confinement technique has recently attracted great interest due to the possibility of obtaining high quality III-V based active layers on Si. Using this approach we integrate III-V materials monolithically on Si through the epitaxial growth of III-V materials into a pre-patterned structure by Selective Area Metal-Organic Vapor Phase Epitaxy. We report here on the growth of InP on STI patterned Si wafers using the defect confinement technique while focusing on scaled trench widths (W < 50 nm). We demonstrate the impact of the crystalline alignment of the InP layer with the underlying substrate by exploring as starting geometry at the bottom in between the STI either a rounded etch pit covered with a Ge buffer layer versus a crystalline V-groove structure in Si. We show the large impact of the main layer growth temperature and the growth pressure on the trench filling, the growth uniformity and the crystal quality which we could correlate with changes in resistivity and the presence of impurity diffusion in the III-V layer. Moreover, we derived a fundamental understanding and theoretical modeling of the growth mechanisms in STI trenches and the determining role of the nucleation layer. This lead to a strong enhancement of the crystalline quality and growth uniformity of the InP semiconductor. As a conclusion, this study of the InP selective area growth brings some elements for the optimization of the heteroepitaxy of III-V compounds on patterned Si substrates. The demonstration of a clear reduction in defect density along the trench orientation is an original achievement and confirms the potential of heterogeneous integration approach on a common Si platform.

Driven by fabrication cost reduction and device performance improvement, the Silicon semiconductor industry continues its never-ending pursuit of new approaches for fabricating integrated circuits. The heterogeneous integration of III-V high mobility semiconductors on a silicon platform in a 3D architecture such as Fin-Field-Effect-Transistor (FinFET) is a winning combination to further boost the performance of future CMOS devices. Direct heteroepitaxy of III-V compound semiconductors on Si has traditionally represented a formidable challenge, due to the extensive lattice mismatch of 8% between the Si substrate and high mobility III-V compounds, such as In0.53Ga0.47As/InP heterostructure. The defect confinement technique has recently attracted great interest due to the possibility of obtaining high quality III-V based active regions, using nanometer scale trenches with high aspect ratio (>3) in order to eliminate (111)-oriented defects (such as threading dislocations, twins or stacking faults) on the sidewalls. Using this approach we integrate III-V materials monolithically on Si through the epitaxial growth of III-V materials into a pre-patterned structure by Selective Area Metal-Organic Vapor Phase Epitaxy (SA-MOVPE). Silicon 300mm wafers substrates patterned with ~300nm deep Shallow Trench Isolation (STI) structures are used with trenches having typical widths ranging from 500 nm down to ~20nm. We report here on the SA-MOVPE growth of InP on STI patterned Si wafers using the defect confinement technique while focusing on scaled trench widths (W < 50 nm). We demonstrate the impact of the crystalline alignment of the InP layer with the underlying substrate by exploring as starting geometry at the bottom in between the STI either a rounded etch pit covered with a Ge buffer layer versus a crystalline V-groove structure in Si. The structures are fully characterized by Scanning and Transmission Electron Microscopy, Atomic Force Microscopy, X-Ray Diffraction, Secondary Ion Mass Spectroscopy and Scanning Spreading Resistance Microscopy. We demonstrate the dependence of the material quality and trench filling upon different sets of growth conditions. We show the large impact of the main layer growth temperature and the growth pressure on the trench filling, the growth uniformity and the crystal quality which we could correlate with changes in resistivity and the presence of impurity diffusion in the III-V layer. Moreover, we derived a fundamental understanding and theoretical modeling of the growth mechanisms in STI trenches and the determining role of the nucleation layer. This lead to a strong enhancement of the crystalline quality and growth uniformity of the InP semiconductor. As a conclusion, this study of the InP selective area growth brings some elements for the optimization of the heteroepitaxy of III-V compounds on patterned Si substrates. The demonstration of a clear reduction in defect density along the trench orientation is an original achievement and confirms the potential of heterogeneous integration approach for advanced III-V based logic devices or III-V based photonic applications on a common Si platform.

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Deep Level Transient Spectroscopy (DLTS) has been applied to MOS capacitors (MOSCAPs) fabricated on n- and p-type GaAs and on n-type InxGa1-xAs epitaxial layers deposited by MBE on GaAs substrates. The gate dielectric consists of 10 nm ALD Al2O3. It is shown that the dominant deep levels in the case of GaAs MOSCAPs are two broad interface-state-related bands centered around midgap, which appear to be very similar to what has been found in the past for other gate dielectrics on GaAs. At the same time, it is reported that the interface-state peak shifts closer to the conduction band for the InxGa1-xAs layers, whereby the activation energy becomes smaller for higher x. However, it is demonstrated that in this case not only interface states contribute to the DLTS emission signal but also deep levels associated with threading dislocations (TDs) in the relaxed layers. This contribution grows progressively with the In content, i.e., with the amount of relaxation. From this, it is concluded that InxGa1-xAs/GaAs substrates are not favorable for inversion-type of MOS devices due to the increasing impact of the TDs on the device performance.

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Physical and electrical properties of Ge/Al2O3/Pt and Ge/GeO2/Al2O3/Pt gate stacks using molecular beam deposition were proposed in this work. In spite of a straight deposition of Al2O3 on Ge substrate, XPS and TEM analysis revealed the formation of a thin interfacial layer coming from the intermixing between Ge sub-oxides and the high-ĸ dielectric. Electrical measurements showed a high density of interface states (3x1012eV-1.cm-2) mainly due to the presence of this interlayer. Performing a FGA in 10% H2/90% N2 on such structures leads to a significant reduction of DIT and leakage current density. Moreover, growing an in-situ GeO2 layer on Ge before high-ĸ deposition allowed us to reduce the interface states and to reach a very low DIT-value of 1~2x1011eV-1.cm-2 for Ge/GeO2/Al2O3 gate stacks after FGA, providing the efficient passivation of Ge/GeO2 interface. It has also been demonstrated that Al2O3 was a good capping layer, preventing from Ge/GeO2 interfacial degradation under high temperature treatment.