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In this study, the recent advances and trends in chiplet lateral communications (bridges) will be investigated. Emphasis is placed on the definition, kinds, advantages and disadvantages, challenges (opportunities), and examples of chiplet horizontal communications. Some recommendations will also be provided. [ABSTRACT FROM AUTHOR]

In this study, the heterogeneous integration of two chips on a 2.3D hybrid substrate using solder joint and underfill is investigated. Emphasis is placed on the materials, design, process, fabrication, and reliability of the package. Drop test and results of the package are also provided. [ABSTRACT FROM AUTHOR]

In this study, the recent advances and trends of chiplet design and heterogeneous integration packaging will be investigated. Emphasis is placed on the definition, kinds, advantages and disadvantages, lateral interconnects, and examples of chiplet design and heterogeneous integration packaging. Also, emphasis is placed on the fundamental and examples of hybrid bonding. [ABSTRACT FROM AUTHOR]

In this study, the reliability of the solder joints of a sixside molded panel-level chip-scale package (PLCSP) is investigated. Emphasis is placed on the thermal cycling test (25°C Δ 125°C, 50-min cycle) of the six-side molded PLCSP on a printed circuit board. For comparison purpose, the one without six-side molded (ordinary) PLCSP is also subjected to the same test. The thermal cycling test results are plotted into a Weibull distribution, and the true Weibull slope and true characteristic life at 90% confidence are presented. The solder joint mean life ratio of these two cases and its confidence level are also determined. Furthermore, their solder joint failure location and failure mode are provided. Finally, a nonlinear, time- and temperature-dependent 3-D finite element simulation is performed for these two cases and correlated with the thermal cycling test results. [ABSTRACT FROM AUTHOR]

In this study, the reliability of the solder joints of a heterogeneous integration of one large chip (10 × 10 mm) and two smaller chips (735 mm) by a fan-out method with a redistribution layer-first substrate fabricated on a 5153510-mm panel is investigated. Emphasis is placed on the thermal cycling test (25°C D 125°C, 50-min cycle) of the heterogeneous integration package on a printed circuit board (PCB). The thermal cycling test results are plotted into a Weibull distribution. The Weibull slope and characteristic life at median rank are presented. At 90% confidence, the true Weibull slope and the true 10% life interval are also provided. A linear acceleration factor is adopted to map the solder joint reliability at the test condition to the solder joint reliability at an operating condition. The failure location and failure mode of the PCB assembly of the heterogeneous integration package are provided and discussed. A nonlinear, time- and temperature-dependent 3-D finite element simulation is performed for the heterogeneous integration PCB assembly and correlated with the thermal cycling test results. [ABSTRACT FROM AUTHOR]

In this study, the design, materials, process, assembly, and reliability of a six-side molded panel-level chip-scale package (PLCSP) are presented. Emphasis is placed on the fabrication of the redistribution layers (RDLs) of the PLCSP on a large temporary panel with multiple device wafers. Because all the printed circuited board (PCB) panels are in rectangular shape, some of the device wafers are diced into two or more pieces so the panel is fully utilized. Thus, it is very high throughput. Because all the processes/equipment are PCB processes/equipment (not semiconductor process/equipment), it is a very low-cost process. After the fabrication of RDLs, the wafers from the PCB panel were debonded. It is followed by solder ball mounting and fabricating the six-side molded PLCSP from the original device wafers with RDLs. The drop test and the results including failure analysis of the PLCSP are presented. Thermal cycling of the six-side molded PLCSP PCB assembly is performed by a nonlinear temperature- and timedependent finite-element simulation. [ABSTRACT FROM AUTHOR]

In this investigation, the chip-last, redistribution-layer (RDL)-first, fan-out panel-level packaging (FOPLP) for heterogeneous integration is studied. Emphasis is placed on the materials, process, fabrication, and reliability of a heterogeneous integration of one large chip (10 3 10 mm2) and two small chips (7 3 5 mm2) by an FOPLPmethod on a 20320-mm2 RDL-first substrate fabricated on a 515 3 510 mm2 temporary glass panel. Reliability test such as the drop test of the heterogeneous integration package on a printed circuit board (PCB) is performed, and test results including failure analysis are presented. Some recommendations are also provided. [ABSTRACT FROM AUTHOR]

The recent advances and trends in heterogeneous integrations are presented in this study. Emphasis is placed on: (A) the definition of heterogeneous integrations, (B) the classifications of heterogeneous integrations such as heterogeneous integrations on (a) organic substrates, (b) silicon substrates (through-silicon via interposers), (c) silicon substrates (bridges), (d) fan-out RDL (redistribution-layer) substrates, and (e) ceramic substrates, and (C) the examples of heterogeneous integrations of chip-to-chip, chip-to-wafer, memory stacks, package-on-package, light-emitting diode, CMOS image sensors, microelectro- mechanical systems, vertical-cavity surface-emitting laser, and photodetector. The trends of heterogeneous integrations are also presented. [ABSTRACT FROM AUTHOR]

Thermal performance of 3D IC integration is investigated in this study. Emphasis is placed on the determination of a set of equivalent thermal conductivity equations for Cu-filled TSVs with various TSV diameters, TSV pitches, TSV thicknesses, passivation thicknesses, and microbump pads. Also, the thermal behavior of a TSV cell is examined. Furthermore, 3D heat transfer simulations are adopted to verify the accuracy of the equivalent equations. Finally, the feasibility of these equivalent equations is demonstrated through a simple 3D IC integration structure. [ABSTRACT FROM AUTHOR]

In this study, key enabling technologies such as the oxide liner by the PECVD, the barrier and seed layers by the PVD, and Cu plating of blind TSVs on 300 mm wafers for 3D integration are investigated. Emphasis is placed on the determination and optimization of the important parameters for each of the key enabling technologies. Also, the leakage current of the fabricated Cu-filled TSVs is measured. Furthermore, cross sections and SEM of the fabricated TSVs are examined. [ABSTRACT FROM AUTHOR]

This paper proposes a 3D IC integration TSV testing apparatus, primarily using at least one set of TSV component testing devices with a specific design. Under complex technological conditions, such as varying depth-width ratios of TSVs and heterogeneous IC integration, as well as the principle of different coupling parasitic parameters between TSVs, the TSV coupling measuring device designed for specific purposes in coordination with a measuring method for high-frequency coupling TSV Sparameters, achieves the function of monitoring the SiO2 thickness completeness of TSVs. This feasible approach further allows judgment of whether subsequent processes can continue, effectively reducing costs. [ABSTRACT FROM AUTHOR]

Moore's law has been the most powerful driver for the development of the microelectronic industry. This law is grounded in lithography scaling and integration (in 2D) of all functions on a single chip, perhaps through system-on-chip (SoC). On the other hand, the integration of all these functions can be achieved through system-in-package (SiP) or, ultimately, 3D IC integration. However, there are many critical issues for 3D IC integration. In this study, some of the critical issues will be discussed and some potential solutions or research problems will be proposed. [ABSTRACT FROM AUTHOR]

The design and assembly process of 10 different 3D MEMS packages will be presented and discussed in this study. These 3D MEMS packages integrate the MEMS devices from the MEMS wafer (with either wirebonding pads, or solder-bumped TSV, through silicon via, substrate, or solder-bumped flip chip without TSV), the ASIC chips from the ASIC wafer (either with or without TSV), and the cavity package cap from the cap wafer (either with or without TSV). The assembly process consists of release (etching), singulation, wire bonding, flip chip, TSV, cavity etching, chip-to-wafer (C2W) bonding, and wafer-to-wafer (W2W) bonding. It can be shown that these packages lead to a small packaging footprint, high electrical performance, and potentially low cost. [ABSTRACT FROM AUTHOR]