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Phase Change Memory (PCM) can directly connect persistent memory to main memory bus, while it achieves high read throughput and low standby power, the critical concerns are its poor write performance and limited durability. A naturally in-spired design is the hybrid memory architecture that fuses DRAM and PCM, so as to exploit the positive aspects of both types of memory. Unfortunately, existing solutions are seriously challenged by the limited main memory size, which is the primary bottleneck of in-memory computing. In this paper, we introduce a novel Content Aware Hybrid DRAM-PCM memory system framework—CAHRAM, which exploits deduplication to improve line sharing with high memory efficiency. It reduces write traffic to hybrid memory by removing unnecessary duplicate line writes, thereby further enhancing the write endurance of PCM. And it also substantially extends available free memory space by coalescing redundant lines in hybrid memory. We also design a reference-based page migration technique to minimize the access overheads caused by the performance gap between DRAM and PCM. Compared with the state-of-the-art in a hybrid memory simulator, our experiment results show that CAHRAM can achieve the highest I/O performance and the longest PCM lifetime with the competitive efficiencies in space and energy.

Offering a combination of low latency, high energy-efficiency, and flexibility, field-programmable gate arrays (FPGAs) suit applications ranging from Internet of Things (IoT) computing to artificial intelligence (AI). The conventional static random access memory (SRAM) FPGAs face severe challenges including large standby power and low logic density due to utilization of SRAM cell and MOS switch for signal routing. In response, researchers have introduced emerging non-volatile (NV) memory technologies to solve standby power issues. However, access transistors used for NV memory cell configuration still consume a large silicon area. In this article, we introduce an NV via-switch (VS) FPGA featuring fully back-end-of-line (BEOL) signal routing and front-end-of-line (FEOL) logic computing for high logic density. The VS fabricated in BEOL is constructed by two Cu atom switches (ASs) for signal routing and two a-Si/SiN/a-Si varistors for AS configuration. We demonstrate the first implementation of the VS-FPGA at 65-nm node and evaluate its performance by various basic applications. 2.6x logic density, 1.5x energy efficiency, and 1.4x operation speed are achieved in comparison with a previous complementary AS (CAS) FPGA in which one access transistor is necessary for each CAS configuration.

Memory arrays such as SRAM cells are responsible to the high-power consumption of modern digital systems. This investigation proposed an SRAM utilizing an ultra-low power cell, implemented using the 16-nm FinFET CMOS technology. Voltage supply selection of the static RAM cells is done by gating the wordline (WL) enable. In standby mode, the cell wordline is not activated, where the cell operates on a lower voltage level so that the stored bit status is still retained. On the other hand, the normal mode is activated when the wordline of the cell is enabled. Theoretical derivations, all-PVT-corner post-layout simulations, and measurement results were provided for verification of the functionality and performance. An SRAM of 1-kb capacity is designed based on the propose cell. The on-silicon measurement demonstrates 0.006832 fJ (energy/bit) at 500 MHz clock rate and 0.8 V supply.

A seamless mode-switch control scheme for primary side regulation flyback with capacitorless self-adaptive startup is presented in this article to increase the system stability for full-load range and reduce the area cost. Instead of traditional soft-startup, a peak current of primary side (PCPS) control scheme without off-chip capacitor is adapted during the startup process and a homologous startup modeling is built. Including the traditional pulsewidth modulation (PWM), the pulse frequency modulation (PFM), and deep pulsewidth modulation (DPWM) are adapted to reduce the standby power at utralight load. Meanwhile, a seamless control scheme is proposed to assure the continuity among the PCPS, PWM, PFM, and DPWM mode switch. The controller chip is fabricated in 0.18 μ m BCD process. The experiment results show that the startup time and overshoot voltage are, respectively, 35 ms and 4 V at 0.8 A load current, 48 ms, and 0.2 V at 0.008 A load current. The accuracy of output voltage is within ±0.98% under different input voltages and loads while the peak power efficiency of 88.52% is achieved.

Rotational speed detection is important for alternator-voltage-regulator (AVR) to starts-up and generates regulated electric power for vehicles. However, the rotational speed detection in standby mode for self-start is challenging with low loss rectifier, such as the Schottky diode. In this paper, a novel rotational speed detection method by sensing phase voltage or field voltage at specific modes is proposed to solve the issue without extra wiring or external components. The analysis of phase voltage in standby mode considering rectifier leakage current explains the challenges of conventional detection. The derivation of field voltage in standby mode with ANSYS Maxwell simulation verifies the proposed method. The experimental platform with a three-phase six-pole pairs alternator verified that the proposed method can detect rotational speed even in self-start and low speed of 200 rpm.

In this article, the effect of large double frequency capacitor voltage ripple (CVR) on harmonic performance, efficiency, and capacitor lifetime in the cascaded H-bridge low capacitance static reactive power compensator (StatCom) (LC-StatCom) is analytically determined. With insight provided by the analysis, an LC-StatCom with modular switched capacitors is proposed that provides a degree of freedom to control the CVR magnitude. The premise of the operation is to keep redundant capacitor modules in standby mode when operating with lower currents. In addition, it is shown that by distributing losses between additional dc-side switches and the main H-bridge switches, the proposed concept provides opportunities for choosing an optimal hybrid combination of semiconductor technologies. The proposed concept is evaluated using a simulated 8.5 MVA StatCom and feasibility of the proposed system is confirmed by experiments on a seven-level 0.8 kVA single-phase LC-StatCom prototype.

Due to its high modularity and scalability, the modular multilevel converter (MMC) has extensively been used in the modern industry. The low reliability of MMCs, which are consisted of tens or hundreds of vulnerable submodules (SMs), directly impacts the power supply continuity of the access systems. Redundancy and preventive maintenance are two significant measures to improve MMC reliability in operation. Therefore, this article presents a reliability model of MMCs with numerous SMs, whose lifetime follows arbitrary distribution, in redundancy strategies, such as active mode and standby mode. The lifetime of SMs is the minimum of component lifetime, which is estimated by a physics-of-failure-based lifetime estimation approach. Employing this reliability model, a reliability-centered maintenance (RCM) scheme with a minimum annual maintenance cost, is proposed to implement the dynamic decision of the maintenance intervals, quantitatively considering multistate of MMC operation. The relationship among redundancy, maintenance, and cost is further discussed in case studies. The proposed reliability model and RCM scheme provide a guideline for MMC redundancy strategy selection and maintenance decision.

Microgrids are becoming a significant aggregation of distributed energy resources (DERs) that improves the reliability and resilience of the power delivery system. Most of the early microgrid experience occurred in behind-themeter applications for installations with critical loads and significant backup power and load prioritization requirements. Very successful systems that include campus and utility applications have been operational for up to and exceeding a decade. For these early systems, available codes and standards consisted mostly of adapted device-level legacy emergency and standby power requirements. Grid interconnection and efficient, safe operating requirements were improvised via programmed computers, and the protection focus was the microgrids themselves. The larger microgrid installations often required qualified staff trained to monitor and operate the systems.

Wireless sensor nodes spend most of their time in standby mode and wake up periodically to send measurement data. Typically, a radio-frequency antenna is coupled with an amplifier to provide this wake-up function; together, these two elements recognize instances of radio signal activation. Even during standby operation, the sensor node utilizes a certain base amount of energy, which can be critical when using an energy-harvesting source. In this study, we propose a novel optical approach to the wake-up function for autonomous sensor nodes, which employs a solar cell as the wake-up signal detector. A bright light flash coming from another node or a smartphone hits a solar cell and activates the sensor node. Unlike photodiodes or RF-antennas, solar cells do not require any additional energy to detect such a signal. Therefore, the proposed electrical circuit allows the sensor node to wake-up from a complete power-off state. The solar cell of the novel wake-up receiver has an area of sensitivity of 8 mm $\times10$ mm. The wake-up signal can be recognized from a maximum distance of 25 cm at a range of ambient illumination from 0 – 1600 lx with a transmitter optical power of 20 mW. In the power-off state, the power consumption of this novel design is the lowest of all existing off-the-shelf wake-up receivers: 248 pW at 0 lx and 627 nW at 1600 lx.

A Pt-functionalized hydrogen sensor was fabricated on a recessed AlGaN/GaN heterojunction platform where the thickness of the recessed AlGaN barrier layer under the Pt catalyst was 10 nm. Sensing characteristics were investigated under two different bias modes: forward and reverse bias operations. Unlike conventional diode type sensors, the recessed heterojunction sensor exhibited superior sensing characteristics under the reverse bias operation mode in comparison to the forward bias operation mode. The thin AlGaN barrier layer enhanced the field emission process under reverse bias operation, thus enabling a high response, which had another benefit of significantly lowering standby power consumption compared to the forward bias operation mode. A response of ~870 % and a response time of ~11 sec were achieved at 200°C with a standby power consumption of 0.03 W/cm2.

An ultralow-voltage retention SRAM (ULVR-SRAM) cell using header and footer power-switches (HFPSs) is investigated for power-gating (PG) applications. The cell can change its operational mode depending on the cell voltage ( ${V} _{\mathrm{ cell}}$ ) controlled by the HFPSs: When the ordinary supply voltage is applied, the cell can act as a high-performance SRAM cell. When ${V} _{\mathrm{ cell}}$ is reduced to an ultralow voltage, the cell can transition to the ULVR mode and dramatically reduce the leakage power without losing its data, i.e., the substantive PG can be achieved using the ULVR. The ability of leakage power reduction is enhanced by introducing the body biases that are automatically induced only during the ULVR mode. The design methodology is developed based on quasi-static noise margins, where the transistor sizes and the bias condition for ${V} _{\mathrm{ cell}}$ are determined so as to minimize the leakage power with keeping a sufficiently high noise margin in the ULVR mode. An optimally designed ULVR-SRAM cell shows excellent PG ability: The leakage power can be reduced by ~98% using the ULVR and a minimally short break-even time of $1.5\mu \text{s}$ can be achieved for the 8KB macro. The ULVR-SRAM can provide a new class of energy efficient PG architecture.

This paper proposes a 300 mA low-dropout (LDO) regulator using an $I_{Q}$ of only $0.94~\mu \text{A}$ , which has the advantage of minimizing power consumption in the standby mode of a battery-based system. The LDO uses a source follower buffer with dynamic biasing to maintain loop stability and load transient response performance. Under light-load conditions, the buffer enters a fully-off state because there is a sub-nA bias current. Therefore, the LDO uses a dual output operational transconductance amplifier (DO-OTA) for operation under light-load conditions. The second output of the DO-OTA for light-load operation in the LDO forms an additional feedback path instead of the fully-off buffer. The second output of the DO-OTA is designed to consume a current lower than the bias current of the buffer while operating. Furthermore, the buffer in the LDO is designed for operation above 5 mA $I_{L}$ . While the buffer is operating, the dynamic biasing current of the buffer is used as the second output of the DO-OTA. The second output of the DO-OTA has lower output impedance characteristics than its main output, so the LDO can secure loop stability under light-load conditions by lowering the DC gain. As a result, the LDO exhibits load transient response performance up to 300 mA by using a minimal $I_{Q}$ under the no-load condition. The LDO is based on a 180 nm bipolar-CMOS-DMOS (BCDMOS) process and covers an area of approximately $256 \times 143 \mu \text {m}^{2}$ . The measured $I_{Q}$ is $0.94~\mu \text{A}$ under the no-load condition with a maximum load current of 300 mA.

Nowadays, energy is one of the main considerations with the increasing demands for IoTs, wearable-devices, machine learning and artificial intelligence. Asynchronous logic is a viable solution to address the energy issues owing to its advantages of no clock tree, robust circuit operation and avoidance of worst-case timing. NULL Convention Logic (NCL), one of the most popular asynchronous logic paradigms, expresses logic directly and needs minimal delay analysis. However, mainstream CMOS-based NCL still suffers from high static power issue. Spin transfer torque magnetic tunnel junction (STT-MTJ) is a potential device for low-power NCL design with the merits of non-volatility, high speed, nearly zero standby power and 3-D integration capability. In this work, we designed a novel nonvolatile NCL (NV-NCL) pipeline by integrating NCL and STT-MTJ. Compared to traditional NCL pipeline, our proposed NV-NCL pipeline exploits nonvolatile registers (NVRs) to reduce static power consumption. Meanwhile, write completion detector (WCD) was added in NVR to realize self-adaptive writing, further reducing dynamic write power. The behaviors and performance of the proposed NV-NCL pipeline were evaluated by using a 40 nm CMOS process and an in-house developed STT-MTJ model. Finally, parameter optimizations are explored to improve performance in terms of write time (∼5 ns), power consumption (∼0.48 pJ/bit) and reliability.

This article presents Switched-Capacitor assisted Power Gating (SwCap PG) for reducing the leakage currents of large digital circuits. For the first time, PG switch is biased in the super turn-off and the super turn-on mode during the off-state and the on-state, respectively. A simple switched-capacitor network reconfigures and biases the PG switch in four different possible states with low area and power overhead. During the super turn-off, voltage stress is avoided in the PG switch when the circuit load uses supply voltage equal to the nominal $\text{V}_{\mathbf {DD}}$ in a given technology, and maximum possible leakage current reduction is achieved by the optimal biasing of the gate voltage. The proposed SwCap PG is experimentally validated in the 180nm CMOS technology. Measurement results of CMOS SwCap PG show that leakage current and $\text{R}_{\mathbf {ON}}$ reduce by 186- $226\times $ and 18% respectively, as compared to the conventional PG. An alternate solution for SwCap network using MEMS devices as the switching elements is implemented for additional benefits. Measurement results of MEMS SwCap PG show that leakage current and $\text{R}_{\mathbf {ON}}$ reduce by $172\times $ and 26% respectively, compared to the conventional PG. Finally, the applicability of the SwCap PG in the nano-scale CMOS technologies is addressed.

A highly integrated, high-voltage dual-mode boost converter is presented for solid-state drives applications in portable devices, where standby mode efficiency with 100-mA load. To enhance efficiency in light load conditions and to achieve a wide operation load range, loss minimization by balancing conduction and switching losses is adopted, and a dynamic power-gating scheme is applied for pulse frequency modulation mode operation. Moreover, robust dual-mode operation is implemented with a time-based control scheme, which enables operation with a lower peak current for optimal loss balancing. The proposed converter is fabricated in 130-nm complementary metal-oxide-semiconductor process with an area of 1.7 mm2. The measured efficiency for supplying 12-V output from 5.5-V input is 91% at its peak load of 40 mA and 85% with an extremely light load of 200 μA. It also achieves a wide dynamic load range from 200 μA to 600 mA for >85% efficiency and from 2 to 150 mA for >90% efficiency.

We propose a maximum efficiency tracking for a multiple-transmitter system that optimizes both the current ratios of transmitter (Tx) coils and the effective Rx load. It is found that unlike the single-Tx case, the optimal load impedance of multiple-Tx system depends on the current ratios among Tx coils. Meanwhile, the Tx current ratios should be controlled to be the same with magnetic coupling ratios between each Tx and Rx. Hence, we propose a two-step tracking method that first optimizes the Tx current ratios and then optimizes the Rx load impedance. To match the Tx current ratio with the magnetic coupling ratio, it is analyzed that the reflected resistances at every Tx become identical to each other when the Tx coil current ratios are equal to the magnetic coupling ratios. It is also revealed that the reflected resistance at specific Tx is reduced (increased) when its Tx current is increased (reduced) relative to other Tx currents. The proposed feedback equalizes all reflected resistances based on this property. The second step of the proposed tracking is to optimize the Rx load while fixing the Tx current ratios by globally scaling up or down the strengths of whole Tx currents. Maximum of 478 W is delivered at 79% efficiency. The algorithm does not have a limit on the number of Txs except the small standby power consumption. The proposed theoretic analysis and control method enable the first-ever maximum efficiency tracking for multiple-Tx system, where the first step optimizes the relative Tx current ratios and the second step optimizes the load impedance.

Resistive memory (ReRAM) has emerged as a promising nonvolatile memory technology that may replace a significant portion of DRAM in future computer systems. ReRAM has many advantages, such as high density, low standby power, and good scalability. When adopting crossbar architecture, ReRAM cell can achieve the smallest theoretical size in fabrication, which is ideal for constructing dense memory with large capacity. However, crossbar cell structure suffers from a variety of reliability issues, which come from large voltage drops on long wires. To ensure operation reliability, ReRAM writes conservatively use the worst-case access latency of all cells in ReRAM arrays, which leads to significant performance degradation and dynamic energy waste. In this article, we study the correlation between the ReRAM cell switching latency and the number of cells in low-resistance state (LRS) along bitlines, and propose to dynamically speed up write operations based on bitline data patterns, i.e., the number of LRS cells presented in bitlines. We leverage the intrinsic in-memory processing capability of ReRAM crossbar and propose a low-overhead runtime profiler that effectively tracks the data patterns in different bitlines. To achieve further write latency reduction, we employ data compression and row address dependent memory data layout to reduce the numbers of LRS cells on bitlines. Moreover, we further present two optimization techniques, i.e., selective profiling and fine-grained profiling, to mitigate energy overhead brought by bitline data patterns tracking. The experimental results show that, on average, our design improves system performance by 20.5% and 14.2%, and reduces memory dynamic energy by 20.3% and 12.6%, compared to the baseline and the state-of-the-art crossbar design, respectively.

Notice of Violation of IEEE Publication Principles by Soumyabrata Patra in IEEE Sensors Journal, Vol. 20, No. 12, June 15, 2020 After careful and considered review of the content and authorship of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE’s Publication Principles. This paper contains significant portions of original text from the paper cited below. The original text was copied without attribution (including appropriate references to the original author(s) and/or paper title) and without permission. Performance of a Modified Magnetostrictive Energy Harvester in Mechanical Vibration" by Subhasish Dey, Debabrata Roy, Soumyabrata Patra, Tapan Santra, in Heliyon, Vol 5, Issue 1, January 2019 Billions of off line powered smart things with embedded intelligence, such as sensors, actuators, and connectivity will support the rapid growth of IoT in the near future. The significant impact on worldwide energy consumption from these always-connected products has driven the need for compact, highly efficient off line power converters with ultra-low standby power consumption. This paper developed a novel Magnetostrictive energy harvester (MEH) with a power electronics converter for battery-free IoT applications. The developed energy harvester using Fe-Ga alloy (7×2×42 mm 3 ) as a Magnetostrictive material is able to generate peak to peak voltage around 21.6 Vat a vibration frequency of 29 Hz with the efficiency of 49% yields an average power of 51.23 mW. Such MEH output cannot be directly used to power IoT devices as it contains harmonic. This paper proposed two prototypes, MEH as a vibration sensor with sensitivity around 55 V.s/m (volt/(meter/second)) and as a DC power source for IoT devices, which can able to provide 10 V DC at 44.4 mWpower.

The opto-coupler is usually used for isolated resonant converter to feedback the secondary-side output information. However, the characteristics of the opto-coupler are easily affected by the operating conditions, which will cause higher standby power loss. In this article, a novel primary-side controlled isolated half-bridge resonant converter with output voltage and current estimation for LLC and series resonant converter (SRC) operations is presented. The output voltage is estimated by sampling the auxiliary winding voltage when the output diode current flows to zero, the output current is estimated by integrating the resonant current until the transformer decoupled. The operating principles of the half-bridge resonant converter and the design criteria of the key component parameters are addressed and analyzed. Also, the methods for estimating output voltage and output current are discussed in detail. Finally, an experimental prototype with rated power 100 W half-bridge resonant converter for input voltage 280-342 V and output voltage 24 V is built with microcontroller to validate the proposed primary-side regulation technique. Experimental results show the output voltage and current can be controlled with the error less than 1% and 8%, respectively. The highest efficiency of the system is 95.2%.

Recently, various magnetic non-volatile ternary content-addressable memory (MNV-TCAM) cells that use magnetic tunnel junctions (MTJs) as storage units have been proposed to realize zero standby power. However, they still suffer from low reliability and high power consumption for search operation. In addition, the restrictions on the ordering of the TCAM array required by the using of the priority encoder to resolve the multiple match problem due to the ‘X’ results in large delay and high energy consumption for update operation. To address these issues, the novel MNV-TCAM cell is first proposed, aiming to achieve high-speed, low-power, and high-reliable search operation. In addition to the search data operation, it can realize a search length operation. By exploiting this search length operation, we then present circuit-level design of the MNV-TCAM with a priority-decision in memory technology, which can utilize the length information of matched words sorted in an arbitrary order to decide the highest-priority matched word by performing a three-phase search operation. It implies that the restrictions on the ordering can be eliminated, thus, improving the update speed and energy-efficiency. Finally, hybrid CMOS/MTJ simulations are performed to demonstrate its functionality and evaluate its performance in terms of search reliability, search speed, and search energy consumption.

Power-efficiency has become one of the most critical concerns for HPC as we continue to scale computational capabilities. A significant fraction of system power is spent on large main memories, mainly caused by the substantial amount of DIMM standby power needed. However, while necessary for some workloads, for many workloads large memory configurations are too rich, i.e., these workloads only make use of a fraction of the available memory, causing unnecessary power usage. This observation opens new opportunities for power reduction by powering DIMMs on and off depending on the current workload. In this article, we propose footprint-based DIMM hotplug that enables a compute node to adjust the number of DIMMs that are powered on depending on the memory footprint of a running job. Our technique relies on two main subcomponents-memory footprint monitoring and DIMM management-which we both implement as part of an optimized page management system with small control overhead. Using Linux's memory hotplug capabilities, we implement our approach on a real system, and our results show that our proposed technique can save 50.6-52.1 percent of the DIMM standby energy and the CPU+DRAM energy of up to 1.50 Wh for various small-memory-footprint applications without loss of performance.

This letter describes a miniature, ultra low power, all-dynamic temperature sensor based on a duty-cycled resistive transducer bridge and a 9-bit asynchronous SAR ADC in 65-nm CMOS. It features a novel floating bridge technique and automatic power gating to achieve the lowest reported power consumption. It consumes 2.18 pJ per conversion and has an RMS resolution of 0.53 K, leading to an FoM of 0.61 pJ $\cdot \text{K}^{2}$ . A standby power of 52 pW allows a high power-efficiency, even at low sample rates. It occupies $36\times 46\,\,\mu \text{m}$ of chip area and has a sensing range from −20 °C to 120 °C.

This article presents a highly stable SRAM-based physically unclonable function (PUF) using enhancement–enhancement (EE)-structure bit cells for native stability improvement. The PUF bit cells are power-gated 2-D and are normally in the OFF state, which largely reduces power and is beneficial to attack tolerance. In addition, a dark-bit detection technique based on a lightweight integrated ${V}_{\text {SS}}$ -bias generator is implemented in order to screen out potentially unstable bit cells (dark bits) induced by supply voltage/temperature (VT) variations and other factors. Measured native bit error rate (BER) of prototype chips fabricated in 130-nm standard CMOS is 0.21% at 0.8 V and 23 °C, which is 14 $\times $ better compared with the conventional SRAM-based PUF. After masking the detected dark bits, no bit error (3339 bits $\times $ 500 evaluations) appeared at the worst VT corner across 0.8 to 1.4 V and −40 °C to 120 °C. This technique also eliminated all unstable bits in the accelerated aging test. Both the data before and after dark-bit masking have passed all applicable NIST SP 800–22 randomness tests. The measured operational energy at 0.8 V is 128 fJ/bit and the standby power is 0.44 pW/bit, thanks to the 2-D power-gating scheme. The nMOS-only bit cell is highly compact, with a normalized bit cell area of 373 F 2.

In this paper, we present a battery management technique that significantly increases the battery lifetime of event-based devices that are predominantly in standby mode without requiring off or on chip large power switches. The proposed technique uses a novel battery management technique to remove Wake-Up Receiver (WUR) Low Drop-Out (LDO) unit, while causing minimal change to the system’s power supply configuration. This technique manages the system so that it can wake up to a normal battery configuration while sleeping in a different battery set-up. This, as a result, drops standby power consumption significantly, making the proposed technique suitable for IoT sensors and, in general, event-based devices. Battery management comprises of voltage level detector, switches for changing battery configuration, and voltage level shifters. The design was applied to an active Radio Frequency Identification (RFID) tag with an embedded WUR and fabricated using TSMC 180nm technology. Measurements on the test chip showed that the proposed architecture and design leads to 80% standby energy saving, prolonging overall (active plus standby) battery’s lifetime by 2.5 times while having negligible area overhead. The advantages and disadvantages of the proposed technique are also presented and discussed.

Quaternary memory and logic circuits have been studied by researchers, as they can provide denser integrated circuits and subsequently lower area and power consumption via succinct interconnects. Using multithreshold gate-all-around carbon nanotube field-effect transistors and the nonvolatile feature of magnetic tunnel junctions (MTJs), this letter proposes a bio-inspired variation-aware nonvolatile quaternary latch (Qlatch). Nonvolatility allows the system to be completely powered off during the idle state to reduce standby power significantly without the need for extra component and data loss. Moreover, thanks to the bio-inspired structure of the Qlatch, and the fact that no sense amplifier is used in this circuit to read the MTJs, the Qlatch is more robust to process variations. Simulation results show that the nonvolatile Qlatch consumes 7% less dynamic power and 12% less static power than the conventional Qlatch, has a 61% lower delay, and has 68% lower power delay product.

This letter presents a microcontroller unit (MCU) that employs a $c$ -axis aligned crystalline indium–gallium–zinc oxide semiconductor FET (CAAC-IGZO FET) with an extremely low off-state current below the zepto-ampere (10−21 A) level. This MCU based on IGZO-FETs has logic circuits and memory macros that can retain data even when the power supply is turned off, and internal voltage regulators that store the reference voltage. A prototype chip has been fabricated with a monolithic process that combines an IGZO process (embedded in BEOL) and an Si CMOS process; the chip has a standby power of 880 nW, a system backup time of 21 ns with 44 fJ/bit, and a wakeup time of $4.69~\mu \text{s}$ . The fabricated chip has demonstrated that the highly energy-efficient normally off computing that establishes low-power operations in Internet of Things and edge AI computing can be achieved with IGZO technology.

A hybrid device technology reconfigurable logic fabric is proposed which leverages the cooperating advantages of distinct magnetic random access memory (MRAM)-based look-up tables (LUTs) to realize sequential logic circuits, along with conventional SRAM-based LUTs to realize combinational logic paths. A hierarchical top-down design approach is used to develop a hybrid spin/charge based FPGA (HSC-FPGA) starting from the configurable logic block (CLB) and slice structures down to LUT circuits and the corresponding device fabrication challenges. Circuit-level simulations indicate at least 40% and 83% read and standby power reduction, respectively, for MRAM-LUTs compared to SRAM-LUTs. However, MRAM-LUTs using spin transfer torque (STT) switching approach suffers from significant write energy consumption. Therefore, we have designed spin Hall effect (SHE)-assisted MRAM-LUTs realizing more than 67% and 61% reduction in reconfiguration energy and area consumption, respectively. Fabric-level simulations exhibit that HSC-FPGA achieves 70% and 30% reductions in standby and read power, respectively, compared to SRAM-based FPGAs for various ISCAS-89 and ITC-99 benchmark circuits. Finally, a multi-level method spanning device-sizing, circuit modular-redundancy, and component-level reconfiguration is developed to increase the process variation resiliency of the MRAM-LUTs. The power consumption and area utilization are analyzed to formulate tradeoffs resulting in recommendations toward future multi-device-based reconfigurable fabrics.

In this brief, a silicon-on-thin-BOX (SOTB) implementation of single-precision floating-point fast-Fourier-transform (FFT) twiddle factor (TF) is presented. The architecture of the proposed TF is developed based on the adaptive method of the coordinate rotation digital computer (CORDIC) algorithm. The 65-nm SOTB technology was chosen because of its ultra-low-power advantage. Furthermore, the back-gate bias technique can be applied on an SOTB chip to adjust the operation for high-performance or low-power requirement. The layout of the SOTB 65-nm TF core is about 22869 gate-count on the die area of 86721 $ \mu \text {m}^{2}$ . The measurement results show that the core reached its highest operating frequency of 55 MHz at the 1.2-V supply voltage (VDD) with the forward back-gate bias (FBB) ≥ 1.5 V. The power and energy consumptions at this point were 1.54 mW and 27.91 pJ/cycle, respectively. The lowest operating VDD was at 0.5 V with the FBB ≥ 0.5 V. In the standby mode, when the clock-gating technique was deployed, the leakage current can be reduced to 0.4 nA at the 0.4 V VDD and −2.5-V reverse back-gate bias (RBB).

Spin-Torque Transfer Magnetic RAM (STT-RAM), one of the emerging nonvolatile memory (NVM) technologies explored as the replacement for SRAM memory architectures, is particularly promising due to the fast access speed, high integration density, and zero standby power consumption. Recently, hybrid deigns with SRAM and STT-RAM buffers for routers in Network-on-Chip (NoC) systems have been widely implemented to maximize the mutually complementary characteristics of different memory technologies, and leverage the efficiency of intra-router latency and system power consumption. With the realization of Processing-in-Memory enabled by STT-RAM, in this paper, we novelly offload the execution from processors to the STT-RAM based on-chip routers to improve the application performance. On top of the hybrid buffer design in routers, we further present system-level approaches, including an ILP model and polynomial-time heuristic algorithms, to fine-tune the application mapping and scheduling on NoCs, with the objectives of improving system performance-energy efficiency. Network overhead caused by flit conflict in conventional communication circumstances can be ideally avoided by computing the contended flits in intermediate routers; meanwhile, the pressure of heavy workload on processors can be relieved by transferring partial operations to routers, such that network latency and system power consumption can be significantly reduced. Experimental results demonstrate that application schedule length and system energy consumption can be reduced by 35.62, 32.87 percent on average, respectively, in extensive evaluation experiments on PARSEC benchmark applications. In particular, the achievements of application performance and energy efficiency, averagely 36.44 and 33.19 percent, for the CNN application AlexNet have verified the practicability and effectiveness of our presented approaches.

A dual-gate configuration has been introduced to organic thin-film transistors (TFTs) for full-depletion behavior to enhance the transconductance, subthreshold slope, and drain current on–off ratio. In this letter, we show how those dual-gate effects influence the static and dynamic responses of three-dimensional (3-D) complementary organic logic gates in comparison to their single-gate counterpart. For the comparative study, 3-D inverters and ring oscillators were fabricated by printing directly on plastic foil in both single- and dual-gate configurations. In the static inverter operation, the fully depleted characteristics of the dual-gate TFTs lead to an increase in voltage gain and a dramatic decrease in standby power consumption. In the dynamic ring oscillator operation, the two configurations have comparable gate delays because the use of an additional gate increases not only the drain current but also the load input gate capacitance. Our findings demonstrate the performance of an inverter that can represent the overall operation of complementary logic gates consisting of pull-up and pull-down networks, thereby providing significant insight into the printed organic TFT circuit design using dual gating effects.

Leakage power consumption of clock distribution networks (CDNs) is an important challenge in modern synchronous integrated circuits with billions of deeply scaled transistors. Multithreshold CMOS technology is commonly used to provide power reduction in standby mode while maintaining high performance in active mode. In this paper, a novel dual-threshold-voltage repeater circuit with split inputs–outputs (SPLIT-IOs) is employed for suppressing leakage currents in gated CDNs. Three floor planning strategies are considered for clock distribution across the chip with signal transition times of less than or equal to 50 ps at the leaves. Depending on the power supply voltage and floor plan, the standby leakage power consumption is reduced by 50.36%–78.43% with the proposed clock tree with SPLIT-IO repeaters as compared to the conventional three-level H-tree in a 45-nm CMOS technology. The spread of standby leakage power due to process variations is compressed by 36.72%–73.77% with the proposed clock tree as compared to the standard network. The proposed circuit technique significantly lowers the total energy consumption of partially active networks with local clock gating as well. The energy savings provided by the SPLIT-IO buffers are enhanced with the scaling of power supply voltage and frequency in synchronous systems-on-chip.

When wirelessly supplying electric power to movable devices using capacitive power transfer (CPT) technology, the sudden move in and move out of the pickup will cause a sudden change to the system structure. As a result, the current and voltage of the inverter may increase dramatically, which may destroy the semiconductor switches or other circuit components, and the system may consume a lot of power after the pickup is removed. To address the issues, this paper proposes an F-type compensated CPT system based on the characteristics of the inductor–capacitor–inductor resonant network. A steady-state model of the proposed CPT system is established, and a set of design equations is provided. The feasibility and validity of the proposed topology and its parameter design method have been verified by the simulation and experimental results. It has demonstrated experimentally that the CPT prototype can be self-protected and automatically enter standby mode after the pickup is removed, and restore to deliver the required power (>25 W) to the load at a high power efficiency (>80%) after the pickup is moved back to the primary circuit, which are the inherent features of the proposed system rather than relying on any additional detection and control.

A bidirectional link geared toward mobile I/O applications is presented that leverages the technological advantages of CMOS scaling to improve energy efficiency. Active power consumption is minimized by operating the link at low power-supply voltage (VDD), using a digital intensive design that avoids the use of bias voltage or current DACs, a low swing transmitter with a source-series terminated (SST) driver, and circuit and system co-design. To enable fast transitions between different active and standby power modes, a feedforward clock-and-data recovery (CDR) topology based on blind-oversampling is employed. A direct data-sequencing technique for blind oversampling is proposed that significantly reduces the area and power consumption of conventional techniques, while improving the low-frequency jitter tolerance as well. A prototype serial link comprising of the transmitter, receiver, and an all-digital phase-locked loop (ADPLL) achieves a data-rate of 1.2–5 Gb/s with total energy/bit of 1–1.31 pJ/b. The transceiver (TX and RX) itself has an energy/bit of 0.6 pJ/b. The link occupies an area of 0.041 mm2 in 22-nm CMOS technology and operates at VDD of 0.55–0.7 V.

Recently, several magnetic tunnel junction (MTJ)-based non-volatile ternary content-addressable memory (NV-TCAM) cells have been proposed to realize zero standby power. However, they still suffer from low reliability and high power consumption during search operations. To address these issues, we propose a novel MTJ-based NV-TCAM cell, which is composed of 15 transistors and 4 MTJs (15T-4MTJ). By utilizing the differential MTJs with complementary states and positive feedback of cross-coupled inverters for sensing, the proposed 15T-4MTJ NV-TCAM cell can significantly improve the search reliability. Moreover, owing to that there is no static current during search operations, only dynamic charging and discharging current, it can achieve ultra-low power consumption. In addition, by using only one transistor as the critical path between the match-line and GND, its switch delay can be shortened, thereby realizing high-speed search operations. Hybrid CMOS/MTJ simulation results of the 144-bit word circuit show that the proposed 15T-4MTJ NV-TCAM cell can obtain a smaller search error rate of 2.7%, a higher search speed of 0.17 ns, and a lower search energy of 0.17 fJ/bit/search in comparison with other MTJ-based NV-TCAM cells. On the other hand, its write energy of 1.589 pJ/bit is about $3.64\times $ smaller than that of the previously proposed 10T-4MTJ NV-TCAM cell.

In this paper, low-energy radiation-hardening approaches are proposed to develop non-volatile (NV) flip-flop (FF) circuits using spintronic devices. In particular, spin Hall effect magnetic tunnel junctions are used to design a radiation-hardened NV-latch that is proposed to be utilized as a shadow latch to maintain the data during the standby mode when the circuit is power-gated. Moreover, soft-error resilient complementary metal–oxide–semiconductor-based latching circuits are designed to be leveraged as master and slave latches in the NVFF structure. The proposed hardening techniques are based on using feedback loops and clock-gating Muller C-elements, as well as increasing the charge capacity of the vulnerable nodes. The circuit simulations indicate that the proposed single-event upset and double node upset resilient latching circuits can achieve at least 81% and 24% power-delay product improvement, respectively, while incurring comparable area overhead compared to the previous energy-efficient radiation-hardened latch designs. Finally, the proposed latching circuits are combined to develop four radiation-hardened NVFF designs. The results obtained show that, using the proposed NV latching circuit as a shadow latch can result in two orders of magnitude reduction in energy consumption compared to the FF circuits with an NV master latch. In addition, the proposed latches achieve favorable tradeoffs in terms of minimized performance overheads and maximized robustness (100%) of soft fault coverage to single and double upsets. Thus, the proposed NVFFs can be employed within logic datapaths to ensure data integrity as a potential mainstream solution for aerospace and avionic nanoelectronics.

Recently, energy conservation has been concerned, and there are several aspects to improve the energy consumption issues. Therefore, many research results were proposed to mitigate the related problems, one of these is to eliminate the extra standby power of household appliances. This paper employed an effective method to identify load characteristics of appliances in different operation states by support vector machines, and a smart home electric energy saving system was built up to implement the method. Furthermore, a virtual living room was simulated in the laboratory as an experimental object, and a prototype system was built up. The performance test results are proposed to validate the feasibility of the proposed system.

In this paper, we propose a novel static random access memory (SRAM) unit cell design and its array structure consisting of single-gated feedback field-effect transistors (FBFETs). To verify the SRAM characteristics, the basic memory operations and write disturbances of the unit cell are investigated through the mixed-mode technology computer-aided design simulations. The unit cell exhibits the superior SRAM characteristics including a write speed of 0.6 ns, a fast read-out speed of ~0.1 ns, and a retention time of 3600 s. Furthermore, the unit cell design exhibits advantages in density, with a small cell area of 8F2, and in the power consumption; the standby power consumption is 0.24 nW/bit for holding “1” and negligible for holding “0.” Moreover, our SRAM array shows reliable ${3} \times {3}$ array operations without any disturbances. This paper demonstrates the promising potential of the FBFET SRAM for high-performance, high-density, and low-power memory applications.

Many emerging devices are currently being explored as potential alternatives to complementary metal-oxide-semiconductor technologies for overcoming power density and energy efficiency limitations. It is now generally accepted that these emerging devices need to be evaluated at the circuit level. In this paper, we investigate the speed and power performance of hyper-field-effect transistor (Hyper-FET) circuits, comparing them with both high-performance and low standby power fin-shaped FET designs on the same technology node. The evaluation, which was carried out at the gate level and circuit level, includes a characterization of 8-bit ripple carry adders. Our experiments showed around 80% speed degradation and 30% power savings for a given range of operating frequencies. These power savings were much smaller than those predicted from the transistor- and gate-level estimations. Deviations from the ideal expected behavior of the Hyper-FET circuitry are illustrated, which support the obtained results.

For more than a century, the Automatic Switch Company (ASCO), now ASCO Power Technologies (Figure 1), provided emergency and standby power equipment to a wide range of industries. Best known for its innovative and robust transfer switches, ASCO Power also developed industry-leading solutions for power control switchgear and other equipment used in mission-critical applications. This article summarizes ASCO Power?s history of innovation and its continuing influence on the industries it serves.

The nanogrids are the basic unit to develop more complex and stronger distributed systems. DC nanogrids allow a better performance and higher efficiency than the AC nanogrids. The lack of DC home appliances in the local market has resulted in a slow development of DC Home Nanogrids (DCHN). The Compact Fluorescent Lamp (CFL) and LED are used in power electronics as high efficiency and low cost lightning components. However, these devices represent a source of emission of harmonics in Alternating Current (AC) and Direct Current (DC) systems, due to their nonlinear behavior. In this paper a mathematical model for the nonlinear loads and experimental results of the voltage and current ripple in a DCHN are presented. The CFL and LED lamps are used as our nonlinear loads for test the model. The model explains well the experimental results of how the ripple amplitude is reduced. We also present the effect of decreasing the ripple amplitude when it is incorporated an induction stove in standby mode to the DCHN, which also is explained by the model.

As technology node scales down below 90 nm, the conventional complementary metal oxide semiconductor (CMOS) logic circuits suffer from various problems such as high standby power due to increase in leakage current. Spintronic devices based on magnetic tunnel junction (MTJ) is one of the most promising technology candidates for the future of the digital circuits. MTJ-based logic circuits can offer nonvolatility, high endurance, high density, low standby power dissipation, and 3-D integration capability with the CMOS technology. In recent years, several full-adder circuits are proposed based on MTJs that are not fully nonvolatile since they use MTJs to store only one of their inputs. This paper proposes a fully nonvolatile magnetic full-adder (MFA) circuit offering the capability of power gating with no loss of data. The proposed circuit stores all the inputs in MTJs using the spin-transfer torque (STT) method assisted by the spin-Hall effect (SHE). Thanks to the SHE assistance, delay and power consumption of the MTJ switching are reduced significantly. Moreover, as a result of lower write current, the endurance of the oxide barrier can be increased. Using a three-terminal SHE–STT–MTJ model and a 45 nm CMOS SPICE model, we simulated and validated the functionality of our design and compared it with some recent previous MFAs. Simulation results reveal that the proposed MFA offers considerable superiorities over the recent counterparts.

Micromechanical photoswitches (MPs) have shown orders of magnitude lower standby power consumption compared to their solid-state technology-based counterparts. In this paper, we demonstrate that the infrared detection threshold (i.e., the lowest detectable power of incident infrared radiation) of this new type of photoswitch can be effectively decreased by applying a bias voltage across the switch without compromising its key feature of near-zero standby power consumption and low false-alarm rate. We show that by exploiting the electrostatic pull-in effect (using bias voltage of ~7 V), a threshold as low as 76 nW can be achieved, which is the lowest threshold demonstrated to date for MPs. A mathematical model predicting the device threshold under a bias voltage is derived and verified by experiments. Furthermore, the effects of the bias on the device’s stability are carefully studied suggesting the existence of a tradeoff between the detection threshold and the false-alarm rate when the bias is higher than 85% of the pull-in voltage. The source of the instability that causes false alarms is found to originate from charge accumulation over time in the dielectric substrate surrounding the bottom contact, which we believe can be mitigated by an improved contact design. Another effect associated with high bias is the contact stiction after infrared-triggered pull-in. To address this, a microheater is integrated into the switch to reopen the contacts while consuming only $\sim 0.5~\mu \text{J}$ per operation. This paper thus presents an effective solution for post-fabrication threshold adjustment of MPs, which is useful for applications requiring variable thresholds.

The low-power multi-sensor system with power management and nonvolatile memory access control for IoT applications are proposed, which achieves almost zero standby power at the no-operation modes. A power management scheme with activity localization can reduce the number of transitions between power-on and power-off modes with rescheduling and bundling task procedures. In addition, autonomously standby mode transition control selects the optimum standby mode of microcontrollers, reducing total power consumption. We demonstrate with evaluation board as a use case of IoT applications, observing 91 percent power reductions by adopting task scheduling and autonomously standby mode transition control combination. Furthermore, we propose a new nonvolatile memory access control technology, and estimate the possibility for future low-power effect.

In advanced technology nodes, bias temperature instability (BTI) has emerged as a prominent reliability concern. The worst-case effects of BTI occur during specific workload phases in which flip-flops (FFs) on a critical path do not switch their logic values for a long duration. These inactive FFs in the circuit experience accelerated workload-dependent static-BTI (S-BTI) stress. The aging effect of S-BTI for a few hours has been shown to be equivalent to one year of aging due to dynamic BTI, which can eventually cause circuit failure. The techniques available to mitigate S-BTI stress during standby mode of circuits are pessimistic, thereby limiting the performance of the circuit. To address this problem, we propose a runtime monitoring method to raise a flag when a timing-critical FF experiences severe S-BTI stress. To reduce the monitoring costs, we select a small representative set of FFs offline based on workload-aware correlation analysis and these selected FFs are monitored online for static aging phases. Our experiments conducted on two processors show that less than 0.5% of the total number of FFs is required to be selected as representative FFs for S-BTI stress monitoring. We also propose a low-overhead mitigation scheme to relax critical FFs by executing a software subroutine that is designed to exercise critical FFs.

Nonvolatile processors (NVPs) have strong vitality in battery-less energy-harvesting sensor nodes (EHSNs) due to their characteristics of zero standby power, resilience to power failures, and fast read/write operations. However, I/O and sensing operations cannot store their system states after power OFF; hence, they are sensitive to power failures and high power switching overhead is induced during power oscillation, which significantly degrades the system performance. In this paper, we propose a novel performance-aware task scheduling technique considering power switching overhead for energy-harvesting NVPs. We first present the analysis of the power switching overhead on EHSNs. Then, the scheduling problem is formulated by mixed-integer linear programming (MILP). Furthermore, offline and online performance-aware heuristic scheduling algorithms with the task splitting (TS) strategy are proposed to solve the scheduling problem efficiently. Experimental results show that comparing with the state-of-the-art energy-harvesting oblivious scheduling strategy, the proposed MILP scheduling approach can improve the performance by 16% on average, and the proposed scheduling algorithm with the TS strategy can reduce the average execution time by 24.8% and 22.5%.

This paper presents a high-swing vertical-cavity surface-emitting laser (VCSEL) driver with two-tap feed-forward equalizer (FFE) in 14-nm FinFET CMOS technology. The design features a standby mode with power-ON time below 10 ns and 86% of power saving. Based on system-level simulations, the impact of the driver swing, tap delay, and weight on the optical eye-opening is studied and it is shown that the FFE combined with high-swing driving can improve the output eye at rates beyond two times the bandwidth of the VCSEL. By applying an extra supply, the output stage is optimized to provide high swing (0.65 V) without suffering from the slow response of a transistor in the triode region. In addition, the bias and modulation currents can be adjusted to accommodate different VCSELs. The designed circuit is tested with two VCSEL types. It is bonded to common-cathode 20 and 18 GHz VCSELs, and in both the cases, data transmission at 45 Gb/s with bit error rate lower than 10−12 is measured. The total power dissipation is below 100 mW, providing a power efficiency of better than 2.11 pJ/bit. To the best of our knowledge, this design is the fastest VCSEL driver in any CMOS technology, which is also capable of burst mode operation.

Regenerative drives, also known as four-quadrant drives are an integral part of many industrial applications ranging from wind power generation, elevators, escalators, centrifuges, pump jacks in oil fields, etc. All regenerative converters need passive LCL filters to filter out pulsewidth modulation frequency components. One disadvantage of using an input LCL filter in front of regenerative converters is that they are also a major source of power loss in the power system as their configuration allows for the flow of capacitive circulating currents even when the power converter is off . The associated power loss in the power system can significantly affect the overall system efficiency when there are large numbers of large power regenerative units in the power system. The filter capacitors also interact with pre-existing voltage distortion in the power system. Multiple regenerative units of various sizes have been shown in this paper to cause undesirable voltage ripple, which in turn causes current oscillations especially in smaller sized regenerative converters. A new active damping scheme is proposed, which also includes actively opening the neutral point of the filter capacitor to eliminate standby power loss associated with regenerative converters with LCL filters. Two ideas are proposed. In the first, only one damping resistor is used, whereas in the other two, damping resistors are used in parallel, where one resistor acts as the fixed damping resistor whereas the other is modulated depending on the amount of system distortion. Test results are given to demonstrate the fundamental concept.

Power gating circuits are utilized to manage power consumption and thermal stress in microprocessors and other high-performance integrated circuits. Most of the power gating techniques utilize sleep transistors in different configurations to reduce the subthreshold leakage current, which is the primary source of the standby power. These sleep transistors, which are added between the supply lines and the circuits as header and footer switches, impose additional area, delay, power, and other overheads and complexities. This brief introduces the concept of combining the functionality of the sleep transistors with the logic devices by utilizing fully depleted silicon-on-insulator (FDSOI) device. This FDSOI transistor-based power gating circuit design approach will eliminate the requirement of employing a separate set of sleep transistors to place the circuit in the sleep or idle mode. This will reduce the overall complexity and overheads of integrated circuits and simplify power gating techniques. In addition, it improves the overall power efficiency and lower thermal effects. SOI devices are becoming critically important for various very-large-scale integration applications, because SOI devices provide higher performance and reliability, and options to design circuits with multiple-threshold voltages to ensure faster switching and lower power consumption. In the proposed circuit design approach, the flexibility to control the threshold voltage of a double-gate FDSOI device via back gate has been exploited to eliminate the need for using a separate set of sleep transistors. The presented sleep transistor design is verified via HSPICE simulation using the Leti-UTSOI model from CEA-Leti .

This paper proposes a new 10-transistor (10T) bitcell for robust operations at subthreshold voltages without any boost circuitry. Features of the proposed bitcell include: 1) differential pre-discharged bit-lines and a pair of decoupled access ports to resist disturbance; 2) footed latch for write assist; 3) spare latch-foot to fight against half-select disturbances; and 4) highly stacked pull-down structure to reduce both leakage and power. A bit-interleaved SRAM macro, constructed with the proposed 10T bitcell, is fabricated in 28 nm CMOS. The power consumption has been measured as 90 nW for 30 kHz access at 0.25 V, and 41 nW for retention at 0.20 V, of which the leakage is 31% better than the state-of-the-art design.

Spin-torque-transfer RAM (STTRAM) is a promising technology for high density on-chip cache due to low standby power and high speed. However, the process variation of STTRAM poses serious challenge to sensing. We propose a non-destructive and low-power sensing scheme that exploits a voltage feedback and boosting technique to develop large sense margin. Monte Carlo simulation results in ST Microelectronics 65-nm technology show that the proposed sensing circuit achieves 807-mV worst case sense margin on average, read access pass yield of $14.4\sigma $ in typical corner and $4.7\times $ reduction in read power compared to conventional voltage sensing.