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Well isolated 72 nm pitch hexagonal honeycomb magnetic tunneling junction (MTJ) array with about 45 nm MgO CD was successfully fabricated on a DRAM platform by using mature DRAM array patterning solution with self-aligned double patterning technology and proposed triple hard mask scheme. The 72 nm pitch MTJ array had an equivalent cell size as small as $0.0044~\mu \text{m}$ 2, the world’s smallest pitch size and cell size for industrial MTJ array to our knowledge. The hexagonal array geometry offered considerably merit for storage density enhancement and MTJ etch convenience. A reactive ion etch (RIE) and ion beam etch (IBE) combined MTJ etching solution was adopted to optimize pillar isolation and mitigate metallic re-deposition and etch damage. Perpendicular magnetic anisotropy was maintained in MTJ array; however, free layer coercivity was smaller than expected, indicating the existence of etch damage or fringe magnetic field interaction. Potential challenges for the chip integration of high-density hexagonal MTJ array are also discussed.

The enhanced surface area of silicon nanotexture is an important metric for solar cell integration as it affects multiple properties including optical reflectance, dopant diffusion, and surface recombination. Silicon nanotexture is typically characterized by its surface-area-to-projected-area ratio or enhanced area factor (EAF). However, traditional approaches for measuring EAF provide limited statistics, making correlation studies difficult. In this article, silicon's dominant ultraviolet reflectance peak, R(E2), which is very sensitive to surface etching, is applied to EAF spatial mapping. A clear decay correlation between R(E2) and EAF is shown for multiple textures created using reactive ion etching and metal catalyzed chemical etching. This correlation is applied to R(280 nm) reflectance mapping to yield accurate, high-resolution full-wafer EAF spatial mapping of silicon nanotextures. R(280 nm) mapping is also shown to be sensitive enough to correlate the impact of nanotexture spatial variation on post-diffusion sheet resistance. Finite-difference time-domain simulations of several nanoscale pyramid textures confirm a decay band for R(E2) versus EAF, consistent with our measurements. We suggest that R(E2) mapping may prove useful for other silicon nanotexture properties and applications where EAF is important.

In this work, thermally evaporated aluminum (Al) was used as hardmask (HM) to obtain silicon microchannels (SiMCs), using an Inductively Coupled Plasma - Reactive Ion Etching (ICP-RIE) system, in SF6/Ar gas mixture environment. The channel depth must be greater than $50~\mu \text{m}$ , with a high aspect ratio. For this, Al HM lines were defined by photolithography and by Al wet etching on a silicon substrate. To improve the resistance against the ICP-RIE etching process, the Al HMs were treated with four different conditions: i) Al HM without treatment step (control sample); ii) with plasma nitridation (AlN/Al structure); iii) with thermal annealing (annealed Al film); iv) with plasma nitridation and annealing (annealed AlN/Al structure). After 100 min of ICP-RIE etching process, SiMC with depths of $90.6~\mu \text{m}$ , $95~\mu \text{m}$ , $91.2~\mu \text{m}$ , and $109~\mu \text{m}$ , respectively, were measured using a scan profiler system. As the main result, the annealed AlN/Al structure presented a high resistance against the ICP-RIE etching for 100 minutes. Furthermore, Scanning Electron Microscopy (SEM) images indicate an etch uniformity on the walls and bottom of the channels for all the samples. This parameter is a mandatory requirement to obtain the integrated microchannel liquid-cooling technology for heat sinks in photovoltaic cells and Complementary Metal-Oxide-Semiconductor microprocessors. [2021-0020]

A comprehensive study of drain current dispersion effects in $\beta $ -Ga2O3 field-effect transistors (FETs) has been done using dc and pulsed measurements. Both the virtual gate effect in the gate–drain access region and mobile traps under the gate are the most plausible explanations for the experimentally observed pulsed current dispersion and high-temperature threshold voltage shift, respectively. Unpassivated devices show significant current dispersion between dc and pulsed ${I}$ – ${V}$ response in gate lag measurements characterized by time constants in the range of 400–690 $\mu \text{s}$ both at room temperature and higher temperatures. The increasing time constant with temperature suggests a complex electron capture and emission process in the virtual gate. The reactive ion etching step during the device fabrication is most likely responsible for introducing the traps. The effect of traps can be minimized by using surface passivation layers, in this case, silicon nitride, which shows significant improvement in the current dispersion. This work demonstrates the detrimental effect that the traps can have on the current dispersion, which significantly limits the high-frequency operation of the device.

Blazed gratings are widely used in optical detection devices with the unique property of concentration of light energy to a desired diffraction order. However, traditional substrates for fabricating blazed gratings are easily damaged with the wear and tear in long-term usage under harsh conditions. Here, we propose the fabrication of blazed gratings on sapphire with high mechanical stability by femtosecond laser lithography combined with subsequent reactive ion etching (RIE). Various sapphire blazed gratings with periods from 2 μm to 10 μm and heights from 260 nm to 2 μm were realized to concentrate light energy (wavelengths of 405 nm, 532 nm and 633 nm) to different diffraction orders (1st, 2nd, and 3rd). The results provide great insights for the construction of micro-optical devices that have potential applications under harsh conditions.

Light- and elevated temperature-induced degradation (LeTID) of silicon wafers reduces the energy yield of photovoltaic modules in the field. A previous study demonstrated that this degradation is greatly reduced in samples with a surface textured with black silicon formed via reactive ion etching. However, the reason for this reduction is currently not understood. This article extends that result to a range of nano-textures formed using commercial metal-catalyzed chemical etching. Lifetime test structures are fabricated on multicrystalline wafers with six different chemical nano-textures and the results are compared to planar reference samples. The article demonstrates a reduction in the extent of light-induced degradation compared to planar reference samples for all six textures. The extent of LeTID is observed to reduce with decreasing front surface reflectance and increasing front surface area. The article finds that wafer thickness, phosphorus gettering, and fast-firing cannot explain the result.

Etched-and-regrown GaN pn-diodes capable of high breakdown voltage (1610 V), low reverse current leakage (1 nA = 6 $\mu \text{A}$ /cm2 at 1250 V), excellent forward characteristics (ideality factor ~1.6), and low specific on-resistance (1.1 $\text{m}\Omega $ .cm2) were realized by mitigating plasma etch-related defects at the regrown interface. Epitaxial ${n}$ -GaN layers grown by metal-organic chemical vapor deposition on free-standing GaN substrates were etched using inductively coupled plasma etching (ICP), and we demonstrate that a slow reactive ion etch (RIE) prior to ${p}$ -GaN regrowth dramatically increases diode electrical performance compared to wet chemical surface treatments. Etched-and-regrown diodes without a junction termination extension (JTE) were characterized to compare diode performance using the post-ICP RIE method with prior studies of other post-ICP treatments. Then, etched-and-regrown diodes using the post-ICP RIE etch steps prior to regrowth were fabricated with a multi-step JTE to demonstrate kV-class operation.

We fabricated a quadruple-interface perpendicular magnetic tunnel junction (MTJ) (Quad-MTJ) down to 33 nm using physical vapor-deposition, reactive ion etching, and damage-control integration process technologies that we developed under a 300-mm process. We demonstrated the greater scalability and higher writing speed of Quad-MTJ compared with double-interface perpendicular MTJ: 1) it has twice the thermal stability factor—1X nm Quad-MTJ can achieve 10 years retention—while maintaining a low resistance-area product and high tunnel magnetoresistance ratio; 2) smaller overdrive ratio of write voltage to obtain a sufficiently low write-error rate; 2) smaller pulsewidth dependence of the switching current; and 4) more than double the write efficiency at 10-ns write operation down to 33-nm MTJ. The effective suppression of the switching current increase for higher write speeds was explained by the spin-transfer-torque model using the Fokker-Planck equation. Our 33-nm Quad-MTJ also achieved excellent endurance (at least 1011) owing to its higher write efficiency and low-damage integration-process technology. It is thus a promising method for low power, high speed, and reliable STT-MRAM with excellent scalability down to the 1X nm node.

We present the nanofabrication and transport properties of single silicon nanowires (NWs) having mean widths in the range from sub-30 to 500 nm. Hall effect measurements are undertaken in the magnetic fields of 14 T at 300 K. The NWs are defined by electron-beam lithography (EBL) using the negative tone resist hydrogen silsesquioxane (HSQ) as a mask for reactive ion etching (RIE). Silicon NWs are patterned on nonuniform highly doped n-type silicon-on-insulator (SOI) substrates. The doping profile has been observed to show a significant effect on the NW electrostatics, which in turn influences the contact and transport properties of the NWs. For the formation of Hall electrodes, we have employed an angled substrate evaporation technique, where the NW itself is used as a shadow mask and an intimate sidewall contact has been formed. The Hall electrodes are not opposite to each other in this case; therefore, the longitudinal resistance pickup had to be considered when extracting the Hall signal of the NW. The mobility of these NWs is discussed. For the narrowest 40-nm-wide silicon NW, the obtained value of mobility is 292 ± 6 cm2/Vs and, for the blanket, nonpatterned device layer, it is 100 ± 0.1 cm2/Vs. The effective mobility increases as the width of the NWs decreases. This is attributed to the reduced dimensionality of the electron transport in the NWs. Both the electrical and effective thicknesses of the NW change at small physical width, which results in enhanced electron transport within the channel and enhances the value of the measured Hall signal.

We introduce a deep-recessed gate architecture in $\beta $ -Ga2O3 delta-doped field-effect transistors (FETs) for improvement in dispersion and breakdown properties. The device design incorporates an unintentionally doped (UID) $\beta $ -Ga2O3 layer as the passivation dielectric. To fabricate the device, the deep-recess geometry was developed using BCl3 plasma-based etching at ~5 W reactive ion etching (RIE) power to ensure minimal plasma damage. Etch damage incurred with plasma etching was mitigated by annealing in vacuum at temperatures above 600 °C. A gate-connected field-plate edge termination was implemented for efficient field management. Negligible surface dispersion with lower knee walkout at high ${V}_{{\text {DS}}}$ , and better breakdown characteristics compared to their unpassivated counterparts were achieved. A three-terminal OFF-state breakdown voltage of 315 V, corresponding to an average breakdown field of 2.3 MV/cm was measured. The device breakdown was limited by the field-plate/passivation edge and presents scope for further improvement. This demonstration of epitaxially passivated FET is a significant step for $\beta $ -Ga2O3 technology since the structure simultaneously provides control of surface-related dispersion and excellent field management.

Silicon nanoporous membranes provide the fundamental underlying technology for the development of an implantable bio-artificial kidney. These membranes, which are comprised of micromachined slit-pores that are nominally 10 nm wide, allow for high-efficiency blood filtration as well as immunoprotection for encapsulated cells. Our approach takes advantage of well-established semiconductor fabrication technology to give us precise dimensional control over pore widths, thereby enabling a highly selective filtration function and a clear path towards further miniaturization. This work builds on our prior results on “ribbed nanoporous membranes” by adding a second-level hierarchy of significantly taller “mega-ribs” to further strengthen the membranes. Relying on a two-step Deep Reactive Ion Etch (DRIE) process, we etch $4~\mu \text{m}$ -deep as well as $40~\mu \text{m}$ -deep trenches into a silicon substrate, grow a thermal oxide liner, and deposit a layer of polysilicon into this “mold” to form membranes which, when released after a backside DRIE etch, feature a network of reinforcing ribs on the underside. We have fabricated and tested freestanding membrane spans that are up to 14 times wider than before, with approximately double the measured permeability per unit area. The new architecture can also improve cross-membrane mass-transfer rates and reduce chip-fabrication costs. [2020-0170]

This article reports a novel work on the fabrication of microarrays of electrospun Poly(vinylidene fluoride) (PVDF) membrane for MEMS and energy harvesting applications. Micropatterning of PVDF membrane is an essential step in fabrication process in order for the sample to be integrated in microelectromechanical systems. The high $\beta $ -phase fraction of PVDF membranes was successfully synthesized by one step electrospinning technique. A new fabrication process for micropatterning of electrospun PVDF membrane is being proposed using dry reactive ion etching. Oxygen plasma was chosen as the feeding gas in investigation for high etching rate in PVDF microstructure fabrication process. Micropatterning dimensions of 200/500/ $200~\mu \text{m}$ with the height of over $50~\mu \text{m}$ and etching rate of $2~\mu \text{m}$ /min were achieved in this work. Details of the fabrication process are discussed. High etching rate of patterning process with the selected parameters can be achieved on the electrospun PVDF membranes. This work has demonstrated successful micropatterning and integration of PVDF membrane into MEMS, thus open the possibilities for various application such as for sensors and actuators utilizing polymer membrane. We have validated the capability of the micropatterned device as energy harvester in producing an open circuit voltage density of 1.42 $\text{V}\cdot \text{m}^{{-2}}$ at temperature of 310.15 K and wind speed of 1 $\text{m}\cdot \text{s}^{{-1}}$ . [2019-0180]

Reactive Ion Etching (RIE) of Cytop as the cladding material for optical waveguides and microfluidic channels is investigated. Different grades of Cytop (M, A and S), different mask materials including photoresist and metals, different RIE parameters, along with different substrate materials were investigated. Grass-like structure was observed at the bottom of etched channels, of height that depends on the etching process parameters. A comprehensive post-etch acid cleaning procedure was devised to effectively remove the grass structure. [2019-0232]

We have proposed a novel quad-interface magnetic tunnel junction (MTJ) technology which brings forth an increase of both thermal stability factor $\Delta $ and switching efficiency defined as the ratio of $\Delta $ to intrinsic critical current ${I}_{\text {C0}}$ ( $\Delta /{I}_{\text {C0}}$ ) by a factor of 1.5–2 compared with the conventional double-interface MTJ technology. The free layer of the developed quad interface consists of bottom-MgO/FL1/middle-MgO/FL2/top-MgO stack structure. We successfully fabricated the quad-interface MTJ using a 300-mm process based on a novel low-damage integration process including physical vapor deposition (PVD), reactive ion etching (RIE), and so on. By developing the quad-interface MTJ, we have achieved about two times larger $\Delta $ and $\Delta /{I}_{\text {C0}}$ at the same time. Moreover, we have achieved about two times larger tunnel magnetoresistance (TMR) ratio at the same resistance area (RA) product by developing the FL1, bottom-MgO, and middle-MgO. The developed quad-interface MTJ technology considered as post-double-interface MTJ technology will become an essential technology for the scaling of the spin-transfer-torque magnetoresistive random access memory (STT-MRAM) beyond 20 nm.

This paper reports the development of fiber optical hydrogen sensors using palladium and gold alloy nanostructures as sensor materials for hydrogen measurements using a D-shaped fiber as a platform. Using a maskless reactive ion etching technique, silica nanocone structures were formed on the surface of the D-shaped fiber. Palladium and gold alloys were deposited on the surface of nanostructured D-shaped fiber to form a nano-alloy sensor film. Evanescent interaction between guided light propagated in the fiber core and nano-alloy enabled highly sensitive hydrogen detection from concentrations that ranged from 0.25% to 10% in atmosphere pressure. The formation of nanostructured alloy enabled by the nanocone surface led to more than 3 times faster in sensor response time and significant improvements in sensor sensitivity and reversibility. The work presented here demonstrates that highly controllable VLSI microfabrication schemes can be applied to produce nanostructured sensor films on optical fibers for high-sensitivity chemical sensing.

Superconducting microwave resonators are important components of superconducting quantum information and astronomy detector systems. In this paper, we show how to modify the microwave resonator performance after fabrication through surface engineering. In particular, we focus on titanium nitride (TiN)/silicon (Si) resonators because they have shown potential for achieving high-quality factors $(\text{Q}_{i}\text{s})$ . Depending on the type of surface treatment, chemical- or plasma-based, we found $\text{Q}_{i}\text{s}$ that vary by approximately a factor of 18. We used inductively coupled plasma (ICP) combined with reactive ion etching (RIE) for the plasma surface treatment. We found that the microwave resonator performance depends on the type of plasma environment, such as single gas (oxygen) or gas mixtures [argon/hydrogen (Ar/H2), argon/octafluorocyclobutane (Ar/C4F8), and argon/sulfur hexafluoride (Ar/SF6)], and the plasma processing conditions, such as treatment time, ICP power, and RIE power. Of the plasma surface treatments, the Ar/SF6 environments with no or low ICP power showed the highest potential to improve $Q_{i}$ . The processing conditions determined the chemistry and roughness of the Si and TiN surfaces, TiN film thickness, and the overall TiN/Si resonator structure (edge and sidewall). Our results can be used as a guideline for optimizing the microwave resonator performance using surface treatments.

An active matrix light emitting diode (LED) micro-display system was demonstrated with GaN-on-Si epilayers and a custom-designed CMOS backplane using an Au-free Cu/Sn-based metal bonding method. The blue micro-LED array consists of $64\times36$ pixels with a pitch size of $40\,\,\mu \text{m}\,\,\times 40\,\,\mu \text{m}$ and a pixel density of 635 pixels/in (ppi). The Si substrate for the LED growth was removed by reactive ion etching (RIE) using SF6-based gas after flip-chip bonding. Crack-free and smooth GaN layers in the display area were exposed. Images and videos with 4-bit grayscale could be clearly rendered, and light crosstalk was significantly suppressed compared to its counterpart using the GaN-on-sapphire epilayers. The demonstration suggests the tremendous potential of the low-cost and large-scale GaN-on-Si epilayers and cost-effective Au-free Cu/Sn-based bonding scheme for micro-display applications.

In this paper, we report on the fabrication and high performance of power p-n diodes grown on free-standing (FS) GaN substrate. The key technique to enhance the high breakdown voltage and suppress the surface leakage current is the isolation process. The mesa-structure diode is generally formed by utilizing the inductively coupled plasma reactive ion etching; however, it always induces high surface damages and thus causes a high leakage current. In this paper, we propose a planar structure by employing the oxygen ion implantation to frame the isolation region. By following the crucial process, the fabricated mesa- and planar-type diodes exhibit the turn-on voltages of 3.5 and 3.7 V, specific on-resistance ( $\text{R}_{\mathrm{ ON}}\text{A}$ ) of 0.42 and 0.46 $\text{m}\Omega $ -cm2, and breakdown voltage ( V B) of 2640 and 2880 V, respectively. The corresponding Baliga’s figures of merit (BFOM, i.e., V $_{B}^{2}/\text{R}_{\mathrm{ ON}}\text{A}$ ) are 16.6 and 18 GW/cm2, respectively. The BFOM of 18 GW/cm2 is the highest reported value for FS-GaN diode. From the temperature dependent measurements, the planar-type diode also shows the better leakage current and thermal stability than the mesa-type diode.

In this letter, nanowire forests are prepared by using a plasma repolymerization technique. The preparation process involves only a spin-coating step of polyimide and plasma bombardment of the polymer, the entire process is lithography-free, micromachining-compatible, fast, and extremely simple. Moreover, the nanowire forests can further be utilized as nanomasks in reactive ion etching of silicon for nanowire–nanopillar composite forests. Optical features of the nanowire forests and the nanowire–nanopillar composite forests in different wavelength regions are fully investigated. High transmission of the nanowire forests in a visible-light range implies applications of such forests in transparent devices. A specific absorption peak in a range of 8–10 μ m indicates applications of the composite nanoforests in infrared devices for certain substance sensing.

This paper develops and characterizes a three-dimensional (3-D) nanofabrication process using ultrasonic vibration assisted nanomachining based on an atomic force microscope (AFM). The superiorities of height control over force control in the process are explained and are demonstrated by the fabrication results. Three factors impacting actual feature depths are investigated, including the ultrasonic z -vibrational amplitude, the assigned base feature depth, and the machining speed. 3-D nanostructures with continuous height variations were successfully fabricated on polymethyl methacrylate (PMMA) films with the feature height manipulated through controlling the absolute height of the cantilever tip in AFM. By selecting machining parameters based on characterizations, feature dimensions can be controlled as desired values within small variances. The capability of transferring 3-D nanostructures from PMMA films to silicon substrates is further explored in this paper. After selecting recipes of the reactive ion etching process, 3-D nanostructures are successfully transferred to silicon substrates with controllable selectivity. The reported ultrasonic vibration assisted nanomachining process in height control provides a robust approach of fabricating 3-D nanostructures.

The paper introduces a 24-channel air-trench isolated Silica-based VOA array. The air trenches thermally insulate the VOAs with etched-free waveguide technologies. Reactive ion etching and wet etching were used at different channel locations to suppress thermal crosstalk and reduce power consumption. When thermal crosstalk is declined by 3 dB for the straight waveguide, the power consumption was decreased from 195 to 95 mW because the lightwave radiation can be scattered by the air trench in the dark state. This crosstalk is improved by 9 dB for the curved waveguide. The polarization dependent loss falls down to 0.28 dB at 15 dB attenuation since the air trench and etched-free waveguide also releases the stress.

An electrostatic bi-stable $4\times 4$ micro-mirror array is implemented by using the standard Advanced Semiconductor Manufacturing Corporation 0.35- $\mu \text{m}$ 2-Poly-3-Metal fabless complementary metal-oxide-semiconductor microelectromechanical systems (CMOS-MEMS) process. Mechanical structures, including mirrors $(18 ~\mu \text {m} \times 18 ~\mu \text{m}$ in area each), electrostatic actuation mechanisms, and the suspensions, are made in the top three metal layers. Typical static pull-in voltage is tested to be 49 V and the maximum tilt angle is estimated to be 14.6°. The micro mirror can be operated at frequencies upward of 11 kHz at least. Total lifetime of more than 134.5 h, $4.8\times 10^{9}$ cycles, is tested. To avoid stiction during the process, the micro-mirror array is sacrificial-released from the substrate after the CMOS process by using reactive ion etching (RIE) and photoresist-assisted wet etching. Micro-mirror-wise processing yield of 99.3% after the release implies the robustness of the developed CMOS-MEMS process. [2017-0180]

Aerosol deposition (AD) method is technique for forming high density ceramic films on substrate material surface at room temperature. The yttrium oxide films formed by the AD method (AD-Y2O3 films) have been developed as plasma resistance coating used for the plasma etching equipment. In recent years, plasma eroded particles from chamber components of the etching devices are regarded as a serious issue that they reduce the semiconductor device yield rate. AD-Y2O3 films which have excellent plasma resistance can reduce the eroded particles in the plasma etching equipment and greatly have contributed to manufacturing high integrated semiconductor devices. In this paper, the plasma erosion behavior of AD-Y2O3 films were investigated compared with sintered Al2O3, sintered Y2O3 and thermal splayed Y2O3 in order to clarify the reason why AD Y2O3 films were superior as plasma resistance material. The plasma etching rates of AD-Y2O3 films were not significantly different from other samples. It was assumed that the etching rates were dependent on the chemical stability to fluorine plasma of material. On the other hand, the surface roughness difference before and after plasma exposure of AD-Y2O3 films were much smaller than other samples. It was assumed that the surface roughness difference is dependent on the crystalline size of material. The structure of AD-Y2O3 films, which had high density and nano-crystalline structure, were eroded homogeneously and smoothly. It suggests AD-Y2O3 films do not generate large eroded particles and are superior to reduce the eroded particles in the etching devices.

The critical dimension (CD) is highly influenced by the reactive ion etching (RIE) of silicon in the CMOS technology. The CD has to be well-controlled since it is one of the most important features related to process stability and product quality. However, the RIE process involves a lot of parameters which are highly confounded and entangled and thus it is very difficult to analyze the process. To study and extract the influences of these parameters in terms of CD variation, screening experiments are carried out to obtain the necessary factors to develop a CD-related model. An elaborated model, based on the selected parameters, is then built up via applying the design of experiments and response surface optimization. This model is validated to be capable of characterizing the process as well as predicting the CD.

This paper presents the design, fabrication, and characterization of piezoelectric micromachined ultrasound transducers (PMUTs) based on scandium aluminum nitride (ScxAl1–xN) thin films (x = 15%). ScAlN thin film was prepared with a dual magnetron system and patterned by a reactive ion etching system utilizing chlorine-based chemistry with an etching rate of 160 nm/min. The film was characterized by X-ray diffraction, which indicated a crystalline structure expansion compared with pure AlN and a well-aligned ScAlN film. ScAlN PMUTs were fabricated by a two-mask process based on cavity SOI wafers. ScAlN PMUTs with 50- and 40- $\mu \text{m}$ diameter had a large dynamic displacement sensitivity measured in air of 25 nm/V at 17 MHz and 10 nm/V at 25 MHz, twice that of AlN PMUTs with the same dimensions. The peak displacement as a function of electrode coverage was characterized, with maximum displacement achieved with an electrode radius equal to 70% of the PMUT radius. Electrical impedance measurements indicated that the ScAlN PMUTs had 36% greater electromechanical coupling coefficient ( $\text{k}_{\mathrm {t}}^{2})$ compared with AlN PMUTs. The output pressure of a $7\times7$ ScAlN PMUT array was 0.7 kPa/V at ~1.7 mm away from the array, which is approximately three times greater that of an $8\times8$ AlN PMUT array with the same element geometry and fill factor measured at the same distance. Acoustic spreading loss and PMUT insertion loss from mechanical transmit to receive were characterized with a 15 $\times $ 15 ScAlN PMUT array via hydrophone and laser Doppler vibrometer. [17509-2017]

We develop a process of fabricating silicon waveguides and devices using a bulk silicon substrate. The fabrication process mainly consists of one silicon dry etching and one silicon wet etching. The use of silicon wet etching makes the process simple and inexpensive. Because of the anisotropic nature of silicon wet etching, the bulk-silicon-based (BSB) waveguide made by the process consists of an inverted-trapezoidal core on a rectangular pedestal and a trapezoidal base beneath the pedestal. In addition, geometrically smooth BSB waveguide bends can be achieved when the radii of curvature of the bends are sufficiently large. The propagation loss of the BSB waveguide depends on wet etching conditions and it is 4.0 or 0.79 dB/cm for transverse-magnetic polarization. It is confirmed that the minimum radius of curvature of the BSB waveguide bend is 500 μm. The BSB waveguides and bends are expected to be used to implement low-cost sensors with simple geometry.

In this paper, we demonstrate novel texturing technologies developed for diamond wire sawn multicrystalline silicon wafers. SEM analysis shows that inverted pyramid like texture is produced on the wafer surface by a combination of reactive ion etching and metal-assisted chemical etching technologies. The inverted pyramid like textured surface shows remarkable antireflection performance over the other two types of texturing technologies. Screen-printed passivated emitter rear contact cells are fabricated to illustrate the effect of different texturing on cell performance. The cells with inverted pyramid like texture show the highest batch average efficiency of 20.51%, with the best efficiency of 20.69%. Detailed performance parameters and quantum efficiency for each type of cells are shown in the paper. Quantum efficiency simulations are also performed based on the reflectance and control parameters measured during the cell fabrication process. In addition, light-induced degradation of the cells is also analyzed.

Test structures were developed to visualize the progress of the dry release of an MEMS device fabricated by deep reactive ion etching (DRIE). Because of the high aspect ratio of DRIE MEMS devices, the undercut progress cannot be observed from the surface. Therefore, a destructive test, i.e., a cross-sectional-view observation of a cleaved sample, has mostly been employed. Using the proposed test structure, the progress of the silicon undercutting can be evaluated in a nondestructive manner, using only an optical microscope. The test structure was not only found to be useful in optimizing the release etching procedure, but also allows us to discover a particular DRIE mode that is useful for dry release. Indeed, most DRIE process engineers have considered and mainly tuned the etching phase; using the test structures, we found that the deposition phase of DRIE can be strategically used to further increase the undercutting speed. The new mode, referred to as the “undercut directional etching mode,” intentionally leaves a fluorocarbon layer for protection of the side-wall, at the bottom center of the trench openings. Because of the deposition layer remaining at the bottom center, the introduced plasma species are concentrated towards the edge of the trench, i.e., at the foot of silicon structure to be released, thereby enhancing the undercut etching. A second test structure identified the appearance of the new mode and visualized the dependence of the etching behavior on the trench opening width. The optimized etching conditions determined using the test structures led to the successful release of a standard in-plane MEMS device.

This paper presents a metal-assisted chemical etching (MACE) method for high aspect silicon structures. Ultrahigh aspect trenches and pillars of 400 and 80, respectively, have been achieved using MACE. A survey of the MACE method investigated the etching time, pattern sizes, and concentration of etching solution. In addition, a comparison of the etching methods related to the etching depth, surface roughness, and aspect ratio structure, etc., between the deep reactive ion etching and MACE methods has been reported. A simple method for cantilever fabrication has been proposed and demonstrated. Cantilever-based pillars fabricated by MACE were successfully produced via an assembly technology. The pillars were assembled onto a glass substrate and fixed with a conductive glue. The fabricated cantilever showed a resonance frequency of 235 kHz and a quality factor of 800.

Spin-on polyimide is an organic thin film often used as a sacrificial layer for surface micromachining due to its high thermal stability, ease of removal, and compatibility with many materials and processes used in the realization of microelectromechanical systems (MEMS). The incorporation of sloped sidewalls in polyimide for fabricating pedestal structures is crucial in order to provide strong anchors in free-standing MEMS devices, especially in cases having a high aspect ratio and/or where structural materials have limited deposition conformality. This paper demonstrates a reliable reactive ion etching (RIE) methodology for tuning the polyimide sidewall angle, ranging from a vertical sidewall up to an angle of about 25° from the vertical. The key modifications to the process parameter space include changes to the process temperature and chamber pressure. This paper also presents a novel lift-off process, which is based on the use of an interfacial polymer layer to facilitate removal of an overlying silicon oxide hard mask. This procedure allows polyimide sacrificial layers employing a silicon oxide hard mask to be used on samples that have exposed silicon oxide layers elsewhere on the chip that are required to remain intact during hard mask removal. Therefore, this lift-off process is applicable in situations where the silicon oxide hard mask removal cannot be accomplished by wet etching in hydrofluoric acid solutions.

In this work, Si nanostructure arrays are fabricated using a low-cost chemical/electrochemical etching method. The technique consists of two consecutive chemical and electrochemical etching steps. A mask-less and nonlithographical technique of anisotropic wet etching of silicon samples in hydroxide solutions was used to generate pyramid shape seeding points. The subsequent fabrication stages consist of electrochemically etching to generate nanowires. The growth mechanism of the nanowires was investigated experimentally in order to find out the effects of various fabrication parameters on the physical properties of the nanowires like their structures, shapes, sizes, aspect ratio, and morphologies. Modeling and simulation of the nanowires growth are performed using multiphysics software tool, COMSOL, in order to explain and confirm the experimental results.

This paper reports research performed on developing and optimizing a process recipe for the plasma etching of deep high-aspect ratio features into fused silica (fused quartz) material using an inductively coupled plasma reactive-ion etch process. As part of this effort, we performed a design of experiments (DOE), wherein the etch recipe parameters having the most impact on the etch process were varied over fixed ranges of predetermined values, while the other etch recipe process parameters were unchanged. Subsequently, the etched samples were analyzed so as to quantify the etch outcomes. Using the experimental data collected during the DOE, we then performed multiple regression analysis on this data to determine optimal etch tool parameters in order to achieve the desired etch results. Based on this work, we have demonstrated the ability to etch very deep features into fused silica of over 100 microns, having nearly vertical sidewalls, and with aspect ratios of over 10 to 1 using the optimized etch process. The ability to fabricate deep high-aspect ratio features into fused silica has important implications for a number of micro-electromechanical systems applications. The etch technology developments presented herein are applicable to fused silica, as well as to other silicon-dioxide-based materials including crystalline quartz. [2015-0253]

The historical and technological development of the ubiquitous trench power MOSFET (or vertical trench VDMOS) is described. Overcoming the deficiencies of VMOS and planar VDMOS, trench VDMOS innovations include pioneering efforts in reactive ion etching and oxidation of the silicon trench gate, polysilicon fill and recessed etchback, unit cell and distributed voltage clamping to protect the trench gate, and scaling active cells to high densities using deep submicron fabrication. Thereafter, gate–drain engineered trench VDMOS improved high-frequency switching capability with lower gate charge utilizing nonuniform gate oxides, field shaping, and charge balancing (superjunction, RSO) methods. The recent adaptation of trench gates in wide bandgap unipolar devices is also described.

An integrated optical design of a rectangular-edge filter device in 250-nm silicon-on-insulator platform is proposed and demonstrated experimentally. The device is designed with a multimode waveguide (supporting at least two modes) with asymmetric side-wall grating, which is adiabatically interfaced with input/output single-mode waveguides. The input/output access waveguides are terminated with grating couplers for optical characterizations. Design parameters are optimized for a sharp-edge or nearly rectangular-edge filter response in optical C-band (1530 nm $\leq \lambda _{\text{edge}} \leq $ 1565 nm). The submicron features and the entire footprint of the devices were defined with a single-step e-beam lithography process by using negative-tone resist and subsequent dry etching of $\sim$ 100 nm by using an inductively coupled reactive ion etching system. All the fabricated devices exhibit a rectangular-edge filter response at $\lambda _{\text{edge}} \sim $ 1560 nm with an edge-extinction of $>$ 40 dB at the rate of 118 dB/nm. The rectangular-edge is followed by a broad pass-band of $\sim $ 40 nm till the first-order Bragg reflected wavelength of $\lambda _B^{00} \sim $ 1600 nm in the transmission characteristics obtained for 1520 nm $\leq \lambda \leq$ 1620 nm. Tunability of a rectangular-edge filter is verified with cladding refractive index change and the observed refractive index sensitivity of the edge is $\sim$ 18 nm/RIU. The limit of detection for 1-dB transmitted power extinction at $\lambda _{\text{edge}}$ of a typical fabricated device is estimated to be 5.3 $\times\, \text{10}^{-4}$ RIU.

The performance of an on-chip X-band (8–12 GHz) inductor, integrated with a partially-inverted zinc ferrite (piZF) film, is presented. The ferrite-core inductor is realized in three steps—first, fabrication of an uncoated spiral inductor via a 130 nm Si-CMOS process in a foundry, followed by passivation removal around the coil by reactive ion etching (RIE), and finally, deposition of piZF directly on the coil by microwave-assisted solution-based processing. The resulting piZF film covers the inductor coil conformally and exhibits high saturation magnetization ( ${M}_{\mathrm{S}}=130$ emu/cm $^{3})$ and very low coercivity ( ${{H}}_{\mathrm{C}} Oe) at room temperature. The ferromagnetic resonance frequency ( $f_{FMR})$ of piZF was determined by the coplanar-waveguide ferromagnetic-resonance technique to be ${\sim}$ 30 GHz, well above the frequency of targeted X-band applications. The inductance-density and Q -factor of the piZF-coated inductor are enhanced by 13% and 25% to 450 nH/mm $^{{2}}$ and 5.8, respectively, at 10 GHz. This is the first report of an on-chip ferrite-core RF inductor operating above 6 GHz.

The investigated N-channel power vertical double-diffused metal-oxide-semiconductor field-effect-transistor (power VD MOSFET) suffered a drain-to-source current leakage ( $IDSS$ leakage). The leakage was caused by the dislocations located mainly in the N+ source area in the vicinity of the edge of the polycrystalline silicon gate. The stress induced by temperature gradients during wafer insertion into a furnace, its withdrawal from a furnace, and plasma damage were assumed to be the potential causes of the occurrence of dislocations. Inserting a wafer into a furnace and withdrawing it from a furnace at a slower pace during the steps of a high-temperature process' showed only a negligible suppression of the $IDSS$ leakage. The plasma etching of the polycrystalline silicon gate by $HBr$ (instead of the standard $SF_{6}$ ) changed the pattern of $IDSS$ failing transistors across a wafer (from the edge ring to continuous coverage), but the leakage was not suppressed. The $IDSS$ leakage was completely eliminated by the 5-s shorter plasma-etching time (from 21 to 16 s) of the P+ implantation screen oxide. The plasma damage generated by the long etching time of the P+ implantation screen oxide was determined as the root cause of the occurrence of dislocations.

The electrical performances of gate-recessed AlGaN/GaN high-electron mobility transistors (HEMTs) fabricated using the damage-free neutral beam etching (NBE) method are demonstrated. The NBE method could eliminate the plasma-induced defects generated by irradiating ultraviolet/VUV photons in the conventional inductively coupled plasma reactive ion etching method. The AlGaN/GaN HEMT device fabricated using the new gate recess process exhibited superior electrical performances, including a maximum drain current density ( ${I}_{\mathrm {DS,max}}$ ) of 1.54 A/mm, low $1/f$ noise, a current-gain cutoff frequency ( ${f}_{\mathrm {T}}$ ) of 153 GHz, a maximum frequency of oscillation ( ${f}_{\mathrm {{MAX}}}$ ) of 167 GHz, and a minimum noise figure (NF $_{\mathrm {{min}}}$ ) of 3.28 dB with an associated gain ( ${G}_{\mathrm {{AS}}}$ ) of 5.06 dB at 54 GHz. Such superior characteristics confirm the inherent advantages of adopting the damage-free NBE process in fabricating GaN devices for millimeter-wave applications.

This paper presents an application of reactive ion etching followed by diamond-like carbon nanooverlay deposition using radio frequency plasma-enhanced chemical vapor deposition method for effective tuning of the refractive index (RI) sensitivity of long-period gratings (LPGs). Both etching and deposition take place within one process. Combination of both plasma-based processes allows for well-controlled tuning of the LPG sensorial response up to its operation at both dispersion turning point of higher order cladding modes and mode transition regime. As a result of the processing, the RI sensitivity has been enhanced up to over 12 000 nm/RIU per single resonance in narrow RI range (1.3344–1.3355 RIU) and over 2000 nm/RIU in broader RI range (1.34–1.356 RIU). Experimental results have been supported by numerical analyses that show capabilities for further significant improvement of both RI sensitivity and range of RI measured with the enhanced sensitivity.

This paper presents the fabrication of deep SiO2 and Tempax glass pillar structures by using reactive ion etching system, which intends to realize optical modulator mounted on an image sensor. The optical modulator consists of high aspect ratio SiO2 or Tempax glass pillars that can modulate the transmitted light intensity by moving a liquid in and out of the spaces between pillars based on the reversible electrowetting of liquid on top of micro-pillars surfaces. SiO2 pillars having smooth surfaces, vertical shapes, and high aspect ratio of 12 with a depth of 12 $\mu \text{m}$ , diameter of 1 $\mu \text{m}$ , and the pitch of the two pillars of $2~\mu \text{m}$ has been achieved. In addition, Tempax glass pillar structures are also successfully fabricated under investigation of gas mixtures of SF6 and O2. Finally, a 7.2 mm $\times \,\, 9.6$ mm optical window area integrated with an image sensor for an optical modulator has been demonstrated where high transmission modulation together with a large contrast has been observed of approximately 65% and 0.86 for cases with and without matching oil penetration, respectively. [2016-0036]

A wet-chemical surface texturing technique, including a two-step metal-catalyzed chemical etching (MCCE) and an extra alkaline treatment, has been proven as an efficient way to fabricate high-efficiency black multicrystalline (mc) silicon solar cells, whereas it is limited by the production capacity and the cost cutting due to the complicated process. Here, we demonstrated that with careful control of the composition in etching solution, low-aspect-ratio bowl-like nanostructures with atomically smooth surfaces could be directly achieved by improved one-step MCCE and with no posttreatment, like alkali solution. The doublet surface texture of implementing this nanobowl structure upon the industrialized acidic-textured surface showed concurrent improvement in optical and electrical properties for realizing 18.23% efficiency mc-Si solar cells (156 mm × 156 mm), which is sufficiently higher than 17.7% of the solely acidic-textured cells in the same batch. The one-step MCCE method demonstrated in this study may provide a cost-effective way to manufacture high-performance mc-Si solar cells for the present photovoltaic industry.

We show that inorganic fluorides, such as NaF and NH 4 F, can etch SiO 2 in the presence of HCl vapor resulting in a negative tone pattern transfer to a SiO 2 substrate. Using a polydimethylsiloxane stamp, we demonstrate high-quality one-step pattern transfer to a SiO 2 substrate. Compared with traditional HF vapor etching and buffered oxide etching methods, the current approach avoids direct handling of HF and, therefore, significantly reduces the associated safety risks. Our results suggest that fluoride etching could be a general purpose pattern transfer technique for soft lithography of SiO 2 substrates.

The embedded mask patterning (EMP) process provides a potential L10-FePt media solution for 1–10 Tbit/in2 magnetic recording areal density level. Methanol/Ar reactive ion etch process of FePt media (Ru 2 nm/FePt 8 nm) in EMP is investigated using an ion-neutral-redep synergy etch rate model with the consideration of sputtered redeposition. It has been found that etching of high aspect ratio features spacing that is largely limited by its low etch rate due to high redeposition rate; etching of small size grains is mostly limited by hard mask erosion through the etching process. This would cause etch non-uniformity within the grain size and grain spacing distribution. The hard mask on top of the small size grains (i.e., less than 3 nm) erodes much faster than the larger size gains, resulting in a completely consumed mask before the underlying layers are reached. It is important to reduce local ion sputtering in order to minimize mask erosion for the small grains. We have found that a higher chemical etch selectivity (>30:1) is essential to minimize mask erosion on the grains of 2 nm or larger. We also report that when sputter yield of Ru mask and FePt is adjusted from $10^{-1}$ to $10^{-2}$ level, further improvement is observed with the patterned grain size down to 2.5 nm and spacing down to 1.5 nm, and we suggest that the use of etch gas chemistry with a lighter atomic weight (such as He instead of Ar) would allow for sub-10 nm grain patterning.

Part I of this paper introduced a two-stage model for reliability characterization and lifetime prediction of amorphous-silicon thin-film transistors (a-Si TFTs) under low gate-field stress that includes both charge trapping in the silicon nitride (SiNx) gate dielectric and defect generation in the a-Si channel. In part II, the model is used to experimentally reduce the drain current instability under room temperature operation of a-Si TFTs under a prolonged gate bias of 5 V. Deposition conditions for the SiNx gate insulator and the a-Si channel layer were varied, and TFTs were fabricated with all reactive-ion-etch steps, or with all wet-etch steps. The stability of the a-Si channel also depends on the deposition conditions for the underlying SiNx gate insulator, and TFTs made with wet etching are more stable than TFTs made with reactive ion etching. Combining the various improvements raised the extrapolated 50% lifetime of the drain current of back-channel-passivated dry-etched TFTs under continuous operation in saturation at 20 °C with $V_{\mathrm{GS}}=\text{5}\ \text{V}$ from $\text{3}\times \text{10}^{4}\ \text{s}$ (9.2 h) to $\text{4}\times \text{10}^{7}\ \text{s}$ (1.4 years). We also extend the model, so that parameters from the degradation at one gate voltage can be used to estimate the degradation at other low gate voltages.

This paper presents a new approach and preliminary results for MEMS-enabled low-cost and high throughput parallel scanning probe nanolithography. The proposed approach is based on integrated microelectromechanical systems capable of simultaneous generation of a large number of identical nanoprecision patterns on a substrate. Integration of two-degree-of-freedom MEMS actuators with two-dimensional nanoprobe arrays as well as preliminary results for simultaneous generation of multiple submicrometer patterns using such devices is reported. Electrical cross talk between the fully silicon fabricated actuators along X - and Y -axes has been eliminated by optimizing the design. Scratch marks as narrow as 250 nm and as long as 42 μm have been generated on a thin photoresist layer, which was spin-coated on a silicon substrate using the electrothermal MEMS structure carrying up to 25 nanotips. Furthermore, the submicrometer patterns have been successfully transferred to the underlying silicon substrate via reactive ion etching. Patterns as narrow as 250 nm (∼60 nm in depth) were obtained on the underlying silicon substrate.

The reactive-ion-etching (RIE) characteristics of phase change material GeTe in CHF3/O2 plasma for back end of nonvolatile phase change memory devices were investigated in this paper. The etch rate and surface root-mean-square (RMS) roughness of crystalline GeTe and amorphous GeTe films were studied with various etching parameters, such as gas mixture ratio, chamber gas pressure, and power. It is found that the etch rate first increases with the increasing concentration of O2 and get at peak value 68.5 nm/min at 12% O2/(CHF3+O2), then decreases from 12% to 20% of O2 fraction. The surface RMS roughness slightly increases with the increasing oxygen content. By changing the gas pressure, the etch rate of GeTe films increases approximately linearly with increasing gas pressure up to 50 mTorr. In addition, the etch rate increases approximately linearly with increasing power below 400 W. The XPS spectra shows that some non-volatile GeFx, GeOx, TeFx, and TeOx by-products were left on the etched film surface. From these results of etched TiN films and GeTe films, the result of RIE with one step recipe shows the formation of under-cut on the profile of etched film. However, the result of RIE with two steps recipe shows better vertical characteristic and few residues were left on the profile of etched film.

In this letter, a plasma-free etch stop structure is developed for GaN HEMT toward enhancement-mode operation. The self-terminated precision gate recess is realized by inserting a thin AlN/GaN bilayer in the AlGaN barrier layer. The gate recess is stopped automatically at the GaN insertion layer after high-temperature oxidation and wet etch, leaving a thin AlGaN barrier to maintain a quantum well channel that is normally pinched off. With addition of an Al2O3 gate dielectric, quasi normally OFF GaN MOSHEMTs have been fabricated with high threshold uniformity and low ON-resistance comparable with the normally ON devices on the same wafer. A high channel mobility of 1400 cm $^{2}/\textrm {V}\cdot \textrm {s}$ was obtained due to the preservation of the high electron mobility in the quantum-well channel under the gate.

WOS: 000372012100008, Metal-assisted etching (MAE) can be used to form antireflective and light-trapping structures on crystalline silicon solar cells. This method has been widely used to form nanowires and nanoholes on their surfaces. In this study, the MAE technique with additional hole-injection mechanisms has been investigated to form surface nanostructures with various shapes. The effect of each chemical's percentage, as well as the etching time, has been studied on the surface geometry and optical performance. The average reflection from the surface was reduced to less than 3% over the solar spectrum. The light-trapping properties of the structures were investigated through absorption measurements on thin wafers, and a nearly 90% average absorption was obtained for samples with a 50-mu m thickness. The smoothing of the surface and lifetime of the chemical solutions has been systematically studied. As a result, control over the surface geometry and optical properties have been obtained with this new single-step etching approach. Passivation of the surface with SiO2 is also investigated to realize device implementation in the next step.

Metal-assisted etching can be used to etch high-aspect-ratio structures in silicon (Si) wafers. Using Au as catalytic metal, we have developed a simple robust technique that allows very high aspect ratio structures to be etched on n-type substrates. For example, arrays of hundreds of narrow (10 μm) and long (85 mm) trenches can be etched completely through a 650-μm-thick wafer in order to harvest silicon for solar cells using the SLIVER technique. We have developed a method for controlling the porosity of deposited Au films with thicknesses of 10–30 nm in order to achieve uniform etching.

Reducing surface reflectance by surface roughening is critical to improve the efficiency of all kinds of solar cells. In this letter, nanotexturing based on reactive ion etching (RIE) was adopted to increase the blue response and conversion efficiency of multicrystalline silicon (mc-Si) solar cells. After antireflection film deposition, the reflectivity at 400 nm remarkably decreases from 27.76% for acid-textured wafer to 4.46% for RIE-textured wafer. The average conversion efficiency of industrial wafer-scale (15.6 cm $\times \,\, 15.6$ cm) mc-Si solar cells increased from 18.10% to 18.72%. This letter presents an effective strategy to improve the efficiency of industrial mc-Si solar cells.

The antireflection (AR) performance and far-field transmittance, depending on the morphology and parameters of subwavelength structures (SWSs), have been investigated by a 3-D finite-difference time-domain (FDTD) method. It is found that far-field transmission characteristics are dominated mainly by period of SWSs. If the period is increased above 220 nm, the far-field transmittance rapidly decreases for a short-wavelength region. An effective and inexpensive method for fabricating disordered SWSs on fused silica has been demonstrated in this paper. An Au nanoscale island mask was formed by lower temperatures thermal dewetted at normal atmosphere. Then, a disordered SWS was fabricated by reactive ion etching (RIE). The average diameter of the Au nanoscale island was easily controlled by the thickness of Au thin films and annealing temperature. The etched depth and shape of fused silica SWSs depend additionally on RIE duration, thus achieving efficient AR characteristics. The measured data and calculated results obtained by the FDTD method exhibit reasonably similar tendencies. The optimized single-side fused silica SWS that is tapered on the tips leads to a significantly high transmissivity value of 96.2%. In addition, it exhibits a broadband AR property at a wavelength range of 400–1100 nm.