CMOS-MEMS Micro-Mirror Arrays by Post-Processing ASMC 0.35- $\mu \text{m}$ CMOS Chips

An electrostatic bi-stable $4\times 4$ micro-mirror array is implemented by using the standard Advanced Semiconductor Manufacturing Corporation 0.35- $\mu \text{m}$ 2-Poly-3-Metal fabless complementary metal-oxide-semiconductor microelectromechanical systems (CMOS-MEMS) process. Mechanical structures, including mirrors $(18 ~\mu \text {m} \times 18 ~\mu \text{m}$ in area each), electrostatic actuation mechanisms, and the suspensions, are made in the top three metal layers. Typical static pull-in voltage is tested to be 49 V and the maximum tilt angle is estimated to be 14.6°. The micro mirror can be operated at frequencies upward of 11 kHz at least. Total lifetime of more than 134.5 h, $4.8\times 10^{9}$ cycles, is tested. To avoid stiction during the process, the micro-mirror array is sacrificial-released from the substrate after the CMOS process by using reactive ion etching (RIE) and photoresist-assisted wet etching. Micro-mirror-wise processing yield of 99.3% after the release implies the robustness of the developed CMOS-MEMS process. [2017-0180]