Suppression of Dislocation-Induced Drain Leakage Current in Power VD MOSFET Structures

The investigated N-channel power vertical double-diffused metal-oxide-semiconductor field-effect-transistor (power VD MOSFET) suffered a drain-to-source current leakage ( $IDSS$ leakage). The leakage was caused by the dislocations located mainly in the N+ source area in the vicinity of the edge of the polycrystalline silicon gate. The stress induced by temperature gradients during wafer insertion into a furnace, its withdrawal from a furnace, and plasma damage were assumed to be the potential causes of the occurrence of dislocations. Inserting a wafer into a furnace and withdrawing it from a furnace at a slower pace during the steps of a high-temperature process' showed only a negligible suppression of the $IDSS$ leakage. The plasma etching of the polycrystalline silicon gate by $HBr$ (instead of the standard $SF_{6}$ ) changed the pattern of $IDSS$ failing transistors across a wafer (from the edge ring to continuous coverage), but the leakage was not suppressed. The $IDSS$ leakage was completely eliminated by the 5-s shorter plasma-etching time (from 21 to 16 s) of the P+ implantation screen oxide. The plasma damage generated by the long etching time of the P+ implantation screen oxide was determined as the root cause of the occurrence of dislocations.