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This paper presents an IEEE 1149.1 based defect and fault tolerant scan chain usable for testing and configuring large area and wafer scale integrated systems. It uses the triple modular redundancy (TMR) approach to tolerate defects on critical portions of IEEE 1149.1 circuitry. By a suitable distribution of sensitive circuits, failures on power, clock (TCK) and control signals (TMS and nTRST) can be tolerated. Some implementation issues, such as layout regularity and timing are discussed. The yield analysis shows that a basic IEEE 1149.1 scan chain can be a significant yield detractor, and its impact on yield is much larger than the small fraction of the total area it occupies. By contrast, the proposed fault tolerant scan chain maintains a high yield for realistic chain size.

This paper discusses the NP-complete problem of reconfiguring a two-dimensional degradable VLSI/WSI array under the row and column routing constraints. A new strategy for row selection in the logical array is proposed and the earlier approach by Low et. al. is simplified. A flaw in Low's algorithm is also addressed. Experimental results show that our algorithm is approximately 50% faster than the most efficient algorithm, cited in the literature, without loss of performance.

Shows that current techniques that use BISTs for testing CUTs often make it impossible to distinguish which one is faulty: a CUT or a MISR. The paper shows a number of additional benefits following from making use of BIST to test chips, FPGA circuits etc., if the only effect were that the testing of an MISR would confirm credibly the correctness of the MISR. Furthermore, the paper proposes such modification of the MISR compactor structure that it makes possible to obtain reliable results of testing. Additionally, an effective technique of testing such compactor is presented and a minimal number of test clock cycles that is required for full testing its correctness is determined.

This paper presents a closed form yield model that takes into account the constraints of an architecture. It applies to architectures that approximate global redundancy and for which the constraints translate into yield losses. The impact of the constraints on yield was evaluated by calculating the probability of observing non-tolerable defect patterns and by subtracting these probabilities from the yield of arrays with global redundancy. It is shown that most of the yield losses come from a few patterns comprising a small number of defects. A relatively sharp threshold in the yield to defect density relationship is observed. This paper also proposes a regression yield model. Using a simple regression analysis, a simplified model accurately predicts the slope and pivot point of true yield curves. These models can be used to predict when more redundancy is needed for given array and cells sizes.

As VLSI technology has developed, the interest in implementing an entire or significant part of a parallel computer system using wafer-scale integration (WSI) is growing. The major problem for this case is the possibility of drastically low yield and/or reliability of the system if there is no strategy for coping with such situations. In this paper, we propose a reconfigurable processor array based on the 1 1/2 -track switch (TS) model, such that spare processing elements (PEs) are not necessarily put around the array, but are more flexibly put in the array by changing the connections of spare PEs to non-spare PEs while retaining the connections among the non-spare PEs in the same manner as those in the 1 1/2 -TS model. The proposed model has a desirable property such that the physical distances between logically adjacent PEs in the reconfigured array are within a constant, i.e. independent of the size of the array. We show that the hardware overhead of the proposed model is a little greater than that of the 1 1/2 -TS model, while the yield of the proposed model is much better than that of the 1 1/2 -TS model.

In designing defect-tolerant WSI systems, introducing subsystem-dividing in which an overall system is divided into subsystems and defect recovery is performed for every subsystem, results in reduced chip area of redundant interconnection lines and reduced delay time through redundant interconnection lines. On the other hand, subsystem-dividing results in reduced defect recovery ability. This paper presents a novel subsystem-dividing method called "the multi-dimensional subsystem-dividing", in which a system is divided into subsystems in multiple dimensions, i.e. multiple directions intersecting each other. Since spare circuits from different directions can be provided to an area, the defect recovery ability of WSI systems under the presented method can be improved, i.e. the yield of the system can be enhanced to a greater extent than conventional subsystem-dividing which is single dimensional.

Creating large area FPGAs is limited by defective sections and the maximum reticule print size (/spl sim/3/spl times/3 cm). FPGAs are well suited for expanding into monolithic multiprint systems 2 to 9 times larger (5-10 cm square) we call deciMeter scale integration (DMSI). DMSI expands system capacity, while producing many copies per wafer. Its design criteria is much simpler than the complex wafer scale integration, but still uses defect avoidance routing around flawed blocks to build complete working systems. FPGAs have the main features required for successful DMSI systems: a repeatable cell, built in switchable flexible routing, high connectivity requirements between cell blocks, and flexibility with many potential applications. Modest changes at the periphery of FPGAs chips enables DMSI capability. Laser formed connections and cuts have proven effectiveness in bypassing fabrication time defects and creating defect free working wafer scale systems. The important DMSI criteria for laser defect avoidance is that defect free devices should need no correction. Depending on the DMSI size and current chip yields design defect avoidance requirements vary from simple row column substitution to cell by cell/row column substitution with redundant signal paths. Power shorts defects and how they are handled prove an important limitation on chip size.

A new stochastic method is introduced for calculating the manufacturing field of fault-tolerant VLSI/WSI systems. This method is an improvement on a previous method based on a Markov chain. This new method gives a higher lower bound value of the field with respect to other methods based on the same assumptions. This improvement is obtained by the consideration of reconfiguration strategies based on the knowledge of the fault patterns and the redundancy levels. The proposed method is easy to use in parametric studies of the field of a chip versus redundancy level and very versatile for inclusion in CAM/CAD programming environments.

As VLSI technology has developed, the interest in implementing an entire or significant part of a parallel computer system using wafer scale integration is growing. The major problem for the case is the possibility of drastically low yield and/or reliability of the system if there is no strategy for coping with such situations. Various strategies to restructure the faulty physical system into the fault-free target logical system are described in the literature. These restructures are performed using interconnection networks consisting of links and switches. Then the reliabilities of the systems depend on those of PEs and the interconnection networks. However, as far as we know, there are few studies considering the simultaneous faults of PEs and interconnection links. In this paper, by extending the Roychowdhury's (1989) algorithm, we propose a polynomial time algorithm for reconfiguring the 1 1/2 track-switch model compensating for simultaneous PE and bus faults.

For a redundant (array) system, he (or she) who considers that the total system reliability might be worse than a nonredundant system because of additional circuit faults might naturally say, "Is the redundancy really useful?". The main purpose of the paper is to answer the question for redundant array systems using E-1 1/2 track switches (Tadayoshi Horita and Itsuo Takanami, 2000) and a reconfiguration method. The answer is "the redundancy using these methods is useful!". Furthermore, the condition that the assumption that additional circuits such as tracks, switches, etc. are fault-free becomes valid is given.

Defect and fault tolerance techniques have played a substantial role in the evolution of silicon digital integrated circuits (ICs). The complex and several mechanisms causing defects in the as-manufactured IC could be represented by simple functional defects ("stuck-at" faults, etc.) and. given these simple functional defects, a variety of testing techniques (including "built-in self-test") could be deployed. Defect tolerance by reconstructing an IC emerged rather early in RAMs and in various array-based architectures. Field-useable testing techniques capable of isolating the site of a defect causing a functional failure farther extended capabilities to allow field-correction or self-correction when failures occurred. Analog ICs present a more sophisticated challenge, though several capabilities for defect tolerance (e.g., laser adjustment of resistances or capacitances) and for fault tolerance (including modular redundancy) emerged. The microelectromechanical systems (MEMS) technology (also called "microsystems technology"-MST) has matured to the point where more extensive applications can be commercially realized. moving beyond the relatively limited number of significant commercial applications now seen. Addition of defect and fault tolerance to the MEMS technology in a manner which abstracts details to achieve simple models will, however, be difficult.

Interconnect crosstalk prediction has become increasingly important with deep submicron downscaling of ICs and wafer scale integration. Existing tools for management of the emi problem are computationally expensive and not very broad in application. The unique approach proposed involves the creation of parameterized models of primitive interconnect structures, wirecells, using modular artificial neural networks (MANNs). The finite element method, a circuit simulator and a neural network multi-paradigm prototyping system are coupled together to produce a library of re-usable MANN-based wirecell models. The method is especially attractive because it is capable of modeling the simultaneous effect of several uncorrelated variables such as interconnect length, width, thickness, separation, conductor and insulating medium characteristics on crosstalk and delay. Equi-coupling contours called isocouples are derived for noise characterization to guide design activities such as placement (e.g. matched devices placed on same isocouple). Experimental results from a transconductance amplifier demonstrate the viability of the approach.

A performance-scalable ISDP (Interactive Sensor Data Processing) workstation, accelerated with commercial PCI multiprocessor cards, is described and a WSI massively data-parallel processor (MdPP) device is proposed for the replacement of its VLSI processors. Delivering 60 GOPS for 16-bit integer multiply-accumulate operations, a WSI-FPGA implementation of the reconfigurable device is shown to be better suited to ISDP applications and at least two orders-of-magnitude more cost-effective.