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Dependable testing of compactor MISR: an imperceptible problem?
- Source :
- ETW
- Publication Year :
- 2003
- Publisher :
- IEEE Comput. Soc, 2003.
-
Abstract
- Shows that current techniques that use BISTs for testing CUTs often make it impossible to distinguish which one is faulty: a CUT or a MISR. The paper shows a number of additional benefits following from making use of BIST to test chips, FPGA circuits etc., if the only effect were that the testing of an MISR would confirm credibly the correctness of the MISR. Furthermore, the paper proposes such modification of the MISR compactor structure that it makes possible to obtain reliable results of testing. Additionally, an effective technique of testing such compactor is presented and a minimal number of test clock cycles that is required for full testing its correctness is determined.
- Subjects :
- Engineering
Sequential logic
Correctness
Wafer-scale integration
business.industry
White-box testing
Hardware_PERFORMANCEANDRELIABILITY
Reliability engineering
Built-in self-test
Embedded system
Hardware_INTEGRATEDCIRCUITS
business
Field-programmable gate array
Orthogonal array testing
Electronic circuit
Subjects
Details
- Database :
- OpenAIRE
- Journal :
- Proceedings The Seventh IEEE European Test Workshop
- Accession number :
- edsair.doi...........5ca0c4445b766a9b7ee8352f5eccaeeb