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Ultra-high-speed cameras are a powerful tool for biology as well as physics and mechanics to analyze the process of ultra-high-speed phenomena. The frame rate of the state-of-the-art burst-readout ultra-high-speed silicon imagers has reached approximately 20Mfps [1,2]. To observe faster phenomena such as plasma generation in laser processing, the state of electrons in a chemical reaction, and so on, much faster cameras are desired. There are several factors that prevent the speed-up of the ultra-high-speed imager: high gate control voltages and high power dissipation for high-efficiency multi-stage charge transfer in CCD imagers, and the current density limit of the power and ground lines and RC-constant of the vertical readout lines in CMOS imagers. Computational imaging can be a promising option to break the design limit of solid-state ultra-high-speed imagers. Several dedicated CMOS imagers have been demonstrated [3,4]. This paper presents a demonstration of a single-chip ultra-high-speed multi-aperture CMOS imager based on compressive sampling. The imager performs single-shot burst-readout image acquisition at a frame rate of 200Mfps.

Fluorescence lifetime imaging microscopy (FLIM), which is a nondestructive and minimally invasive manner and can therefore be applied to living cells and tissues, is a great analysis tool in fundamental physics as well as in the life sciences. Charge-coupled devices (CCDs) [1] and single-photon avalanche diodes (SPADs) [2,3] are used for time-resolved lifetime measurement. In particular, SPAD-based time-resolved imagers have a high single-photon sensitivity and good noise robustness. However, they consist of a SPAD array with pixel circuitry, time-to-digital converters (TDCs), digital integrators to amplify signals, and readout circuitry. To implement the high photon-counting rate, a large number of TDCs and digital integrators are required. The spatial resolution of the SPAD-based time-resolved imagers is limited on this account. A recently reported time-resolved CMOS imager [4] using a draining-only modulation (DOM) technique has an attractive feature that a very simple pixel structure and 2-stage charge transfer without transfer gate (TG) can be simultaneously attained. However, it has a small aperture area, a comparatively low transfer speed, and multiple outputs are a challenge.

In this paper, a lock-in pixel readout circuits using a high speed lateral electric field modulator with differential charge accumulation for a stimulated Raman scattering imager is presented. The stimulated Raman scattering works by detecting the vibrations in chemical bonds between atoms, and the generated Raman signal after stimulated scattering processes is very low compared to offset signal. By using a high-speed lateral electric field modulator with lock-in pixels differential charge accumulation technique using a sample-and hold circuit with a fully differential amplifier, very small effective Raman signal can be extracted from large offset signal and high dynamic range is achieved.

Time-of-Flight (ToF) range imagers have a wide range of applications, such as 3D mice, gesture-based remote controllers, amusement, robots, security systems, and automobiles. Numerous ToF range imager developments have been reported [1-4]. Recent developments are often based on CMOS image sensor technology with pinned photodiode options [5-7], which are suitable for cost-effective mass production. Reported CMOS ToF range imagers use single-tap or two-tap lock-in pixels; to cancel the influence of background light, two or four sub-frames are used to produce a background-canceled range image. These architectures, however, have difficulty with precise range measurements of moving objects, because background light cancelation is not guaranteed for moving objects. Lock-in pixels without any charge-draining gate suffer from background light during the readout time of the operation. Another important issue with CMOS ToF range imagers for high range resolution is the speed of lock-in pixels, which must be improved to use high-modulation-frequency light or short-duration light pulses.

Recently, 3D scanning systems have attracted rapidly rising attention in combination with 3D printers. One of the common technologies in contactless 3D scanners is the light-section method, which has advantages in term of accuracy. The method, however, requires a long base line between a camera and light source to achieve high resolution and a mechanical scanning system. A high range resolution Time-of-Flight (ToF) imager provides new possibilities of implementing a miniature head, which allows flexible scanning of an object with a complicated structure. The range resolution of reported CMOS ToF imagers [1-3] is limited to a few centimeters. For higher resolution, higher modulation frequency is required. However, the modulation frequency used for CMOS ToF imagers is limited to several tens of MHz. This paper presents a ToF imager with 0.3mm range resolution, which corresponds to 2ps time resolution. To achieve this high resolution, the imager uses a ToF measurement technique based on an impulse photocurrent response [4] and draining-only modulation (DOM) pixels [5]. To realize a range imager with 2D pixel array, column-wise gating-clock skew calibration is implemented to demonstrate simultaneous sub-mm ToF measurements for the whole pixel array.

An extremely low temporal noise and wide dynamic range CMOS image sensor is developed using low-noise transistors and high gray-scale resolution (17b) folding-integration/cyclic ADC. Two types of pixel are designed. One is a high conversion gain (HCG) pixel with removing the coupling capacitance between the transfer gate and the floating diffusion, and the other is a pixel for wide dynamic range (WDR) CMOS imager with the native transistor as a source follower amplifier. The CMOS image sensor which is in combination with the proposed pixels and the high performance column ADC has achieved a low pixel temporal noise of 1.1e− rms and a wide dynamic range of 87.5dB with the video rate operation (30Hz). In addition, the WDR pixel has a very small occurrence of the RTS noise because of the effect of the native transistor in the pixel. The implemented HCG CMOS imager and WDR CMOS imager using 0.18μm technology have the pixel conversion gain of 73.2-μV/e− and 22.8-μV/e−, respectively.

Low-noise CMOS image sensors (CIS) employing column-parallel amplifiers that significantly reduce temporal noise, as well as electron-multiplication CCD (EM-CCD) image sensors are becoming popular for very-low-light-level imaging. These low-noise imagers with high-gain amplification in either the charge or voltage domains sacrifice the intra-scene dynamic range. Scientific applications of solid-state imagers strongly require very low temporal noise and wide intra-scene dynamic range as well as very high gray-scale resolution. A column-parallel analog-to-digital converter (ADC) and column-level signal processing in CISs are key techniques to meet these requirements. Single-slope [1,2], successive-approximation [3] and cyclic ADCs [4] are widely used for the column-parallel ADC in CMOS imagers. However, these ADCs require additional gain enhancements to achieve very low temporal noise. A recently reported [5] delta-sigma (ΔΣ) ADC has an attractive feature that low temporal noise and high resolution can be simultaneously attained by an oversampling technique. However, for very high resolution, a high number of samplings per pixel output, e.g., more than 360 samplings for 16b, is required.