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This article presents the coupled electrothermal simulation results of single event burnout (SEB) in power diode with field limiting rings termination structure. Two different hardening techniques of low carrier lifetime control and introducing the buffer layer are investigated comparatively in both the radiation tolerance improvement and the electrical performance degradation. Our simulations reveal that a significant reduction in the carrier lifetime is needed for the hardening of the power diode using only the carrier lifetime control method. However, the sharp increases in the forward voltage drop and the leakage current at the lower carrier lifetime make this hardening technique unacceptable. On the contrary, the addition of the buffer layer is able to improve the safe operating area under the heavy ion irradiation even up to the breakdown voltage, while the breakdown characteristics and the leakage current are kept unchanged and the increases in the forward voltage drop and the reverse recovery charge can be well controlled. In conclusion, adding a buffer layer is considered a superior and promising hardening technique. [ABSTRACT FROM AUTHOR]

The development of more electric aircraft (MEA) has accelerated in recent years. Power converter systems for MEA require higher reliability compared with the conventional power converter systems as well as higher energy efficiency. A power device at high altitude might break down at a certain rate because of cosmic rays. Thus, it is necessary to carefully consider the reliability of single event burnout together with the converter design. This study examines a failure in time (FIT) rate comparison among three different inverter configurations using 3.3-kV and 6.5-kV full SiC power modules (FSPMs) under several operating conditions. It presents module and inverter configuration selection criteria in consideration of the FIT rate. In addition, the transitions of FIT rates during the flight are calculated using actual flight data to help the power converter system designers understand how the FIT rate should be considered. Furthermore, this study verifies a high-frequency switching operation at various bus voltages for a 6.5-kV FSPM and the power loss calculation for MEA applications. [ABSTRACT FROM AUTHOR]

The objective of the Dosimetry Inter-comparison and Miniaturization Experiment (DIME) approach is to compare different miniature electronic dosimeters for monitoring exposure to ionizing radiation primarily in terms of potential degradation due to total ionizing dose (TID) and the threat of single event effects (SEEs). As the title implies, DIME is divided in two parts: DIME-1 is a passive board that is turned on only to read the cumulative dose and DIME-2 is an active board that requires continuous power to monitor the radiation-induced energy depositions that can lead to SEE. This article describes the details of the operation of DIME-2 and the results of the flight on the Demonstration and Science Experiments (DSX) satellite which orbited the Earth in an elliptical middle earth orbit (MEO) orbit that extended from 6000 to 12 000 km at an inclination of 42° thereby crossing the entire slot region between the inner and outer electron belts. Measurements made every 15 min consistently showed a large peak in the energy depositions at perigee and a small one near apogee with fewer events in the slot region. [ABSTRACT FROM AUTHOR]

In this article, the single event responses of a 4-Mb commercial two-transistor and two-capacitor (2T2C) ferroelectric random access memory (FRAM) are studied. A microbeam was used to identify sensitive circuit areas. Various response categories are identified. The two most vulnerable sensitive areas were investigated using reverse engineering, and the results indicate that the n-well resistors located in the peripheral circuits are the primary source of the bit upset response and functional interruption. Analysis results indicate that ion strikes on the n-well resistor generate current disturbances in circuits, which can alter the polarization state of the ferroelectric bit storage capacitor and interrupt the data transfer process of the device. [ABSTRACT FROM AUTHOR]

In this article, the single event burnout (SEB) performances for 2DEG Alx $\text{Ga}_{{1}-{x}}\text{N}$ channel p-GaN gate high electron mobility transistors (HEMTs) have been investigated comprehensively to reveal the failure mechanisms and broaden applications in harsh environments. As Al composition ${x}$ increases from 0.0 to 0.4, ${V}_{\text {BR}}$ increases from 500 to 730 V, and the corresponding SEB voltage ${V}_{\text {SEB}}$ at linear energy transfer (LET) = 10 pC/ $\mu \text{m}$ increases from 300 to 450 V. Possible mechanisms of Alx $\text{Ga}_{{1}-{x}}\text{N}$ channel HEMTs from the perspective of electric field (${E}$ -field) are proposed. ${E}$ -field near source and drain side after radiation would have a high peak ${E}$ -field and that of p-GaN layer exceeds 3.3 MV/cm of critical ${E}$ -field for GaN material, causing SEB to occur (LET = 10 pC/ $\mu \text{m}$). When SEB occurs in HEMTs, ${E}$ -field would increase rapidly and cannot be recovered. A new phenomenon has been first discovered when SEB occurs in Alx $\text{Ga}_{{1}-{x}}\text{N}$ channel HEMTs with p-GaN gate (${x} = {0.0}$ –0.4, step = 0.1). In addition to the back-channel effect, an excess of holes would be left in the buffer layer after electrons flow toward the drain. It allows the injection of an excess of holes in the buffer layer into the gate with low potential, resulting in a sharp increase in ${I}_{\text {G}}$. Simulation results indicate that AlGaN channel HEMTs have great advantages in SEB performances compared with the traditional GaN channel HEMTs. [ABSTRACT FROM AUTHOR]

In this article, we present a unique method of measuring single-event transient (SET) sensitivity in 12-nm FinFET technology. A test structure is presented that approximately measures the length of SETs using flip-flop shift registers with clock inputs driven by an inverter chain. The test structure was irradiated with ions at linear energy transfers (LETs) of 4.0, 5.6, 10.4, and 17.9 MeV-cm2/mg, and the cross sections of SET pulses measured down to 12.7 ps are presented. The experimental results are interpreted using a modeling methodology that combines TCAD and radiation effect simulations to capture the SET physics, and SPICE simulations to model the SETs in a circuit. The modeling shows that only ion strikes on the fin structure of the transistor would result in enough charge collected to produce SETs, while strikes in the subfin and substrate do not result in enough charge collected to produce measurable transients. Comparisons of the cumulative cross sections obtained from the experiment and from the simulations validate the modeling methodology presented. [ABSTRACT FROM AUTHOR]

A single-event effect (SEE) simulation toolkit has been developed at CERN for the whole radiation effects community and released as an open-source code. It has been validated by comparing the simulated energy deposition of inelastic interactions, due to monoenergetic neutrons in the 1.2–17 MeV energy range, to the distribution measured experimentally by a silicon diode detector. [ABSTRACT FROM AUTHOR]

The deposition of energy in large and small sensitive volumes is studied after ultrahigh energy heavy-ion irradiation. We demonstrate that the energy deposition increase effect previously reported in p-i-n diode detectors due to delta electrons occurs only in large sensitive volumes, but not in small ones, typical of advanced microelectronic devices, such as the cells of a 3-D NAND Flash memories. We attribute this effect to the trajectories of the secondary electrons. [ABSTRACT FROM AUTHOR]

Ion-induced SETs were captured from a germanium photodiode (PD) in an integrated silicon photonics technology platform. Statistics from 400 ion-strike events were extracted for various optical powers and LETs incident on the PD. The results show that the transient peak decreases with increasing optical power. TCAD simulation results indicate that photo-generated carriers decrease the built-in electric field of the PD, thereby decreasing the transient peak. The photo-generated carriers also increase the probability of Auger recombination, which further reduces the transient peak under illuminated conditions, but this effect is small and does not contribute significantly to the transient peak reduction. Finally, a short case study with an ON–OFF keying modulation scheme is presented to show how these transients have the potential to corrupt bits in realistic communication systems. Furthermore, it is also shown that hardening techniques can be utilized to mitigate bit errors in communication systems that use integrated Ge PDs. [ABSTRACT FROM AUTHOR]

A silicon detector with a fast electronics chain is used for the dosimetry of protons in the range 0.5–5 MeV at the Centro Nacional de Aceleradores (CNA) 3 MV Tandem laboratory in Seville, Spain. In this configuration, measurements can be performed in pulsed mode, using a digitizer to record event-by-event proton energy depositions. The distributions of deposited energy were obtained thanks to a calibration with an alpha source. Measurements of flux and deposited energy are used to enable single event effect (SEE) testing on selected static random access memories (SRAMs). [ABSTRACT FROM AUTHOR]

High-voltage p-i-n diodes for space applications are sensitive to single event burnout (SEB), which may cause the failure of the entire electronic system. This article describes the SEB failure mechanism of high-voltage p-i-n diodes with field limiting rings (FLRs) termination structure, based on the electro-thermal coupled transient simulation model in the Sentaurus TCAD simulator. The simulation results show that the catastrophic failures result from the intense local heating at the edge of the main junction, because the high electric field strength at this region induces strong impact ionization of the charge carriers. The strike at the edge of the main junction shows the strongest sensitivity to SEB since the energetic particle-induced carriers are deposited exactly at the high electric field region. Then, a novel SEB hardening technique of localized carrier lifetime control at the edge of the main junction region is proposed based on the analysis on the failure mechanism. Our simulation results demonstrate that the reduction of the localized carrier lifetime can alleviate the peak electric field and reduce the local heat accumulation, thereby improving the SEB performance of high-voltage p-i-n diodes. [ABSTRACT FROM AUTHOR]

Accurate characterization of radiation-induced soft errors is a critical step toward understanding the impact of these glitches on circuit and system reliability. With process scaling, there has been exponential increase in number of transistors that can be packed on a die which, in turn, results in higher sensitive node count and persistent soft error susceptibilities. In this work, a novel circuit technique employing higher sensitivity toward soft errors is proposed. The circuit makes use of current-starved gates with bias knobs to fine-tune both measurement resolution and strike sensitivity enabling accelerated and efficient induction of errors in a limited-time irradiation test environment. The back-sampling chain (BSC) circuit can measure individual radiation-induced transient pulse with as low amplitude as $0.3\times $ VDD while maintaining a high measurement resolution for pulsewidth characterization. The bias knobs allowing tuning of sensitivity and resolution enable, for the first time, a strike pulse waveform reconstruction methodology that can be used to calibrate current pulse models for assessing soft error rate (SER) sensitivity of standard logic gates. [ABSTRACT FROM AUTHOR]

Field-programmable gate arrays (FPGAs) are susceptible to radiation-induced effects that can affect more than one memory cell. Radiation-induced microsingle event functional interrupts (micro-SEFIs) are one of such events that can upset several bits at a time. These events need to be studied because they can overcome protection from techniques such as triple modular redundancy (TMR) and error correction codes (ECCs). Extracting these events from radiation data helps to understand if specific resources of the FPGA are more vulnerable and the extent of this vulnerability. This article presents a method based on statistics and fault injection to identify micro-SEFIs from beam-test data in the configuration memory and block RAM (BRAM) of SRAM-based FPGAs. The results show the cross section of these events for the configuration RAM (CRAM) and BRAM for three families of Xilinx SRAM FPGAs gathered throughout three neutron tests. This article also contains data from a fault injection campaign to uncover the possible CRAM source bits causing micro-SEFIs in memory look-up tables (LUTs) of Xilinx 7-series and Ultrascale devices. [ABSTRACT FROM AUTHOR]

Single event burnout (SEB) of enhancement mode GaN high-electron mobility transistors (HEMTs) under heavy ion irradiation is systematically studied based on simulations in this work. Susceptibility to SEB of different particle incidence environments is investigated to determine the device’s sensitive position. Under these conditions, the mechanism of SEB in enhancement mode HEMTs is mainly associated with the charge congestion and subsequent continuous impact ionization. A hardened HEMT structure with the gate and drain double field plates is proposed correspondingly. Apart from better output characteristics and almost 25% improvement of breakdown voltage, the hardened structure also demonstrates better tolerance of SEB. This hardened structure can modify the electric field in the high field region so that charge accumulation is reduced significantly, thus effectively decreasing the possibility of SEB’s occurrence. With a vertical heavy ion strike of 63.8 MeV $\cdot $ cm2/mg linear energy transfer (LET), SEB threshold voltage of the conventional structure HEMT is 160 V, while that of the hardened structure HEMT is much higher, reaching 249 V. Besides, the hardened device exhibits better SEB tolerance than the conventional device even at different higher LET conditions. Furthermore, the contribution to SEB tolerance of each field plate is also discussed. [ABSTRACT FROM AUTHOR]

The dependence of temperature and back-gate bias on single-event upset (SEU) sensitivity is investigated based on a 0.2- $\mu \text{m}$ double silicon-on-insulator (DSOI) technology. At room temperature, an obvious decrease in SEU cross section with the negative back-gate bias is experimentally observed for a DSOI static random access memory (SRAM). The physical mechanism of single-event effect (SEE) is explained through technology computer-aided design (TCAD) simulations. TCAD simulations were also performed to explain the impact of back-gate bias on charge collection and full width at half maximum (FWHM) of the pulsewidth at various temperatures. Both charge collection and FWHM of the pulsewidth increase significantly with temperature rising from 240 to 400 K. It is demonstrated that the SEU threshold linear energy transfer (LET) for a DSOI 6T SRAM cell decreases with an increase in temperature. Compared with a fully depleted SOI (FDSOI) technology, the unique independent back-gate bias scheme for a DSOI SRAM cell exhibits higher tolerance to SEU. At 400 K, it is found that the SEU threshold LET (LETth) for a DSOI 6T SRAM cell increases by 12.5% with back-gate bias of nMOS reduced from 0 to −15 V. [ABSTRACT FROM AUTHOR]

Single event transients (SETs) have become increasingly problematic for modern CMOS circuits due to the continuous scaling of feature sizes and higher operating frequencies. Especially when involving safety-critical or radiation-exposed applications, the circuits must be designed using hardening techniques. In this brief, we present a new radiation-hardened-by-design full-adder cell on 45-nm technology. The proposed design is hardened against transient errors by selective duplication of sensitive transistors based on a comprehensive radiation-sensitivity analysis. Experimental results show a 62% reduction in the SET sensitivity of the proposed design with respect to the unhardened one. Moreover, the proposed hardening technique leads to improvement in performance and power overhead and zero area overhead with respect to the state-of-the-art techniques applied to the unhardened full-adder cell. [ABSTRACT FROM AUTHOR]

The sensitivity of the LM139A quad voltage comparator toward simultaneous single-event transient has been investigated through laser single photon absorption. The results have been supported and compared to heavy-ion tests. The analysis of sensitivity leads to the observation of two sensitive cases related to internal charge-sharing mechanism between comparator function and input line coupling effects. [ABSTRACT FROM AUTHOR]

Peak transient currents due to pulsed-laser or heavy-ion irradiation of Ge $p$ MOS FinFETs are nearly independent of gate bias. This is because the prompt photocurrent is due primarily to a transient source–drain shunt. In contrast, long-term diffusion charge collection is strongly gate-bias dependent. This bias dependence results from hole injection from the source in response to the transient increase in electron concentration in the channel. The transients measured at the source terminal change polarity when the strike location moves from the source to the drain, but this effect does not occur for the transients measured at the drain terminal. Charge collection mechanisms are studied using TCAD simulations. [ABSTRACT FROM AUTHOR]

In this work, the study of the single event effects (SEEs) in capacitor-less one-transistor dynamic random access memory (1T-DRAM) based on an indium gallium arsenide on insulator (InGaAs-OI) transistor is conducted for the first time. The electrical properties of the 90-nm device are numerically simulated to determine appropriate operation condition. The successful memory behaviors are observed due to the gate-induced drain leakage (GIDL) programming method. The impacts of different linear energy transfer (LET) values, high-energy particle (HEP) strike positions and directions, and HEP hitting moments on the memory performance are investigated via simulations. Unlike the conventional SOI device, the source and drain in 1T-DRAM cells are found to be sensitive to SEEs with a higher transient current. The single event upsets (SEUs) are found to occur only when the HEP hits the device at reading “0” state and holding state before read “0.” An increased read-out current is obtained after the HEP strike due to the GIDL- and SEE-induced accumulative floating holes. The related mechanisms are discussed in detail. These results and discussions are useful for the development of the SEE hardening of 1T-DRAM-based embedded memory for space applications in the future. [ABSTRACT FROM AUTHOR]

In this article, we present a study of single-event transients (SETs) through an integrated test vehicle. This block was designed and manufactured within two test-chips in 28- and 22-nm fully depleted silicon-on-insulator (FDSOI) advanced technologies. Radiation testing was performed on those test chips in order to characterize SETs. The results are cross-coupled with Monte Carlo simulations and discussed. [ABSTRACT FROM AUTHOR]

This article studies the impact of radiation-induced single-event effects (SEEs) in the Zynq-7000 field programmable gate array (FPGA) and presents an in-depth analysis of the SEE susceptibility of all the memories of the programmable logic. The radiation experiments were performed in the CERN North Area facility and in the GSI Helmholtz Centre for Heavy Ion Research using very/ultra high-energy heavy ions. The offline analysis of the radiation experimental results produced a deep understanding for various SEE phenomena observed in the Zynq-7000 FPGAs, such as single-event function interrupts (SEFIs), single-event transient (SET) in global signals, and multiple bit upsets that could be key issues for the design of an effective SEE mitigation approach. [ABSTRACT FROM AUTHOR]

During the flight, an aircraft is submitted to a radiation environment composed of cosmic-ray-induced particles (CRIP) of which neutrons are responsible for approximately 40% of the crew effective dose and are the main cause of single event effects (SEE) in avionics systems at flight altitudes. A model of Learjet aircraft was developed on Monte Carlo simulation using the MCNPX code in order to detail the CRIP field inside the aircraft. The radiation source modeling was previously developed by a computational platform that simulates the energy and angular distributions of the CRIP along the atmosphere. In this article, we determined the variation of the neutron radiation field in several positions inside the aircraft at 11- and 18-km altitudes and for both equatorial and polar regions. The results suggest that the maximum variation of neutron fluence rate between different positions inside the aircraft shows a tendency of higher differences for a lower energy threshold (thermal and E > 1 MeV) in comparison with those differences for a higher energy threshold (E > 10 MeV). Moreover, the angular distribution results show relevant differences between positions inside aircraft, mainly for thermal neutrons close to the fuel. The general tendency is to enhance these discrepancies for devices with new technologies, due to their lower energy threshold for SEE occurrences. [ABSTRACT FROM AUTHOR]

This article presents a digital dosimeter for on-chip total ionizing dose (TID) computation, designed and fabricated in 28- and 22-nm fully depleted silicon-on-insulator (FD-SOI) technologies. FD-SOI has improved, by far, the robustness to single event effect (SEE), while TID may require fine control in high krad regime, leading to the interest for an integrated dynamic monitoring capability. The digital dosimeter is therefore implemented with a simplified TID hardware model and monitoring structure, capable of tracking and reporting TID value while being quasi-insensitive to voltage and temperature variations. The dosimeter is experimentally validated with gamma rays, showing less than 5% mismatch in dose estimate in the 0 to 50-krad(Si) range. Low-energy photons and alpha particles were used to extend the measurements to other sources and up to 500 krad(Si), where the mismatch with the theoretical estimate remains limited to 16%. The digital dosimeter, with an area of 0.002 mm2 and a very low imprint, is a suitable companion for any system requiring dynamic TID monitoring. [ABSTRACT FROM AUTHOR]

We perform Monte Carlo (MC) simulations to describe heavy ion (HI) nuclear interactions in a broad energy range (4 MeV/n–150 GeV/n), focusing on the single event effect (SEE) sub-linear energy transfer (LET) impact. Previously retrieved single event latch-up (SEL) experimental data have indicated that standard energy ions (~10 MeV/n) can produce high-LET secondaries through fusion reactions which are expected to strongly influence the SEE cross section in the sub-LET region. Alternatively, interactions of higher energy ions (>100 MeV/n) yield secondaries of a similar LET distribution as from the projectile, for projectile-like fragments, and high-energy proton reactions, for target-like fragments. Hence, the factor of relevance to the sub-LET SEE cross section is correlated to low-energy. [ABSTRACT FROM AUTHOR]

This article is a first attempt to explore, by simulation, the radiation response of III–V binary compound semiconductors subjected to high-energy atmospheric neutrons. The study focuses on the radiation response of eight III–V materials: GaAs, AlAs, InP, InAs, GaSb, InSb, GaN, and GaP. For each semiconductor, the interaction rates of a bulk material target exposed to a neutron source mimicking the atmospheric neutron spectrum at sea level are evaluated both from a direct calculation using nuclear cross section libraries and by Geant4 simulations. The latter are also used to investigate in detail the reaction rates per type of reaction (elastic, inelastic, and nonelastic) and to classify all of the neutron-induced secondary products considering their atomic number and energy. Implications for single event effects are analyzed and discussed, notably in terms of electrical charge deposited in the material with respect to the critical charge for technologies ranging from 180 to 14 nm. [ABSTRACT FROM AUTHOR]

This article presents the radiation hardened by design (RHBD) techniques applied to a 15-GHz quadrature subsampling phase-locked loop (PLL) at a sub-50 nm partially depleted silicon-on-insulator technology node. Radiation-hardening techniques are integrated into a subsampling architecture for robust noise and radiation performance. Experimentally validated bias-dependent single-event models are used to characterize the radiation response, and the applicability of existing RHBD techniques to subsampling PLLs is examined. A significant vulnerability introduced in dual-loop architectures such as subsampling is identified and mitigated with a proposed technique. Favorable noise and loop perturbation suppression characteristics of the subsampling architecture are leveraged to develop a high-performance RHBD PLL, maintaining performance specifications comparable to unhardened designs. [ABSTRACT FROM AUTHOR]

Traditionally, increasing logical masking probability has been used to improve the circuit reliability against single-event transients (SETs). As the very first work, this paper presents a new approach to increase the reliability of digital circuits against soft errors caused by multiple event transients (METs) by taking advantages of circuit partitioning and local logical restructuring techniques. In the proposed approach, the circuit is partitioned into various subcircuits and, then, several structures of each subcircuits which satisfy the area constraints are extracted by using a graph-based procedure. In order to select the suitable alternative between various subcircuit structures, we introduce a novel metric named global failure probability in the presence of METs (GFPM). This parameter provides an evaluation of each subcircuits contribution in the soft error rate (SER) of the given circuit making it possible to estimate the impacts of changing the structure of the subcircuits on the circuit SER. Hence, it prevents from repeatedly calculating the SER of the circuit that is very time-consuming leading to significant improvements in the optimization runtime. Experimental studies on ISCAS benchmark circuits show that the proposed approach, on average, achieves 18.4% SER reduction with 11.9% area overhead and 8.2% delay overhead comparing to the original circuit while the global SET-based SER mitigation approach and the global MET-based SER mitigation approach achieve 8.46% and 21.8% SER reduction, respectively. Besides, the proposed technique is about $580 \times $ faster than the global MET-based method. [ABSTRACT FROM AUTHOR]

Conventional radiation-hardened cells of static random access memory (SRAM) are not robust enough in 28 nm technology, due to partial immunity of single-event upset (SEU) effect (Quatro-based cells) or insufficient critical charges in sensitive nodes (conventional stacked cells). The reduction of read noise margin (RNM) at the low supply voltage (VDD) confines these cells from low VDD applications. We propose a novel interleaving stacked-14T (ILS-14T) cell which prevents voltage transient from propagating to other redundancies. The ILS-14T cell can be resilient to both 0–1 and 1–0 upsets by injecting 12 mA in sensitive nodes. The critical charges of the ILS-14T cell are substantially larger than most other hardened cells at VDD from 0.3 to 0.9 V. The RNM of the ILS-14T cell is two times of most Quatro-based cells at 0.3 V VDD and larger than most cells at 0.6 and 0.9 V VDD. The area of occupation is 334% of the conventional 6T cell, which equals other 14T cells. The static–dynamic decoder array with 20%–40% area penalty and 116%–132% delay of rising edge, when compared with the conventional one, reduces the read failure rate by preventing single event transients (SETs) from propagating to unexpected word lines (WLs). [ABSTRACT FROM AUTHOR]

This article presents neutron radiation-induced soft error rate (SER) statistics and detailed analysis thereof, revealing a multitude of circuit parameters impacting the soft-error susceptibility of standard combinational logic in advanced CMOS nodes. A high-density array-based soft-error characterization vehicle is presented, featuring standard logic gate chains of varying lengths. Neutron irradiation data obtained from gate variants employing devices with distinct channel widths and threshold voltage flavors is analyzed at multiple supply voltages, ranging from nominal down to near-threshold. Supplemented with first-order simulations, measured SER cross-section results obtained from test structures implemented in a 65-nm planar CMOS technology node reveal the complex interplay between factors, such as supply voltage, node capacitance, restore current (IRESTORE), gate topology, and logic chain length responsible in contributing toward the collective soft error susceptibility of a standard gate type, which constitutes the main focus of this article. In addition, the easy process portability of the proposed macro is demonstrated through implementation in a 16-nm FinFET process. [ABSTRACT FROM AUTHOR]

Single event effect (SEE) testing with ultrahigh energy (UHE) heavy ions, such as the beams provided at CERN, presents advantages related to their long ranges with a constant linear energy transfer value. In the present work, the possibility to test components in parallel is being examined, and results from the CERN 2018 UHE Pb test campaigns are studied. Furthermore, the generation of multibit upsets by the UHE Pb ions is evaluated, and the contribution of possible fragments to the SEE measurements is discussed. [ABSTRACT FROM AUTHOR]

The combined impact of single event effect (SEE) and total ion dose (TID) on Si-based radiation-hardened Vertical Double-diffused Metal-Oxide-Semiconductor (VDMOS) Field-Effect Transistor (VDMO-SFET) is investigated in this letter. As previous research of VDMOS on TID effect and SEE carried out separately, in fact, the combined impact could degrade the device performance more seriously, because of the greater numbers of oxide-trapped charges and interface states generated, which is more pronounced during multiple gamma irradiation and post-irradiation annealing. This phenomenon indicates that SEE is not only a transient effect, influencing whether the devices can be driven to failure, but also a potential threat to the long-term reliability of MOSFETs used in aerospace applications. [ABSTRACT FROM AUTHOR]

Fault tree analysis (FTA) is used to find and mitigate vulnerabilities in a system based on its constituent components. Methods exist to efficiently find minimal cut sets (MCSs), which are combinations of components whose failure causes the system to fail. However, traditional FTA ignores the physical location of the components. Components that are close to each other could be defeated by a single event with a radius of effect, such as an explosion or fire. This motivates the search for techniques to identify such vulnerabilities. Adding physical locations to the fault tree structure can help identify vulnerabilities in the overall system. Using this information requires extending existing solution methods or developing entirely new methods. In this paper, two solution approaches were explored. The first executes traditional FTA software, then searches for clusters in the resulting MCS to find these vulnerabilities. The second uses an evolutionary algorithm to search directly for volumes containing components that form cut sets. Results show that the evolutionary approach provided better answers (i.e., smaller volumes) overall and is suitable to identify vulnerabilities caused by proximity of components. However, the cluster approach performed well when evaluating higher numbers of locations and may be suitable in specific situations. Potential refinements to both methods are discussed. [ABSTRACT FROM AUTHOR]

A new algorithmic approach yields insights into the relationship between predicted and on-orbit synchronous dynamic random access memory (SDRAM) error rates on the Van Allen Probes. This article describes more than 5.5 years of data on Solid State Recorder Single Event Effects (SEEs) from December 4, 2012 to June 30, 2018. We compare observations with predictions from the early spacecraft design and give reasons for the large overpredictions. We analyze observed SEEs versus L-shell position and the memory device location on the Solid State Recorder electronic card. We examine the differences among the outlying SEE-susceptible devices on the two spacecraft. The inflight results demonstrate the conservatism of the predictions for the overall upset rate. [ABSTRACT FROM AUTHOR]

Recently there has been an increasing demand for more powerful processors for the next-generation space missions, such as communication and earth observation. The challenge is how to improve the reliability of the processor under the “single event effects” in orbit. We have previously proposed a new way of implementing any traditional software error detection and correction techniques at instruction level, capable of covering both the CPU and caches of “commercial off the shelf” processors. In this paper, a novel way of evaluation of the software protection is presented, based on a theoretical model and software injection experiments to predict the reliability of the whole processing architecture. The fault injection will evaluate the ability of the protection code to detect and recover errors in addition to the accuracy of the reliability models, by comparing the reliability of the theoretical predictions to the reliability of the injection experiments. Automatic compiler error detection and recovery improves the reliability of the system by reducing the error rate of “single event upsets.” In some benchmarks, the error rate was reduced to less than 1%. This research has been tested in two machines; Intel core i5-3470 and a Raspberry Pi 3. On the first processor, the overhead was less than 15%, and on the second one, the overhead was less than 17%. This research can also be ported to multiple high level languages, with the ability to cover multiple instructions and datatypes. [ABSTRACT FROM AUTHOR]

Real-time soft error rate of 65-nm QDRII+ static random access memory was measured on the Tibetan-plateau with an altitude of 4300 m. Error types including single-bit upset (SBU), multiple-cell upset (MCU), and burst errors were observed. The MCU ratio is 23%, with a maximum size of nine cells. Majority of the MCU events are vertically oriented along the well stripes. Monte Carlo simulations were further performed to study the characteristics of the neutron-induced secondary ions. Diverse secondary ion species, from the proton to Re, were found, which were significantly affected by the presence or absence of the tungsten layer. The impact of neutron energy on the linear energy transfer (LET), range, and deposited charge of secondary ions in the sensitive volume was revealed. [ABSTRACT FROM AUTHOR]

In this paper, a temperature-switching approach (TSA) was used to evaluate low-dose-rate (LDR) ionizing radiation effects on single-event transients (SETs) in linear bipolar circuits. The experimental results show that the SET phenomenon of bipolar circuits after irradiation using a TSA with 3-rad(Si)/s dose rate is basically consistent with the SET phenomenon of bipolar circuits after LDR of 0.01-rad(Si)/s irradiation, which is obviously different from the SET phenomenon of bipolar circuits after the high-dose-rate of 10-rad(Si)/s irradiation. The TSA for evaluating the enhanced LDR sensitivity (ELDRS) of bipolar devices can be applied to the rapid evaluation of the SET effect of the bipolar circuits with LDR irradiation. [ABSTRACT FROM AUTHOR]

The dependence of single-event transients on strike location is studied and integrated into the bias-dependent single-event model for circuit simulation. Two nondimensional parameters are introduced, including a drift factor and a diffusion factor to produce the accurate single-event current pulse consisting of drift and diffusion components for each related active region. By translating into the bias-dependent model, considering the current path between well contacts, and modeling the impact of bipolar amplification effects, it is able to predict the charge collection when striking at various strike locations. Circuit-level simulation results agree well with TCAD ones for various circuit blocks, including a single inverter, inverter chains of various layout designs, and OR3 gate. In addition, good agreement with experimental results has been reached, proving the reasonableness of the proposed circuit-level single-event effect (SEE) simulation approach. [ABSTRACT FROM AUTHOR]

Soft error effects due to the alpha particle and terrestrial neutron strike are investigated in a saddle fin DRAM using the 3D TCAD simulation. The strike location and angle dependency are investigated, and the worst-case incidence condition is studied. As the strike time is relevant for the error pattern, the strike during the write period is found to have minor effect, but the strike during the hold period shows data corruption. The inter-active disturbance is effectively suppressed due to the shallow trench isolation, but the inter-active ionizing radiation disturbance can be a potential risk as the capacitance of the storage capacitor continues to reduce with the DRAM technology scaling. [ABSTRACT FROM AUTHOR]

This paper presents two novel memory cell designs that can completely tolerate double-node upsets. First, a layout dependent cell is proposed. Since the cell has many redundant storage nodes, the cell achieves the following robustness: 1) In the case of 1 being stored, the cell can self-recover from any double-node upset (DNU) as well as any single node upset (SNU); 2) in the case of 0 being stored, the cell can self-recover from any double-adjacent-node upset (DANU), partial double-separated-node upset (DSNU) as well as any SNU. Any other DSNU can be tolerated by the cell due to the use of the layout approach. Second, a layout-independent cell is proposed that can self-recover from any DNU as well as any SNU. Simulation results validate the robustness of the proposed cell designs. Furthermore, compared with typical existing radiation hardened memory cells, the proposed layout-dependent cell saves 55.60% read access time and 33.76% write access time at the costs of 4.28% power dissipation and 39.01% silicon area on average, still low compared with layout-independent cell designs. [ABSTRACT FROM AUTHOR]

This brief first time presents single-event burnout (SEB) simulation results for conventional AlGaN/ GaN gate field plate MISFET (GFP-C MISFET), simultaneously, a hardened MISFET with electrode connected doped plugs in the buffer (EC-DP MISFET) is proposed for the first time. The SEB triggering mechanisms contain the back-channel effect and following impact ionization dominated by electron in the high field region. By comparing the simulation results from the GFP-C MISFET and proposed hardened EC-DP MISFET, the carriers induced by heavy ion can be quickly absorbed to drain and source electrode through EC-DP, so that the proposed EC-DP MISFET can achieve better SEB performance than conventional one. With a heavy ion having the linear energy transfer value of 0.6-pC/ $\mu \text{m}$ striking vertically, SEB threshold voltage obtained in GFP-C MISFET and hardened EC-DP MISFET is 280 and 338 V, respectively. [ABSTRACT FROM AUTHOR]

In this paper, a novel radiation-hardened 14-transistor SRAM bitcell with speed and power optimized [radiation-hardened with speed and power optimized (RSP)-14T] for space application is proposed. By circuit- and layout-level optimization design in a 65-nm CMOS technology, the 3-D TCAD mixed-mode simulation results show that the novel structure is provided with increased resilience to single-event upset as well as single-event–multiple-node upsets due to the charge sharing among OFF-transistors. Moreover, the HSPICE simulation results show that the write speed and power consumption of the proposed RSP-14T are improved by ~65% and ~50%, respectively, compared with those of the radiation hardened design (RHD)-12T memory cell. [ABSTRACT FROM AUTHOR]

Neuromorphic computing systems built with resistive random access memory (RRAM) are attractive solutions for implementing deep learning on-chip. In this paper, the single event and cumulative radiation damage susceptibility of a 1-transistor-1-resistor synaptic array architecture is investigated for the inference stage of a neuromorphic system. A physics-based SPICE RRAM model is developed to simulate the analog switching behavior of HfOx-based RRAM devices. SPICE simulations using the RRAM model are performed to capture the effects of transient heavy-ion strikes and experimental results obtained on GeSe-based RRAM devices are used to model the effects of cumulative radiation dose. Error patterns are fed into the software simulation of a multilayer perceptron, a representative artificial neural network for MNIST handwritten digit recognition. Radiation effects on the inference accuracy are analyzed. The results of the analysis indicate that the RRAM-based neuromorphic computing system is highly resistant to transient single-event effects due to the low cross section. The system is also shown to be tolerant to multi-Mrad levels of total ionizing and displacement damage dose. [ABSTRACT FROM AUTHOR]

Cross sections and failure in time rates for neutron-induced single-event burnout (SEB) are estimated for SiC power MOSFETs using a method based on combining results from heavy ion SEB experimental data, 3-D TCAD prediction of sensitive volumes, and Monte Carlo radiation transport simulations of secondary particle production. The results agree well with experimental data and are useful in understanding the mechanisms for neutron-induced SEB data. [ABSTRACT FROM AUTHOR]

The single-event transient response of a high-voltage complementary SiGe-on-silicon-on-insulator technology is investigated along with its temperature dependence using a pulse laser. The p-n-p silicon-germanium heterojunction bipolar transistor (SiGe HBT) shows a larger transient peak amplitude compared to the n-p-n SiGe HBT, which is largely related to the differences in total device volume and peak germanium content between the p-n-p and n-p-n devices. The effects of temperature on the transient response are also investigated using heaters and sensors mounted directly on the device-under-test package. The collector transient peak amplitude shows a negative temperature coefficient for a $V {_{\text {CB}}}$ of 0-V condition, for both the n-p-n and p-n-p devices. However, the temperature dependence of the transient peak amplitude becomes significantly weaker at $V {_{\text {CB}}}>0$ V. Calibrated TCAD simulations were performed to better understand the temperature dependence, and the simulations indicated that the electric field and mobility at higher $V {_{\text {CB}}}$ have a reduced temperature dependence than at a $V {_{\text {CB}}}$ of 0 V. The effects of self-heating are also explored using TCAD simulations and show that even under aggressive self-heating conditions, there is only less than 10% reduction in transient peak amplitude with the self-heating models turned on. The results shown suggest that this particular SiGe technology can be used for environments where highly energetic particles and high temperatures are encountered simultaneously. [ABSTRACT FROM AUTHOR]

This paper focuses on the radiation-induced dose and single-event effects (SEEs) on a color CMOS camera designed for space missions. The $\gamma $ -ray and proton tests are used to evaluate the tolerance against cumulative dose effects. The dark current of the image sensor is the main parameter impacted by dose effects. Heavy ions testing is performed to evaluate SEEs. single-event upset, single-event functional interrupt, and single-event latchup have been observed and mitigation techniques were proposed for specific space missions. [ABSTRACT FROM AUTHOR]