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Biometrics authentication is a very popular method to authorize a person to a system, device, or data. Fingerprints, Retina, Iris, Face, Voice, etc. are the most used Biometrics pattern to recognize and identify a person. A person's ear structure remains the same from his early childhood to old age as compared to other biometric organs in the human body. Thus, Ear can also be a source of a Biometric pattern to identify a person, since it is a visible organ and its image can be easily taken. In this paper, we approach identifying a person using 2D ear imaging. You Only Look Once(YOLO) machine learning (ML) algorithm is used to classify the ear images and identify their source person. We collect a standard ear dataset (EarVN1.0 Dataset) from 164 individual persons with a total of 27,592 training images. Randomly 820 Images, 5 images of each 164 individuals are selecting for testing purpose. The model training accuracy is 82.5%, and the testing accuracy is 75%. The model is implemented using the python language framework and GPU-based implementation. The model training accuracy is 82.5%, and the testing accuracy is 75%. The model is implemented using the python language framework and GPU-based implementation on Jupyter Notebook at Google Colaboratory server.

A wafer is a thin slice or substrate of semiconductors used for the fabrication of microelectronics devices. Thus, a large scale of precision is needed to make the microdevices work properly and to meet the requirements. Wafer test is an important step in wafer manufacturing to validate the activity of the microdevices and produces pictures of each wafer based on the electrical measurement of each of the devices on the wafer. Wafer shows different patterns while testing based on the requirement gap present on some of the devices on the wafer. To detect this error pattern manually is almost an impossible and time-consuming act. Therefore, we are presenting a wafer map pattern recognition system based on some ensemble approaches. Three (3) different ensemble including bagging, boosting, and voting approaches are implemented. Bagging performs relatively better than the others.

Music is an important part of our life as it expresses feelings including joy, happiness, and pain of life. It relieves mental stress by its rhythmic tunes and also becomes a source of entertainment. The modern song involves different instruments and thus combines different genres as well. Music genre classification plays an important role to provide the internal instrumental behaviors of a song specially to trace the signal style, rhythmic structure, and harmonic content of an instrument. Commonly musical genre annotations are performed manually. Besides some automatic machine learning tools including Naive-Bayes, Decision Trees, k NearestNeighbors, Support Vector Machines, and Multilayer Perceptron Neural Nets are employed to classify musical genres. Convolutional is an advanced Neural Network mainly used for image processing, however, it is also performing better in classification with less parameter than multilayer perception. Till now statistical pattern recognition classifier and source separation technique are performed to classify the Marsyas data set. We are proposing a CNN framework to classify musical genre audio signals from the Marsyas data set and analyze the performance.

This paper presents a detailed discussion on the structures, performances, advantages, and limitations of tunnel field-effect transistors (TFETs). The paper includes a comparative study of the performances of conventional metal-oxide-semiconductor FETs (MOSFETs) and TFETs. The paper describes the electrical characteristics of TFETs and explores various recently reported architectures and approaches to improve the device performances.

In this paper, a new topology for dynamic logic-based full adder is proposed and analyzed. The XOR and XNOR gates are generally used as basic logic blocks in the full adder design. In this work, the modified architectures of XOR and XNOR logic gates are used in the implementation of full adder circuit. The suggested topology of XOR/XNOR gates exhibits a full logic swing. The proposed full adder circuit is simulated using the conventional 180 nm CMOS process technology. The simulation results using SPICE simulation tool demonstrate that there are substantial improvements in power dissipation and speed of the proposed circuit compared to the earlier reported designs.

Medical image segmentation is a challenging task in the field of medical science. Many tools have been developed by engineers to detect tumor and perform analysis of medical images. The most important and effective role in the entire procedure is played by image segmentation tool. It has attracted a lot of attention in the last so many years and researchers are continuously working to increase its quality and attributes. This paper is about the detection of brain tumor using a support vector machine based interface using GUI in Matlab. The interface can use any combination of segmentation, filtering and other techniques to achieve optimum results. The algorithm begins with noise removal and feature extraction using discrete wavelet transform. The extracted features include both first and second order features. These features are reduced to the desired level using principle component analysis. These features are also used to train the kernel SVM. The classification is then performed by support vector machine. The interface of GUI is developed using Matlab guide.

A novel method for squaring binary numbers using Vedic mathematics is proposed in this paper. The implementation of the binary squaring circuit uses the improved Vedic multiplier architecture. The circuit is designed in VHDL using the ModeSim tool from Mentor Graphics. The circuit synthesis is performed using the Xilinx ISE 14.1. The HDL-based simulation is presented for 4-bit and 8-bit. The design can easily be expanded for large bit sized inputs. The device utilization and delay comparison are presented using different families of FPGA. The binary squaring circuit presented in this paper show better speed performance than the previously reported squaring circuits.

This paper proposes a novel method using Vedic mathematics for calculating the square of binary numbers. An improved Vedic multiplier architecture is used in the binary squaring circuit. The circuit is further improved by using parallel prefix adder. Parallel prefix adder provides the best delay performance at the expense of area overhead. In this work, the parallel prefix adders like Kogge-Stone adder, Brent-Kung adder, Sklansky adder, Ladner-Fischer adder and Han-Carlson adder are used. The circuit is designed in Verilog HDL. The circuit synthesis has been performed in Xilinx ISE 14.7. Simulation has been performed for 4-bit and 8-bit designs. Performance comparison has been performed taking into consideration several parameters measured on different FPGA families. An improved speed performance is observed in this paper when compared with the previously reported circuits.

Steel is one of the most important building materials of modern times and the production process of flat sheet steel is complicated. Before shipping or delivering steel, sheets need to undergo a careful inspection procedure to avoid defects and thus localizing and classifying surface defects on a steel sheet is crucial. In this study, we advance the steel defect inspection methods by designing machine learning models that aim to detect multi-level defects from sample steel sheet images and classify them according to their corresponding classes. We explore two (2) deep learning methods including U-NET and Deep Residual U-NET to solve the steel defect detection problem with a Dice coefficient accuracy of 0.543 and .731 correspondingly.

The paper presents the HDL implementation of a novel multiplier algorithm based on the combination of Vedic mathematics and Booth-Wallace tree multiplier. An $8 \times 8$ multiplier is implemented in VHDL. The HDL code is simulated and synthesized using ModelSim and Xilinx ISE 14.1, respectively. The performance parameters of 8-bit multipliers implemented using various algorithms are compared in this paper. The comparison results exhibit that the proposed algorithm is faster than other multiplier algorithms.

The activities of many primary sectors depend on the weather for production, e.g. farming. The climate is changing at a drastic rate nowadays, which makes the old weather prediction methods less effective and more hectic. To overcome these difficulties, the improved and reliable weather prediction methods are required. These predictions affect a nation's economy and the lives of people. To develop a weather forecasting system that can be used in remote areas is the main motivation of this work. The data analytics and machine learning algorithms, such as random forest classification, are used to predict weather conditions. In this paper, a low-cost and portable solution for weather prediction is devised.

This paper presents a modified binary multiplier using Vedic mathematics. The paper proposes a modification in the previously published Vedic multiplier circuit. The suggested modified Vedic multiplication technique is more efficient in terms of delay and area. The proposed circuit is implemented in VHDL. The Mentor Graphics ModelSim tool is used for HDL simulation, and the Xilinx ISE Design Suite 14.1 is used for circuit synthesis. The simulation is done for 4-bit, 8-bit, and 16-bit multiplication operations. In this paper, the simulation waveforms are shown only for 4-bit multiplication operation based on the modified Vedic multiplication technique. The proposed method can be extended for a larger bit size. The performance evaluation in terms of speed and device utilization is compared with the previously reported Vedic multiplier architectures. The proposed design exhibits a speed improvement compared to the multiplier architectures available in literature.

Hand sign recognition is an essential part in robot control, human computer interaction, communication with deaf or speech impaired people etc. where performance and time complexity are very important factors. Numerous researches are conducted to offer solutions for sign language classification. Among them, orientation based hashcode (OBH) model recognizes sign images at a lower time but with A lower accuracy. In this paper, we propose a system which consists of OBH, additional feature extraction and machine learning method. It is able to classify sign language finger spelling alphabets efficiently within a short time. Feature vector using Gabor filter and number of fingertips are used as attributes alongside orientation based hashcode for classification through Artificial Neural Network (ANN). Before feeding features into ANN model, Principle Component Analysis (PCA) is used to omit the redundant features. The dataset contains 576 American Sign Language (ASL) alphabet sign images (both RGB and depth images) of 24 different categories which are captured by Microsoft Kinect sensor. The proposed methodology is proved to be 95.8% accurate against randomly selected test dataset and 93.85% accurate using 9-fold validation.

In designing digital filters, Multiply-Accumulate (MAC) unit is used. MAC comprises of multiplier, adder and an accumulator. Faster adder and multiplier circuits are required for high speed MAC unit. But MAC based structures have disadvantages like high power dissipation, slow processing etc. The multiplication operation where input data is to be multiplied with the fixed coefficients considerably took large place to store their temporary data. So, memory based multiplication technique substitute multipliers to reduce area and latency of system. Distributed Arithmetic (DA) is one of the memory based technique. DA based technique substitute multipliers in FIR filters. In this paper, detailed analysis is presented for designing 16-Tap FIR filter using DA and Off-Set Binary Coding (OBC)-DA in VHDL. Synthesis is done using Xilinx ISE for Virtex-4 ML 402. Area, delay and power analysis is performed using Synopsys Design Compiler for 32/28 nm std_cell.

Vedic maths based multiplier is a novel and high speed multiplier. Adder is one of the main components used in this technique. Using fast adder will enhance the overall performance of the Vedic multiplier. In this work, comparative analysis is done using different adder architectures in Synopsis Design Compiler with different standard cell libraries at 32/28 nm. Various Adder topologies like Ripple Carry Adder (RCA), Carry Select Adder (CSA), Square Root Carry Select Adder (SQRT-CSA), Common Boolean Logic (CBL) and Binary to Excess one Converter (BEC) are used to compare area, delay and power. Designing is done for 8-bit, 16-bit, 32-bit and 64-bit Vedic multiplier using the above adders. It is found that 64-bit Vedic multiplier using SQRT-CSA adder is approximately 5% faster than RCA-CSA and BEC, 75% faster than CBL and RCA.

Road traffic management is an ongoing challenge. Machine vision (image processing), RFID gates, aerial surveillance, and/or remote sensors technologies are usually used to reduce traffic management problems. However, their major drawbacks are installation difficulties, maintenance over the time, error handling, coverage and cost effectiveness. Thus, low-cost, flexible, easily maintainable and secure traffic management support systems are in demand. Internet-based real time bidirectional communication can be an alternation to solve most of the addressed problems. It can provide significant benefits over the existing surveillance technologies in use to monitor road traffic condition. In addition, dynamic routing is a vital requirement to make the proposed system more realistic. Therefore, decision tree based logic is applied to calculate the road segment weights and provide dynamic routing. The results indicate that the proposed traffic management support system/tool with dynamic routing (weights) is much more effective to find the optimal routes.

In this paper, we present the principles of a low operational-cost but flexible Internet-based traffic management support system. Most of the past systems were implemented with machine vision (image processing), RFID gateways, aerial surveillance, and/or remote sensors technologies. However, the major drawbacks of the above mentioned systems are their installation difficulties, maintenance over the time, error handling, coverage and cost effectiveness. Nevertheless, they consist unicast/one way communication (client to server only). The proposed system will bring real time bidirectional communication between the clients and the servers. Accurate and real-time traffic situation can be plotted at any given time. In addition, it would make better utilization of the existing technologies to achieve the goals. Users will be able to get help/advice from the system to find the optimized and cost effective way to reach from source to destination or vice versa.

A 16-bit Square Root Carry-Select Adder (SQRT CSA) is implemented and analyzed in this paper. The SQRT CSA is an architecture level modification to reduce area and power dissipation as compared to that of conventional CSA. Conventional CSA with Cin=1 block is replaced with binary-to-excess-1 converter (BEC) in the modified SQRT CSA structure. The architecture of 16-bit CSA is configured into five different stages with progressivley increasing data size. In order to realize 16-bit CSA, the basic building blocks, e.g., XOR gate, AND gate, 2:1 Mux, half adder (HA) and full adder (FA) are implemented using CMOS transmission gate (CMOS TG). The ripple carry adder (RCA) and binary-to-excess converter (BEC) of different bit sizes are also implemented. Transistor level schematics are drawn using Mentor Graphics Design Architect and simulations are carried out using Eldo with TSMC 0.35μm CMOS technology and supply voltage of 3.3 V.

The paper proposes a systematic design methodology for bit-serial multiplication. The proposed approach is a modified method for performing traditional multiplication. This paper presents a general technique for N×N bit-serial multiplication used in signal processing. HDL implementation and simulation of 4×4 bit-serial multiplier is discussed. Synthesis is performed using Xilinx ISE with Virtex-4 ML402 FPGA board.

This paper demonstrates the idea of utilizing Source-Coupled Logic (SCL) concept in dynamic logic realization. The technique gives dual (normal as well as complemented) output. As compared to conventional dynamic logic style, by using the mentioned realization, charge sharing and contention current problems can be avoided to a large extent. The sizing requirement of keepers is not stringent in the proposed realization. The functional evaluation of the realized circuit is improved. The SPICE simulations are performed with 0.35um CMOS technology.

The DCT transform has been extensively used in various digital image coding schemes and image compression standards. In this paper, VHDL implementation of Odd Discrete Cosine Transform (ODCT-II) coefficient computation using independent update algorithm is discussed. By independent, we mean ODCT coefficient computation of shifted data sequence doesn't require ODST coefficients of previous data. The running input data sequence is sampled using a rectangular window. The independent update algorithm is used to compute the transform coefficients of the shifted sequence using Distributed Arithmetic (DA) approach. The design is synthesized using ISE 10.1 and implemented on Vertex 4. Implementation shows that DA based approach is more efficient in terms of device utilization.

Human gesture recognition allows for a more natural human machine interface eliminating expensive training for human's to get accustomed to the machines and avoid costly mistakes that follow till one becomes an experienced user. With advances in technology embedded devices with additional processing power and memory are becoming available. This is making our machines more capable and complex to operate, though the cost of human error is even higher. Hand gesture recognition offers a solution, but it still remains a very time and space complex problem when most non statistical methods are employed. Thus most embedded systems with limited space and processing power are unable to support hand gesture recognition. The paper introduces a statistical method which converts image contour to orientation based hash codes in-order to project it to a 3D-address space bounded by hamming distance. The main objectives are to reduce time, space complexity along with complete rotation invariance and online scalability. The implemented method proved to be 82.1% accurate against 1000 images comprising of 10 distinct static hand gesture sets.

Workflow model is a computerized model to run business process in commercial industries. However, it can be used in different other scenario, especially where the real time environment is similar to distributed environment. In this paper, we have focused on how workflow model in cloud computing can help to maintain the rescue and reorganization activities of disaster situation. The proposed architecture models disaster situation as a distributed cloud system‥ In this regard, existing models deal with temporal and static constrain. However they cannot be used to keep pace with an uncertainly dynamic system like disaster management system. Therefore a dynamically configurable and changeable workflow model is proposed. Multi Agent System (MAS) is used to simplify system architecture. Another contribution of this paper is to define a dynamic adaptive scheduling algorithm that offers an appropriate execution sequence of workflow activities. At the same time proposed algorithms are also capable of resource allocation and imposing dynamic control over the system. Proposed algorithms also consider both successful and failed situation in case of scheduling different activities.

Discrete Cosine Transform (DCT) has been extensively used in various digital image coding schemes and image compression standards. It is known that in most practical cases, the DCT based schemes out-perform in terms of compression ratio. In literature, designing for 1-D Even DCT (EDCT) is given using butterfly structure. It is difficult to implement Odd-DCT (ODCT) because of its difficulty in forming butterfly structure. In this paper, hardware implementation for computation of the ODCT-II coefficients using Distributed Arithmetic (DA) approach is discussed. It is synthesized using ISE 10.1 and implemented on Vertex 4. Implementation shows that DA based approach is more efficient in terms of device utilizations.

A novel technique for digital multiplication is presented that is quite different from the conventional method of multiplication like add and shift (D. Crawley and G. Amaratunga, 1996). This also gives chances for modular design where smaller block can be used to design the bigger one. This will help in designing multiplier in VHDL, as its give effective utilization of structural method of modeling (Hwang Kai, 1979). In this paper the general technique for NxN multiplication is proposed. This gives less computation time for calculating the multiplication result for NxN bit.

One of the important issues in image feature is the area of objects in the image. In this paper we propose an area finding algorithm to measure the area of an image object. This method finds the area by polygonal approximation of image objects. A sequential fine-tuning of this polygon is used to estimate the actual area from polygon area. This area modification sequence is used as a topological description of an image object and used as feature in image matching.