Design and Analysis of Distributed Arithmetic based FIR Filter

In designing digital filters, Multiply-Accumulate (MAC) unit is used. MAC comprises of multiplier, adder and an accumulator. Faster adder and multiplier circuits are required for high speed MAC unit. But MAC based structures have disadvantages like high power dissipation, slow processing etc. The multiplication operation where input data is to be multiplied with the fixed coefficients considerably took large place to store their temporary data. So, memory based multiplication technique substitute multipliers to reduce area and latency of system. Distributed Arithmetic (DA) is one of the memory based technique. DA based technique substitute multipliers in FIR filters. In this paper, detailed analysis is presented for designing 16-Tap FIR filter using DA and Off-Set Binary Coding (OBC)-DA in VHDL. Synthesis is done using Xilinx ISE for Virtex-4 ML 402. Area, delay and power analysis is performed using Synopsys Design Compiler for 32/28 nm std_cell.