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Condition monitoring of insulated gate bipolar transistor (IGBT) modules is an effective way to improve the transient performance and reliability of modular multilevel converters (MMC). This article proposes a novel bond wire failure monitoring method for the multichip IGBT modules in the MMC half-bridge submodule (SM) structure. The collector voltage undershoot VCA(np) of the complementary IGBT switch is measured during the turn-off switching transition of the controlled IGBT switch. VCA(np) is sensitive to the induced voltage over the stray inductance of the IGBT bond wires and provides high sensitivity as a health indicator. The non-intrusive measurement technique is demonstrated using a half-bridge circuit during the turn-off transition of the controlled IGBT, while its complementary switch (i.e., the device under test) is in the off state. Theoretical analysis and experimental results show that the parametric drift due to wire bonding failures can be effectively monitored with high specific relative sensitivity and granularity. To ensure its effectiveness in practical applications, the influence of load current, SM capacitor voltage, and junction temperature is discussed. In addition, a readout circuit is designed featuring the integrated desaturation detection and voltage peak detection, which offers both the short-term overcurrent fault protection and long-term bond wire aging monitoring functions. [ABSTRACT FROM AUTHOR]

Power-electronic-converter-induced motor bearing currents are a widespread problem in the field of electrical drives. Parasitic capacitances between the electrical machine's parts provide a path for leakage currents, which finally harm metallic ball bearings. Remembering that end-windings have a significant contribution in building up stray capacitances, a countermeasure affecting both the lamination stack and end-winding areas is needed. This article focuses on a countermeasure against the noncirculating bearing currents in the cluster of solutions at the motor side. The electrostatic shielding approach, which is a known principle to reduce capacitive couplings, is applied in electrical machines every now and then. In this article, the principle of slot-embedded grounded electrodes is extended to cover also the end-windings. Thus, the electrodes provide a better shaft-to-ground voltage mitigating effect compared to the case where electrodes are applied only in the lamination stack area. The feasibility and effectiveness of such a countermeasure are investigated. Different options in terms of scaling of both the machine size and diameter of the electrodes were analyzed and corresponding conclusions were pointed out. [ABSTRACT FROM AUTHOR]

Multilevel inverters (MLIs) featuring reactive power ability and common ground (CG) have become much popular in transformerless grid-tied photovoltaic applications. A switched-capacitor (SC) based five-level transformerless inverter configuration is thus proposed in this article, which requires only six switches, one diode, three capacitors, and one input dc voltage supply. Notably, only four power switches are operated in high frequency, thus, the switching losses are reduced. Moreover, the presented topology can effectively tackle the leakage current problem using a CG architecture. A multicarrier phase disposition pulsewidth modulation strategy is employed to achieve reactive power regulation and SC voltage self-balancing. To achieve the neutral point voltage balance of the presented five-level inverter, a simple closed-loop voltage-balancing control method is proposed. The operation principles with modulation strategy and voltage self-balancing of SC are discussed in depth. Comparisons between the proposed and the state-of-the-art MLIs are presented in detail. Finally, experimental tests on a single-phase 1.1-kW prototype validate the appropriate performance of the proposed inverter. [ABSTRACT FROM AUTHOR]

Online aging monitoring is the basis for high reliability operation of Insulated gate bipolar transistors (IGBTs). Most monitoring methods focus on the package-related aging. Leakage current (Ileak) has been proposed as a potential chip-related aging (CRA) indicator for IGBTs. However, this method has not been implemented online due to the difficulty in accurate online leakage current measurement. An effective online CRA monitoring method is still required for IGBTs. A novel online CRA monitoring method based on Ileak for IGBTs is proposed in this article. First, an online Ileak measurement circuit is proposed. Second, based on this circuit, an aging monitoring strategy is presented. Finally, accelerating aging tests validate the effectiveness of the proposed method. The on-state voltage drop is selected as an aging indicator for comparison. The proposed method has three advantages. The online CRA monitoring is achieved. It can be used in slight aging situation with high sensitivity because Ileak is linear to the CRA levels. The measurement circuit required by this method is simple and low-cost. [ABSTRACT FROM AUTHOR]

In photovoltaic systems, common-mode voltage (CMV) generates leakage current, which shortens the insulation lifespan and causes safety problems. As for neutral-point-clamped (NPC) inverters, zero CMV PWM (ZCMV PWM) can be implemented to eliminate leakage current, but unable to balance neutral-point (NP) voltage in dc side. This article presents a novel modulation technique for NPC PV inverter. The strategy contains ZCMV PWM and another two modulation modes which keeps CMV constant in one switching period, so as to eliminate leakage current. In order to balance NP voltage, NP current is adjusted by selection of optimal modulation mode and the leakage current is still well eliminated during the process of balancing NP voltage. Compared with conventional ZCMV PWM, the proposed scheme can remove both leakage current and NP voltage deviation. The output performance and limitations of the proposed method are also introduced in the paper. Experiments are provided to verify the validity of the proposed method. [ABSTRACT FROM AUTHOR]

A dual-transformer-based hybrid dual active bridge (DAB) converter for plug-in electric vehicle charging to cope with wide load voltages is introduced in this article. The control degrees of freedom are extended by splitting the leg and transformer of the conventional DAB converter (CDABC) in two parts. Based on the numerical analysis, the full-domain four-variable closed-form optimal trajectories targeting at the minimum root mean square value of the leakage inductor current is attainted, and the unified-segmental control strategy is proposed to handle the working modes shifting without the current inrush. As a result, the conduction losses and switching losses can be significantly reduced in boost mode compared to CDABC. The discussed converter and control strategy are verified by a 1.0-kW prototype. [ABSTRACT FROM AUTHOR]

Insulation aging of underground power cables may lead to severe fault and system outages. Condition monitoring of cable insulation is essential to maintain power system reliability. However, most existing insulation monitoring methods can only work in offline mode and cannot describe cable aging severity quantitatively. In this article, a novel online monitoring scheme for underground power cable insulation based on common-mode (CM) leakage current measurement is proposed. An online neutral-point voltage injection approach is proposed, and CM leakage current distribution model for both the cables with and without metal sheath under the injected voltage is derived. The insulation capacitance can therefore be monitored online without disturbance to the system operation. Simulations and experiments are conducted to prove the effectiveness of the proposed method. With the aid of a designed CM leakage current sensor, CM leakage current smaller than 5 mA can be detected and the accurate evaluation of aging severity is achieved. The key feature of the proposed method lies in its nonintrusiveness and online fashion: the normal operation of the system will not be interrupted, and accurate quantitative monitoring of cable insulation can be achieved online. [ABSTRACT FROM AUTHOR]

A normally-off SiC-JFET/GaN-HEMT cascode device is recently proposed, featuring a cascode configuration that incorporates a high-voltage (HV, e.g., 1200 V) silicon-carbide (SiC) junction field effect transistor (JFET) delivering the HV blocking capability and a low-voltage (LV) enhanced-mode (E-mode) gallium-nitride (GaN) high electron mobility transistor (HEMT) providing the normally-off gate control. This all-wide-bandgap device exhibits superior thermal stability and high switching speed compared to its counterparts, e.g., the SiC/Si cascode device. In this article, we study short-circuit (SC) characteristics of a 1200-V/80-mΩ SiC/GaN cascode device by considering the interactions between the SiC and GaN devices. The single-event SC withstand time (SCWT) of the demonstrated SiC/GaN cascode device is tested to be ∼3 μs under a dc-bus voltage (Vdc) of 600 V when the turn-on gate voltage (VG-on) is set to 5 V. The SC failure occurs due to the formation of hot spots induced by thermal-runaway leakage currents inside the SiC JFET. The SCWT of the cascode device could be improved by applying a moderate VG-on (e.g., SCWT = ∼6.5 μs at VG-on = 3.5 V under v dc = 600 V) without affecting the on-state resistance (r on). However, it is identified that current oscillations tend to be triggered during the SC period when VG-on is too low (e.g., lower than 3 V). The oscillation behavior is attributed to the energy stored in the interconnection parts between the SiC and GaN devices. The harmful oscillations could be suppressed by applying higher VG-on, which drives the SiC JFET into low-transconductance mode by modulating the drain-to-source voltage (VDS-G) of the LV GaN HEMT. [ABSTRACT FROM AUTHOR]

This article introduces a modulation technique that nearly eliminates the common-mode (CM) leakage currents in the transformerless (nonisolated) dual-inverter single-phase charger. This improvement allows for the safe use and commercialization of the transformerless charger, making superior charger efficiency, power density, and cost possible. The CM model of the system is derived to guide the choice of the modulation scheme. Simulations are conducted to validate the CM performance predictions derived analytically. Finally, an experimental 6.6-kW charger prototype is presented to verify the CM leakage current elimination. The experimental results show not only that the proposed modulation meets the required standards regarding CM currents, but also that it does so by a wide margin, and it even outperforms the isolated system used for comparison. [ABSTRACT FROM AUTHOR]

A novel single-stage doubly grounded transformerless inverter configuration which can buck-boost the output voltage is proposed in this paper. In this transformerless inverter configuration grid neutral is directly connected to PV panel negative rail which suppresses/eliminates the PV leakage currents. In addition, the tracking of maximum power point is possible for wide variation of weather conditions due to buck-boost voltage capability of inverter. Moreover, the proposed inverter topology has symmetrical operation in both half cycles hence injects negligible DC offset current in to the grid. Here the symmetrical operation of inverter is achieved due to one inductor is used for both half cycles of the grid. The proposed topology is realized using five switches, two of which work at 50 Hz and remaining three switches at high frequency which reduces overall semiconductor losses. Further, the proposed inverter topology is controlled through a newly developed modulation technique and possible working modes are analyzed and described thoroughly. For performance validation, the experimental analysis of grid connected proposed inverter is performed on a 1 kVA system and results show that proposed inverter feeds power in to the grid with lesser THD while achieving greater efficiency. [ABSTRACT FROM AUTHOR]

The occurrence of frequent high impulse currents during the process of switching-on AC filter banks can accelerate the aging of arresters in ultrahigh-voltage direct-current (UHVDC) and HVDC transmission systems, threatening the safe operation of converter stations. Therefore, impulse aging tests with different current amplitudes were performed on zinc oxide (ZnO) varistors under a negative polarity 15/35 μs impulse current to provide a basis for the aging evaluation criteria of AC filter arresters in UHVDC and HVDC transmission systems. The ratios of even-order to basic resistive harmonic components linearly increase with the number of impulse groups and suddenly decrease after complete damage occurs. The variation trends of the ratios of even-order to basic resistive harmonic components were analyzed and discussed based on the current waveform and amplitude-frequency characteristics of the resistive component and the DC V-I characteristics. Based on the results, a new criterion for the unipolar impulse aging of the ZnO varistor is proposed, i.e., the ratio of second to basic resistive harmonic components, and the application of ZnO varistor even-order harmonic characteristics in online monitoring is briefly discussed. [ABSTRACT FROM AUTHOR]

In this article, a new inverter unit is proposed. It is a compact switched-capacitor-based inverter, which is combined of four switches, two diodes, and four capacitors. Since this inverter unit is a mid-point-clamped inverter, it can mitigate the capacitive leakage current in many applications. One of the main applications of the proposed inverter is in grid-tied photovoltaic systems, where the common-mode current brings many challenges. Other than the mentioned feature, the proposed inverter includes the following advantages: 1) spontaneous balancing of the voltage across the capacitors without needing any control system or auxiliary circuits; 2) capability of full reactive power transfer; 3) low voltage stress on the capacitors compared to common three-level inverter topologies (NPC, T-type-NPC, FC, etc.); and 4) symmetric switching sequence, which causes a continuous input current. The feasibility and versatility of the proposed inverter unit is validated by experimental tests, which are conducted by using a lab-scale prototype. [ABSTRACT FROM AUTHOR]

Conventional Schottky diodes have a switching limit of ideality factor larger than unity due to the thermionic emission. In this work, cold source diodes (CSDs) using cold metals of monolayer 2H phase MX2(M = Nb, Ta; X = S, Se) as the injection source are proposed and investigated by first-principles quantum transport simulations. Different from the conventional Schottky diode, CSDs can break the ideality factor limit of unity and reach steep switching. Cold metals such as 2H MX2are metallic but have energy gaps around the Fermi level. Therefore, high-energy electrons can be effectively filtered and the leakage current is suppressed at off-state. It is shown that the ideality factor of CSDs can be smaller than 1 over eight decades with a minimum of 0.17. At the same time, giant negative differential resistance is realized in CSDs and the peak-to-valley ratio (PVR) can be over 106with a peak current over 100 $\mu \text{A}/\mu \text{m}$. [ABSTRACT FROM AUTHOR]

A modular model-predictive control (MPC) method for a nonisolated three-phase $LCL$ grid-connected converter is proposed with zero-sequence voltage control and regulated third-harmonic injection capabilities. The control method is proposed with the combination of a modified three-phase $LCL$ converter topology to stabilize the common-mode voltage. The control mechanism consists of two layers: 1) the central-level control of $dq$ -sequence output current control cascaded with 2) the local-level control of zero-sequence voltage three-phase inductor current/capacitor voltage MPC. No grid-side inductance value is needed for the two-layer cascaded control structure, which both improves the dynamic performance from the inner MPC loop and avoids the MPC parametric error caused by the uncertainty of grid-side inductance. With the zero-sequence MPC, the common-mode voltage and leakage current can be attenuated without a bulky isolation transformer. A regulated third-harmonic injection (RTHI) method is designed based on the zero-sequence voltage control and the proposed modified converter topology to improve the dc bus utilization and avoid the overmodulation issue. Compared with the conventional third-harmonic injection methods, no extra harmonics are injected to the grid, and there is no need for a specialized grid total harmonic distortion optimization algorithm with the proposed zero-sequence-controlled RTHI. The stability and robustness of the proposed RTHI method are also improved with the zero-sequence MPC regulation. In addition, the modular concept of the local MPC module enables the extensibility for the power converter control with a flexible number of phases. The dynamic performance, leakage current attenuation, dc bus utilization, and grid-connection power quality of the proposed MPC method with RTHI have been validated experimentally. [ABSTRACT FROM AUTHOR]

In this article, a multioutput-based transformerless hybrid solar inverter (TLHSI) with no right half-plane zero (RHPZ) and reduced common-mode leakage/ground current is presented for photovoltaic (PV) based microgrid applications. In the proposed multioutput TLHSI, two magnetically coupled inductor coils are placed between the input and dc output sides along with a dc-link capacitor to continuously provide the stored energy to the dc load so that the RHPZ is eliminated and, thus, makes it a minimum phase system. Furthermore, a hybrid unipolar sinusoidal pulsewidth modulation technique is established to nullify the high-frequency components of common-mode voltage across the PV to ground stray capacitor. Also, it normalizes both dc and ac loads at the same instant from a single dc input during each operating state of the proposed TLHSI. The shoot-through issue is resolved in the proposed TLHSI, which increases the system reliability. Furthermore, as the deadtime is not required in between the switching pulses, the quality of the inverter output voltage improves. The performance analysis of the proposed TLHSI is compared with the existing topologies. To validate the performance of TLHSI, a scaled down 340 W laboratory prototype is developed. [ABSTRACT FROM AUTHOR]

Power inverters for distributed photovoltaic (PV) power generation systems usually need to fulfill several requirements, e.g., the safety, the voltage boost capability, and the reduced volume and the cost. An improved transformerless single-phase quasi-single-stage common-mode PV inverter with four switches and an improved unipolar modulation strategy are proposed in this article. The inverter features double-grounded to solve potential safety issues caused by the leakage current. In addition, its voltage boosting is accomplished by a quasi- single-stage conversion structure so that PV system efficiency can be improved. Meanwhile, it benefits continuous input current so is suitable for PV application. In this article, the operation principle of the proposed inverter, the improved modulation strategy, and two grid-tied control strategies are introduced. The voltage and current stresses of the components are analyzed, and parameter design guideline is further given. Both the off-grid and grid-tied experiments were conducted to verify the theoretical analysis. [ABSTRACT FROM AUTHOR]

This article presents a fully integrated RF energy harvester (EH) with 30% end-to-end power harvesting efficiency (PHE) and supports high-output voltage operation, up to 9.3 V, with a 1.07-GHz input and under the electrode model for neural applications. The EH is composed of a novel ten-stage self-biased gate (SBG) rectifier with an on-chip matching network (MN). The SBG topology elevates the gate-bias of transistors in a nonlinear manner to enable higher conductivity. The design also achieves $>$ 20% PHE range of 12 dB. The design was fabricated in 65-nm CMOS technology and occupies an area of 0.0732 mm2 with on-chip MN. In addition to standalone EH characterization measurement results, animal tissue stimulation test was performed to evaluate its performance in a realistic neural implant application. [ABSTRACT FROM AUTHOR]

Selective area doping technique is essential for diversifying semiconductor device structures. In this letter, selective high-resistance zones on $\beta $ -Ga2O3 wafers were successfully achieved by a high-temperature oxygen annealing process. Polysilicon, which proved to have an ideal blocking capability against oxygen annealing ambient, was employed as an annealing cap layer to prevent local carrier concentration changes during annealing. Based on this unique process approach, we further demonstrate a high-resistance anode edge termination of Schottky barrier diodes, which can considerably reduce the leakage current and increase the breakdown voltage of the devices. This research broadens the device manufacturing method and promotes the development of Ga2O3 devices. [ABSTRACT FROM AUTHOR]

An integrated bootstrap diode emulator is experimentally investigated, including a high voltage (HV) junction field effect transistor (JFET) with adjustable pinch-off voltage ($\text{V}_{{\mathrm {P}}}$) and a medium voltage (MV) diode. It features substrate leakage current suppression, and it can be integrated to 600 V N-type epitaxial (N-epi) Bipolar-CMOS-DMOS (BCD) technology. The HV JFET is formed in a part of the high voltage isolation region and the MV diode is formed outside of the high voltage isolation region. In HV JFET, the extending P-type buried layer (PBL) is introduced as the back gate to adjust $\text{V}_{{\mathrm {P}}}$ of JFET. Since JFET is easy to pinch-off, and $\text{V}_{{\mathrm {P}}}$ of JFET is much lower than breakdown voltage (BV) of MV diode, the bootstrap diode emulator can obtain a high BV of 970 V at block mode. Moreover, BV of MV diode depends on the thickness and doping concentration of N-epi rather than the doping concentration of N-type buried layer (NBL). Thus, the highly doped NBL layer can be introduced in the junction of N-epi/P-sub to further suppress the substrate leakage current at conduction mode. Besides, due to the fact that HV JFET is a majority carrier device, the equivalent reverse recovery characteristic of the bootstrap diode emulator is also competitively, and the equivalent reverse recovery process is also qualitatively analyzed. [ABSTRACT FROM AUTHOR]

The transcutaneous energy transmission system (TETS) has been studied for wireless power supply in ventricular assist devices embedded in the body. To be approved as a medical device, it is necessary to measure the high-frequency patient leakage current (Ip) and to suppress it to a safety limit below 10 mA. However, it is difficult to suppress because the terminal voltage and the frequency of the transmitting coil are extremely high (500 V and 400 kHz). In this study, we propose an original measurement method for Ip in TETS and measure the Ip. Furthermore, the suppression method of Ip is investigated using a high-frequency isolation transformer (HFIT) and an insulation sheet for transmitting coils. Consequently, an Ip of 17.14 mA is obtained when the HFIT without countermeasures and an insulation silicone sheet is used (Type A), whereas an Ip of 7.68 mA is obtained when using two series-connected HFITs and an expanded polystyrene sheet with a thickness of 3.58 mm (Type B). Thus, it is possible to drastically suppress Ip below 10 mA. Additionally, we define the combined capacitance CCom based on the series connection of the capacitance of the insulation transformer Cp and that of the insulation sheet Cc and calculate the theoretical Ip. The theoretical Ip decreases from 20.8 mA for Type A to 5.6 mA for type B. The calculation results of Ip are mostly in agreement with the measurement results, indicating that a reduction in CCom is important for suppressing Ip of the TETS. [ABSTRACT FROM AUTHOR]

The leakage current which flows on the surface of dielectric rods under high voltage involves a series of events which include partial arcing, discharges and corona, these phenomenon are highly non-linear. These sequence of events render the leakage current signal to be very much chaotic. In the present work, the process of delay-embedding is employed to study the phase-portrait of the signal, further Lyapunov Exponents are computed to characterize the chaotic nature of the leakage current. The main focus of the study is intended to understand the chaotic nature of leakage current behaviour over the ageing period and to determine the degree of degradation on the dielectric rod surface. [ABSTRACT FROM AUTHOR]

This letter proposed a decentralized control method to attenuate the circulating current among the grid-connected inverters without extra cost on the communication. Based on the combination of cascaded model predictive control (MPC) and modified $LCL$ filter topologies, the developed method can locally limit the circulating current for different types of inverters, e.g., single/three-phase grid-connection, and various applications, e.g., shunted or distributed inverters with/without common dc bus, respectively. The merits of the proposed method include the following. 1) Decentralized circulating current control without the need of a central controller or the corresponding communication to collect the sampling and calculate the common mode components for leakage current attenuation among different inverters. 2) Generalized control method that can be applied to single/three-phase inverters for both shunted and distributed inverters with/without common dc bus applications. 3) No synchronization is needed for pulsewidth modulation signals among different inverters to attenuate the circulating current. 4) Cascaded MPC without the need of individual inverter’s grid side uncertain filter parameters for the attenuation of circulating current and system parametric modeling. 5) Better transient performance with the inner loop MPC. The experimental results verified the proposed method. [ABSTRACT FROM AUTHOR]

Transformerless inverters, most of which are H-bridge inverters, have been widely used and studied in grid-connected power systems in the last decades. However, the H-bridge inverter is affected by the low- and high-frequency common-mode voltage between the input and output terminals, resulting in a large common-mode leakage current. An alternative solution is to connect the ground of the input terminal to the output load or grid, that is, the dual-grounded inverter. In this case, the low- and high-frequency common-mode voltages can be mitigated or eliminated. As a matter of fact, scholars have made several research results on dual-grounded inverters. However, as of now, there is still no literature that comprehensively and systematically summarizes these research results. To fill this gap, this article classifies different types of dual-grounded inverters from the perspective of topology for the first time, and compares and summarizes their advantages and disadvantages. More than 60 works of literature have been reviewed to identify the practical implementation challenges and research opportunities in the application of dual-grounded inverters. [ABSTRACT FROM AUTHOR]

This article presents a bipolar junction transistor (BJT)-based CMOS temperature-to-frequency converter (TFC). A relaxation oscillator (ROSC) consisting of an integrating capacitor, a current source, and a comparator converts the ratio of the complementary-to-absolute-temperature (CTAT) voltage to the proportional-to-absolute-temperature (PTAT) voltage created by the BJT core to frequency. To improve the temperature accuracy, we incorporate a capacitor flipping technique to remove an offset of the comparator and a settling time error when resetting the integrating capacitor. Moreover, bootstrapped NMOS switches with the triple well structure are implemented to suppress leakage current and prevent from forming parasitic BJTs when the negative CTAT is applied to them by the proposed flipping technique. The prototype fabricated in a 0.11- $\mu \text{m}$ CMOS process consumes 3.1- $\mu \text{W}$ power and occupies a 0.025-mm2 active area. Measurements of 18 samples with the digital trimming show an inaccuracy of $\pm 1~^{\circ }\text{C}$ ($3\sigma$) from $- 40\,\,^{\circ }\text{C}$ to $140~^{\circ }\text{C}$. The area- and energy-efficient TFC is applicable to monitor the temperature inside integrated chips. [ABSTRACT FROM AUTHOR]

Metal halides have been demonstrated to be promising candidates for X-ray detectors. However, its large leakage current caused by the severe ion migration and intrinsic defect substantially degrades device performance. In this work, an asymmetric BA2CsPb2I7-CsPbI3 planar heterojunction X-ray detector is designed to suppress the leakage current. Both experimental and theoretical calculations demonstrate that: 1) enlarged ion migration energy (0.80 eV) and conductivity mutation at the interface ensure stable baseline and suppress leakage current; 2) CsPbI3 ensures effective absorption of X-ray, while BA2CsPb2I7 induces larger bulk resistance, which is expected to achieve higher photocurrent and lower dark current. Finally, the obtained X-ray detector exhibits negligible baseline drift, faster response, and smaller leakage current compared to the CsPbI3 counterparts. Specifically, the device exhibits a detection limit of $0.092 ~\mu $ Gy $_{air}$ /s, and the CsPbI3-based device was $2.63 ~\mu $ Gy $_{air}$ /s. [ABSTRACT FROM AUTHOR]

By adopting atomic layer deposition (ALD) sidewall passivation, the electroluminescence (EL) and communication performances of mini-light emitting diodes (mini-LEDs) of different sizes were improved. In particular, the most significant improvement in the electroluminescence properties of the external quantum efficiency (EQE) (a 7.2% increase), leakage current, and the communication properties of the modulation bandwidth (a 20% increase) transmission rate and bit error rate (BER) was found in the smallest mini-LEDs (80 $\mu \text{m}\,\,\times $ 120 $\mu \text{m}$). According to the results of time-resolved photoluminescence (TRPL) measurements, the carrier lifetime of the samples can be affected by both the size and ALD sidewall passivation. In addition, the effects of ALD sidewall passivation for visible-light communication (VLC) were demonstrated. [ABSTRACT FROM AUTHOR]

This article proposes a new driving scheme based on an n-type low-temperature polycrystalline silicon (LTPS) four-transistor-two-capacitor (4T2C) pixel circuit to improve the quality of motion images of active matrix organic light-emitting diode (AMOLED) displays. The proposed driving scheme can prevent the effect of the lateral leakage current flowing through the OLED common layer by keeping the pixels in the upper and lower row lines in a nonemitting hold period during the program period. The simulation results show that all RGB colors maintain a shooting amount ratio (SAR) below 1% from the first frame when the image is switched from black to white, even for a concentration of the high p-doped hole transport layer (p-HTL). In addition, the parasitic capacitances of the 4T2C pixel circuit that causes OLED current errors are thoroughly analyzed for high luminance uniformity. A 1.5-in 326 pixels per inch (PPI) AMOLED panel based on the proposed driving scheme was fabricated. The results of our measurements show that the SARs of RGB colors are 0.8%, 0.2%, and 0.9%, respectively, and the average ${x}$ -coordinate shift of the color is 0.007 during the transition between black and white images due to the effective suppression of the lateral leakage current. Therefore, we demonstrate that the proposed driving scheme is suitable for AMOLED displays that require high-quality motion images. [ABSTRACT FROM AUTHOR]

The five-level active neutral-point-clamped (5L-ANPC) inverter has been applied to increase the power capacity of photovoltaic (PV) systems. However, this type of configuration requires to balance neutral point (NP) voltage and flying capacitor (FC) voltage properly. For the operation of the transformerless five-level inverter, another requirement is to suppress the leakage current associated with the common-mode voltage (CMV) vectors. Due to the mutually coupled issues, the conventional model predictive control (MPC) methods reported so far cannot deal with them properly at the same time. To address these problems, a novel double-vector MPC (DV-MPC) strategy with zero CMV vector is proposed in this article. First, 19 voltage vectors with zero CMV are implemented as candidate vectors. Then, for the purpose to reduce output current ripples, two voltage vectors are penalized by the cost function without weighting factors to track the reference voltage. In addition, the dwell times are optimized to further mitigate current ripples. Finally, to avoid the sharply increasing computational burden of the online iteration caused by the introduction of the second vector and its corresponding redundant switching states, a voltage-balance strategy is presented for the DV-MPC method, which can determine the suitable switching combinations directly and adapt them to the selected vectors to balance the voltages of the NP and FCs together. The effectiveness of the proposed method is verified by the simulation and experiment at the end of this article. [ABSTRACT FROM AUTHOR]

Deep neural network (DNN) inference and training produce a large amount of intermediate data. To achieve high energy efficiency, sufficient on-chip buffer is preferred to reduce the energy and time consuming off-chip DRAM access. However, SRAM buffer suffers from large area cost and high standby power due to its large cell size and high leakage current. Although embedded DRAM (eDRAM) offers higher memory density, its energy consumption is high due to frequent refresh operation, which is induced by the short refresh interval (40∼100μs). In this paper, a dual-mode buffer memory based on the CMOS compatible HfZrO2 ferroelectric material is proposed for DNN accelerators. It can operate in both volatile eDRAM mode and non-volatile ferroelectric RAM (FeRAM) mode. The functionality of the proposed dual-mode memory bit-cell design is verified using SPICE simulation with the multi-domain Preisach physical model. A data-lifetime-aware memory mode configuration protocol is proposed to optimize the buffer access energy for both DNN inference and training. Detailed circuitry and architectural support for the dual-mode memory are presented. For DNN training with ferroelectric-field-effect-transistor (FeFET) and SRAM-based compute-in-memory (CIM) accelerator, the proposed dual-mode buffer design improves the overall energy efficiency by 92.2%∼98.7%, 44.1%∼47.6%, 12.6%∼13.0% compared to baseline designs using SRAM buffer with the same buffer area, eDRAM and FeRAM with the same buffer capacity, respectively. For DNN inference with tensor-processing-unit (TPU)-like systolic array, the energy efficiency during computing is improved by 40.7%∼45.6%, 18.4%∼29.6% compared to the designs with eDRAM and FeRAM buffer, respectively. By storing the persistent data using the non-volatile mode, the energy efficiency of systolic array is improved by 2.3×∼5.5× over SRAM-based design when standby is frequent. The chip area overhead of the dual-mode buffer design is 5.2%, 4.1% and 7.2% for FeFET-based-CIM, SRAM-based-CIM and systolic-array-based accelerators using eDRAM buffer, respectively. [ABSTRACT FROM AUTHOR]

The semi-Z-source inverter (SZSI) with least switch count (only two switches) eliminates the leakage current due to the doubly grounded structure. However, the main disadvantage is the high voltage stresses of the switches (the sum of double photovoltaic output voltages and the grid voltage amplitude). This article proposed an improved inverter based on the SZSI. It inherits the advantage of less leakage current and owns another merit of lower switch voltage stress. Besides, the operation principle of the proposed inverter is bimodal and only two switches operate at high frequency in each mode. First, the circuit structure and the operation principle are introduced in detail. Then, the grid current controllers in both modes are designed. Two comparisons are investigated for better clarification of the pros and cons of the proposed inverter. Finally, experimental results, obtained with a 500-W laboratory prototype, are presented to validate its performance. [ABSTRACT FROM AUTHOR]

Aiming at the key problems of the existing nonisolated photovoltaic (PV) inverter, such as the common mode (CM) leakage current, the voltage up and down ability, and the service life restricted by the electrolytic capacitor, a novel single-stage common-ground zeta-based inverter with nonelectrolytic capacitor is proposed in this article. The proposed inverter is based on zeta dc converter and has the inherent voltage conversion characteristics of zeta converter, which makes it more suitable for PV system with wide input voltage fluctuation range. In addition, common-ground structure is adopted in this inverter, which can shorten the parasitic capacitor of the PV array to the ground. Therefore, it can effectively suppress the CM leakage current, reduce the shutdown frequency of the PV system, and improve the utilization rate of solar energy. Moreover, the proposed inverter does not contain electrolytic capacitors, which avoids the problem of high maintenance cost due to the short service life and high equivalent series resistance of electrolytic capacitors. First, the topology of the proposed inverter is given, and the modulation and operating principle are analyzed. Second, the passive components are analyzed. Finally, a 1 kW prototype is built for experimental verification. The experimental results verify the correctness of the theoretical analysis and simulation. [ABSTRACT FROM AUTHOR]

In this article, we present a family of multilevel converters with the single-stage dynamic voltage-boosting feature, reduced number of circuit components, modular structure, bidirectional operation, continuous input current, and acceptable overall efficiency. The proposed structure is based on a three-level single-stage boost integrated inverter with an embedded quasi-H-bridge (QHB) cell. It is comprised of five unidirectional power switches and a floating capacitor. By differential connection of two or three QHB cells and with the aim of a single inductor/input dc source, several derived topologies for both the single and three-phase applications with different multilevel output voltage performances have been achieved. The aforementioned advantages make this converter a suitable candidate for renewable energy applications. Theoretical analysis, design consideration, comparative study, and several experimental results for a 3-kW laboratory-built system are presented to validate the effectiveness and feasibility of this proposal. [ABSTRACT FROM AUTHOR]

Converter topologies such as current-source rectifiers and inverters require switching devices with bipolar voltage blocking and unidirectional current conduction capability. Recently available dual-gate GaN monolithic bidirectional switches (MBDSs) can mimic such self-reverse-blocking (SRB) behavior if the MBDS’ two gates are controlled accordingly, but thus need twice the number of gate signals and gate drive circuits. Therefore, we propose cascode-diode control (i.e., without additional sensing or gate drive circuitry) of one MBDS gate using a cascode configuration with a low-voltage silicon Schottky diode. The resulting SRB-MBDS features quasi-ohmic conduction characteristic and single-gate control. We provide static and dynamic measurements of a discrete proof-of-concept realization (600-V, 190-m $\mathrm{\Omega }$ GaN MBDS; 40-V, 10-A silicon Schottky diode) that demonstrate the proposed SRB-MBDS’ feasibility. [ABSTRACT FROM AUTHOR]

In this work, a high performance GaN-on-Si quasi vertical PiN diode was demonstrated by the combination of a beveled sidewall and self-aligned fluorine plasma treatment. The didoes achieved a remarkable breakdown voltage ($\text{V}_{\text {BR}}{)}$ of 930 V and an ultra-low reverse leakage current. Meanwhile the didoes showed a low specific on-resistance ($\text{R}_{ \mathrm{\scriptscriptstyle ON},\textit {sp}}$) of 0.43 $\text{m}\Omega \cdot $ cm2, a high on/off current ratio ($\text{I}_{ \mathrm{\scriptscriptstyle ON}}/\text{I}_{ \mathrm{\scriptscriptstyle OFF}}$) of $10^{{11}}$ , and an excellent Baliga’s figure of merit (BFOM) of 2.01 GW/cm2. The measurement results of X-ray spectroscopy (XPS) and Kelvin Probe Force Microscopy (KPFM) proved the presence of F ions and the decrease of surface potential, which reduced the electric field peak and suppressed the leakage current. These results show a great potential of GaN on Si PiN diode for power applications. [ABSTRACT FROM AUTHOR]

We report Al0.1Ga0.9N p-i-n ultraviolet (UV) avalanche photodiodes (APDs) based on sapphire substrates with a record-high gain over $2 \times 10^{6}$. The devices fabricated with various mesa diameters present consistent avalanche behaviors and identical dark current distributions over multiple ${I}-{V}$ scans, which are comparable to the GaN APDs grown on free-standing GaN substrates. The quadratic fitting of the dark currents versus the mesa sizes reveals that the leakage current at the breakdown voltage is a mixture of surface leakage and bulk leakage, and the surface component is comparable to that of the bulk. Additionally, KOH surface treatment and SiO2 passivation are proven to be very effective in suppressing the leakage current and achieving robust avalanche performance. [ABSTRACT FROM AUTHOR]

In this letter, a 1.2kV optically-controlled SiC transistor (OCT) is proposed and fabricated. A pin diode is monolithically integrated with the SiC OCT for reverse conducting and online junction temperature measurement capability. Field limiting rings are designed as terminal structure for forward blocking capability. The test results indicated that, besides full optical control and high blocking voltage performances, the fabricated transistor chip was also capable of reverse conducting and online junction temperature measurement. The forward breakdown voltage of the transistor was about 1400V and the leakage current at 1200V was ${2.5}\,\,\times \,\,{10}\,\,^{-{8}}\text{A}$. The reverse turn-on voltage was about 2.6V, while the temperature sensitivity of the integrated diode was 2.99mV/K at 5mA. Under 365nm ultraviolet (UV) light with 300mW/cm2 incident intensity, the forward current of the OCT chip was $203.2\mu \text{A}$ at 0.3V, which is about ${1.2}\,\,\times \,\,{10}\,\,^{{5}}$ times the corresponding dark current. The transient characteristic was tested at a 600V bias voltage in a resistive load circuit and the results indicate that the OCT can be switched using a 365nm UV light emitting diode. [ABSTRACT FROM AUTHOR]

In this letter, a high-performance dual-function device fabricated using one single SiO2 resistive switching layer is demonstrated. The SiO2 layer is sandwiched between Ag and n+-Si to form an Ag/SiO2/n+-Si dual-function device with memory and selector features. As a memory device, it shows a high memory window of 107, and can continually operate over 104 cycles. Nonvolatility and stability are examined using a retention and a stress test for 104 s. Measurement at 85°C is performed to further confirm the reliability of the memory feature. As a selector, the device shows an extremely low leakage current of 0.1 pA, a high selectivity of 106, and a low turn-on energy consumption of 0.93 pJ. Moreover, it has steep turn-on and turn-off switching slopes of 1.7 mV/decade and 0.7 mV/decade. The reliability of the selector feature is confirmed by pulse operations and a stress test. [ABSTRACT FROM AUTHOR]

Leakage currents through dielectrics in modern logic, memory, and power devices, and back-end interlevel layers can severely increase the time-zero power dissipation and shorten the lifetime of the material structure. Depending on thickness, material properties, and fabrication quality, different conduction mechanisms through the insulating layer, such as band-to-band and trap-assisted tunneling (TAT) are observed. These leakage currents can be distinguished by their dependence on electric field strength, temperature, and their transient characteristics. The identification of the underlying mechanisms is of utmost importance for the selection of suitable dielectrics and optimization of device processing. In this work, we present a nonradiative multiphonon model which extends our compact physics (Comphy) reliability framework to also account for TAT. The model is based on a single physical defect parameter set from which charge transfer kinetics between charge carrier reservoirs and oxide defects (single-TAT) as well as between the defects (multi-TAT) can be derived. We thereby demonstrate that the thermal barrier for inelastic defect–defect carrier tunneling is approximately twice as large in comparison to reservoir-defect interaction and further show in which parameter regime multi-TAT plays a role. Our results show that multi-TAT currents are a less important contribution to the overall tunnel current than previously assumed. [ABSTRACT FROM AUTHOR]

Many emerging GaN electronic and optoelectronic devices comprise p-GaN layers buried below n-GaN or AlGaN. The activation of these buried p-GaN layers usually relies on the lateral hydrogen diffusion through the etched mesa sidewalls, which is known to induce nonuniform acceptor distributions. However, the acceptor profile, electric field (${E}$ -field) blocking capability, and leakage current mechanisms of the sidewall activated p-GaN layer have not been fully understood. This work addresses these knowledge gaps by fabricating vertical GaN p-n diodes with a thick ($3.8~\mu \text{m}$) p-GaN. Two activation schemes were performed to allow the hydrogen diffusion through sidewalls and the top surface. For the sidewall activation, an analytical model was developed to depict the spatial distribution of the activated acceptor and the temporal evolution of this distribution with the increased annealing time. This model was validated using the ${C}$ – ${V}$ characteristics of the fabricated diodes with various radii. Under reverse biases, the breakdown ${E}$ -field and leakage current of the sidewall-activated diodes were found to be determined only by the edge area with the highest activation efficiency. The leakage mechanism agrees with the trap-assisted tunneling (TAT) model, and the peak junction ${E}$ -field can exceed 3 MV/cm, both being similar to those of surface-activated diodes. These results provide critical information for the design and processing of advanced GaN devices with the buried p-GaN. [ABSTRACT FROM AUTHOR]

In this article, the effect of microwave leakage into the diode region on the suppression of backward current in a relativistic backward wave oscillator (RBWO) operating at low magnetic field is investigated by the theoretical analysis, particle-in-cell (PIC) simulation, and experiments. The theoretical results show that some backward electrons are absorbed by the cathode holder due to microwave leakage, and as the microwave power increases, the microwave frequency increases, and the guiding magnetic field decreases, it will promote the absorption of electrons. The PIC simulations based on the first principle reveal that the leakage microwave partially suppresses the backward current and the suppression is enhanced when the incidence TM02 is dominant. In the ${X}$ -band dual-mode RBWO packaged with permanent magnet experiments, a microwave pulse with the power of 3.9 GW, the frequency of 9.93 GHz, and the efficiency of 33% was measured when the diode voltage was 820 kV and diode current was 14.5 kA. [ABSTRACT FROM AUTHOR]

The impact of dislocation density on off-state leakage current in avalanche-capable gallium nitride (GaN)-on-GaN vertical p-n diodes is experimentally demonstrated and studied. At first, the presence of avalanche breakdown was confirmed on p-n diodes grown on bulk GaN substrates with dislocation density ranging from 1e4 to 1e6 cm−2. The impact of dislocation density on off-state leakage current was then compared and analyzed on devices with confirmed stable avalanche behavior. The devices in the 1e6-cm−2 region show higher leakage current and a more variable-range-hopping-dominated leakage process, while the Poole–Frenkel effect starts showing more influence on the devices in the 1e4-cm−2 region, especially under medium and high average electric field beyond 1.0 MV $\cdot $ cm−1. [ABSTRACT FROM AUTHOR]

Narrow-channel accumulated body nMOSFET devices with p-type side gates surrounding the active area have been electrically characterized between 100 and 400 K with varied side-gate biasing (${V}_{\text {side}}$). The subthreshold slope (SS) and drain induced barrier lowering (DIBL) decrease and threshold voltage (${V}_{t}$) increases linearly with reduced temperature and reduced side-gate bias. Detailed analysis on a 27 nm $\times $ 78 nm (width $\times $ length) device shows SS decreasing from 115 mV/dec at 400 K to 90 mV/dec at 300 K and down to 36 mV/dec at 100 K, DIBL decreasing by approximately 10 mV/V for each 100 K reduction in operating temperature, and ${V}_{t}$ increasing from 0.42 to 0.61 V as the temperature is reduced from 400 to 100 K. ${V}_{t}$ can be adjusted from ~0.3 to ~1.1 V with ~0.3 V/V sensitivity by depletion or accumulation of the body of the device using ${V}_{\text {side}}$. This high level of tunability allows electronic control of ${V}_{t}$ and drive current for variable temperature operation in a wide temperature range with extremely low leakage currents (<10−13 A). [ABSTRACT FROM AUTHOR]

A small subthreshold swing (SS) hydrogen-terminated diamond field-effect transistor is realized by using a wide bandgap material (SnO2). Results showed an SS of 106.4 mV/dec, which should be ascribed to the low interface state density (1.05 $\times10$ 12 cm $^{-2}\cdot $ eV−1) between SnO2 and diamond. The fixed charge density and trapped charge density are $1.1\times10$ 12 cm−2 and $8.6\times10$ 11 cm−2, respectively. Leakage current between source and gate is less than $2.1\times10$ −8 A at gate voltages from −5.0 to 1.0 V and the breakdown voltage is measured to be −180 V. In addition, the devices exhibit normally- OFF characteristics, whose threshold voltage and maximum drain current density are −0.12 V and −21.6 mA/mm with 4- $\mu \text{m}$ gate at ${V}_{GS} = -3$ V. The ON/OFF ratio is around 107 and the maximum effective mobility is extracted to be 165 cm2/(Vs). This work indicates that SnO2 dielectric could form low interface state density with hydrogen-terminated diamond surface and it also provides a simple method to realize normally- OFF devices. [ABSTRACT FROM AUTHOR]

This work presents a comparative study of the subthreshold swing (SS) in InAlN/GaN-based high electron mobility transistor (HEMT), with and without carbon doping in the buffer layer. It is observed that devices with carbon-doped (C-doped) buffer exhibit near-ideal SS of close to 60-mV/decade over a wide range of drain voltage for both up and downsweep. The C-doped buffer layer reduces the OFF-state drain leakage current and increases the drain current ON/OFF ratio. TCAD simulation of the vertical electric field under the gate shows that the sample with a C-doped buffer layer has a much lower value of the peak electric field at the drain side edge of the gate, resulting in lower reverse-biased gate leakage current and smaller SS compared to that of the undoped buffer. Moreover, the junction capacitance at the interface of the unintentionally doped GaN (UID:GAN) and the C-doped buffer layer, in series with the depletion capacitance, reduces the overall capacitance, which further improves the SS in the C-doped wafer. [ABSTRACT FROM AUTHOR]

The Smart Discrete concept which monolithically integrates a vertical high-voltage power device with low-voltage smart circuits has been widely adopted in silicon world for many years and may bring similar benefits to SiC world. For example, it is highly desirable to integrate a gate driver circuit onto a high-voltage SiC thyristor for ultra-fast turn-on. However, the electrical isolation between the vertical high-voltage power device and the low-voltage circuit elements remains a major technical challenge for silicon, and even more so for SiC due to the very limited processing options. In this article, we propose a combination of shallow junction isolation (JI) and partial dielectric isolation (DI) for high-voltage 4H-SiC smart thyristor, which is monolithically integrated with low-voltage nMESFET circuits. The characterization of fabricated devices and analysis of leakage currents across the isolation structure have been done to experimentally verify the feasibility of the isolation method. 8 V parasitic lateral NPNP thyristor between a 6.3 kV 4H-SiC thyristor and isolation moats, 175 V lateral PNP transistor between the passive resistor and isolation moats, and 10 V lateral reverse-biased p-n diode between nMESFET and isolation moats are experimentally demonstrated. [ABSTRACT FROM AUTHOR]

The X-ray free-electron laser (XFEL) at the Pohang Accelerator Laboratory (PAL), Pohang, South Korea, provides X-ray energies of up to 15 keV depending on the experimental purpose. Silicon-based devices have been used as diagnostic devices and detectors for X-rays in experimental stations. Considering recent domestic and international circumstances, developing silicon-based detectors in-house is necessary. We developed a silicon p-intrinsic-n (PIN) photodiode (PD) for X-ray detection, and its performance was investigated and compared with that of a commercial PD used in the PAL-XFEL. The PD was designed to be 1 cm $\times1$ cm in size, and it used the junction side for signal readout and the ohmic side for X-ray entrance. Considering the absorption length of 12-keV X-rays suitable for crystallography, a 500- $ {\mu }\text{m}$ -thick silicon wafer with a high resistivity was used for PD fabrication. It has a guard ring, an n+ edge field shaper, and an antireflection coating (ARC) and is available in four different types based on the metal structure of the junction and ohmic sides. We present here the electrical characteristics of the PDs. The depletion voltage at which the bulk of the PD is fully depleted was determined to be 119.7 ± 8.2 V from bulk capacitance measurements, and the operation voltage of the PD was set to 200 V. PDs with leakage currents less than 30 nA/cm2 at the operation voltage were chosen for performance measurements. The signal-to-noise ratio (SNR) with a Sr-90 radioactive source corresponding to the minimum ionizing particle (MIP) and the quantum efficiency (QE) for wavelengths of 300–1000 nm were measured. Beam tests were conducted at the PAL-XFEL using 600-, 900-, and 1200-eV X-rays where the responses to ultrahigh brightness and ultrashort X-ray pulses were checked. The energy resolutions were measured using gamma-ray radioactive sources, Am-241 (59.5 keV), and Ba-133 (31.0 and 81.0 keV). The differences in performance among the PD types are presented herein in terms of the electrical characteristics, SNR, QE, response to X-ray pulses, and energy resolutions. The results of the fabricated PDs were also compared with those of a commercial PD. [ABSTRACT FROM AUTHOR]

We report the fabrication of vertical metal–oxide–semiconductor (MOS) detectors with the highest energy resolution ever reported. The MOS detectors have been fabricated on 50- $\mu \text{m}$ -thick n-type 4H-SiC epitaxial layers by growing a silicon dioxide (SiO2) layer thermally prior to contact deposition. The MOS detectors exhibited leakage currents two orders of magnitude lower than that observed in a Schottky barrier detector (SBD) fabricated on similar 4H-SiC epilayers. The MOS detectors exhibited a much higher energy resolution of 0.4% compared to 0.8% observed in an SBD for 5486-keV alpha particles although both the devices showed a high charge collection efficiency (CCE) of 96% when exposed to the alpha particles. Capacitance mode deep-level transient spectroscopy (C-DLTS) revealed the presence of “lifetime killer” $\text{Z}_{\mathrm {1/2}}$ defects in similar concentrations in both the devices, and however, the corresponding capture cross section in the SBD has been observed to be one order of magnitude higher compared to the MOS detector, and instead of EH6/7 center seen in the SBD, the MOS device showed the presence of EH5 center. The higher resolution of the MOS device is attributed to the lower leakage current and difference in defect configurations observed between the two devices. The MOS detector showed a positive polarity C-DLTS peak with an activation energy of 1.22 eV, which is likely due to the nonnegligible impedance of the back contact because of the SiO2 layer. The present study opens the great potential of other wide bandgap semiconductor-based vertical MOS detectors, which can be fully depleted for high-resolution X-/ $\gamma $ -ray detection. [ABSTRACT FROM AUTHOR]

The insulation impedance monitoring methods such as capacitance/dissipation factor monitoring methods have been proposed for the online stator insulation condition monitoring. By measuring the insulation leakage currents and the phase-to-ground voltages, the groundwall and phase-to-phase insulation impedances can be calculated in frequency domain. In the existing methods, the calculation is based on the assumption that the differential mode phase-to-ground voltage decreases linearly along the stator winding and no phase angle deviation is considered. However, the phase angles of the induced electromagnetic forces in stator winding in different slots depend on the slot positions. The assumption in the existing methods neglects this phase deviation and causes errors in the monitoring results. In order to eliminate this effect, the effect of the phase angle deviation on monitoring results is analyzed in this article. Its dependency on the turn number, the winding configuration and the frequency of the selected monitoring signals is studied. A compensation method is proposed and the compensation coefficients are calculated for different winding cases for the demonstration purpose. The online experimental results prove that the accuracy of the online monitoring results is improved after the compensation. [ABSTRACT FROM AUTHOR]

A cascaded modular model predictive control (MMPC) method is designed for a modified nonisolated $LCL$ grid-connected inverters to provide resonance damping, improved dynamic performance, and leakage current attenuation capabilities. The continuous control set model predictive control strategy is applied for the proposed method. The active damping function of the inner loop MMPC is analyzed in detail to illustrate the mechanism of improving the system dynamic performance. The cascaded MMPC method is compared with the conventional proportional-integral (PI) control methods with/without a notch filter to show the merits in resonance damping and dynamic response. The optimal control parameters design procedure is elucidated with the tuning mechanism of the MMPC weighing factor and PI gain. With the proposed optimal MMPC design method, the dynamic performance of rising time and overshoot are improved compared to the conventional PI control methods with/without the notch filter. The simulation and experimental results verified the proposed control design method. [ABSTRACT FROM AUTHOR]

With the wide application of inverter-fed motors (IFMs), it is necessary to monitor the groundwall (GW) insulation status to guarantee the reliable operation of motor drive system. This article first proposes a mathematical model of leakage current in IFM to analyze its time domain characteristics, and then an online GW insulation monitoring method is proposed based on the transient characteristics of leakage current. By using the initial oscillation amplitude, oscillation period, and attenuation time of leakage current, the phase, position, and severity of GW insulation degradation can be identified. The proposed method is validated using an IFM, and the experimental results agree well with theoretical analysis. [ABSTRACT FROM AUTHOR]