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We demonstrate a novel way of integrating STT-MRAM for on-chip hybrid memory which exhibits either features of high-retention or high-speed implemented in separate zones in a single chip. For satisfying high-temperature retention requirement, tailored MTJs are shown to support > 10 year retention at 220°C. For high-speed operation, critical improvements have been made in terms of TMR, short fail probability, overdrive and write error rate. The new integration provides a manufacturable way of combining diverse memory components by modulating non-volatility of STT-MRAM without affecting within-chip distributions of critical properties.

7nm CMOS FinFET technology featuring EUV lithography, 4th gen. dual Fin and 2nd gen. multi-eWF gate stack is presented, providing 20% faster speed or consuming 35% less total power over 10nm technology [1]. EUV lithography, fully applied to MOL contacts and minimum-pitched metal/via interconnects, can reduce >25% mask steps with higher fidelity and smaller CD variation. A VT of 6T HD SRAM cell are 1.29 for PD (PG) and 1.34 for PU, respectively.

Exposure to polluted ambient air is inevitable in vehicular application of proton exchange membrane fuel cell (PEMFC). SO 2 and NO 2 are common pollutants which in individual are known to alter PEMFC performance for their presence in the oxidant, as indicated by preceding researchers. However, interacting effects of SO 2 and NO 2 in the oxidant on PEMFC have not been extensively studied. Concerning the vehicular application of PEMFC, durability issue related with SO 2 and NO 2 — poisoned PEMFC are also necessary to be studied in order to maintain the vehicle's performance. Hence this research encompasses the poisoning effects of SO 2 and NO 2 on PEMFC performance. Polluted air resulted a significant decrease in performance of PEMFC.

Scalability of interface driven perpendicular magnetic anisotropy (i-PMA) magnetic tunnel junctions (MTJs) has been improved down to 1X node which verifies STT-MRAM for future standalone memory. With developing a novel damage-less MTJ patterning process, robust magnetic and electrical performances of i-PMA MTJ cell down to 15 nm node could be achieved.

This paper presents, for the first time, the Active Width Modulation (AWM) technology which compensates a string resistance with the active widths of local Y selectors for the purpose of increasing the number of cells-per-string (CPS). The AWM is demonstrated using 58 nm 512 Mb PRAM with 32 CPS instead of 8 CPS [1], which can reduce the chip size by 4.3%. Also, the systematic variability of a program current, ΔI PGM , is reduced from 17.8% to 0.82%, and that of a write energy, ΔE PGM , from 47.9% to 2.0%. Both write endurance and disturbance of >1M cycles are achieved for 512 Mb PRAM. The AWM can be further applied to increase CPS to 64 or 128, together with the reduction of a reset current, I RESET , for sub-40 nm PRAM technology and so on.

Endurance failures are classified into three groups, all of which originate from the atomic transport of GST due to electromigration in molten phase. Based on the analysis, cell structure insusceptible to the atomic transport and for better cycling performance was proposed.

A PRAM cell with great scalability and high speed operation capability with excellent reliability below 20nm technology was demonstrated. This has the meaning of the potential applicable to the technology area of scaling limitation of DRAM cell. We fabricated a confined PRAM cell with 7.5nm×17nm of below 4F2. In particular, Sb-rich Ge-Sb-Te phase change material was employed for high speed operation below 30nsec. The excellent writing endurance performance was predicted to maintain up to 6.5E15cycles by reset program energy acceleration. Its data retention was 4.5 years at 85°C which is enough for DRAM application.

In this paper, an adaptive 3rd-order Volterra filtering is proposed for nonlinear active noise control (ANC) of systems with a cubically nonlinear primary acoustic path and a noisy secondary path, whereby a Gauss-Seidel fast affine projection (GS-FAP) algorithm is employed as an adaptive scheme. The simulation results demonstrate that the proposed nonlinear ANC approach yields stable ANC performance and faster convergence, compared with those of conventional ANC approaches in case of a noisy secondary path.

A computationally efficient and programmable dc-notch FIR filter design using a modified alpha - scaled sampling kernel and an analytic procedure is proposed. Design examples demonstrate that the proposed approach provides an efficient solution for designing a sharp dc-notch FIR filter, and satisfies the required filter specification.

The root cause and an approach to lifetime expectation of bi-modal distribution in Cu/low-k interconnect have been elucidated through experimental and simulation results. The early mode with short failure time and voids at via bottom interface, could be explained by pre-existing voids and large current density resulting from gouging via bottom profile. A high compressive SiCN making Cu/SiCN interface near via into tensile stress causes void nucleation in its specified sites, which indicate the late mode. And component lifetime can be predicted using the data obtained only from early failure, because of the same in activation energy and acceleration factor. This comprehension for bi-modal behavior is helpful in EM reliability of technology node beyond 45 nm.

For the first time, a transistor performance improvement is achieved by increasing the tensile stress of O3-TEOS pre-metal dielectric (PMD) using a novel plasma treatment and integration scheme. Plasma-treated O3-TEOS films show more tensile stress value about twice than that of an as-deposited O3 -TEOS film. The novel process shows up to 10% improvement of Ion for nMOS without any cost of pMOS degradation

A manufacturable Cu/low-k multilevel interconnects have been integrated using HSQ-via-fill dual damascene process for 65nm node as stated in K.-W. Lee et al. (2003). By introducing non-porous type SiOC film (k=2.7) without trench etch stopper and capping oxide, we obtained the effective k (keff) less than 3.0 for 65nm design rule. Simple and reliable process was achieved by improved unit process technologies such as damage-free capping oxide, abrasive free low-k direct polishing, advanced ionized PVD (AiPVD) barrier metal and bi-layer dielectric barriers, etc. according to K.C. Park et al. (2003).

Micro villus patterning (MVP) technology which delivers the maximized cell capacitance is discussed. The key feature of the MVP technology is the formation of a hemispherical grain (HSG) archipelago and its transference to the underlayered oxide. The HSG archipelago pattern is produced on the oxide layer, and, by using that pattern as an etch mask, the oxide archipelago pattern is again transferred to the storage poly for the formation of villus bars by anisotropic dry etch. After the etching process, the oxide etch mask pattern is stripped away by using oxide wet etchant, so that additional Fin undercut structure is achieved underneath the main body. The main body of the storage electrode can be formed by single deposition and etch process, so that the storage electrode structure is strong enough to maintain its physical stability in spite of the complication of its shape. A 256-Mb DRAM-cell size of 0.6 approximately 0.8 mu m/sup 2/ having more than 30 fF of cell capacitance with a stack structure, has been realized. >

A method for the design of reduced-order controllers is developed based on the projective controls approach. The projective controls, previously derived to preserve the dynamic modes of a state-feedback reference system, are extended to allow the preservation of the modes of an output-feedback reference system. This extension is useful if the best available reference control for the system is an output-feedback control. In addition, it allows more design freedom than the projective controls with state-feedback reference. >

A method is developed for computing optimal observers for linear decentralized feedback control systems. Necessary conditions are derived for the decentralized output-feedback control to optimally approximate a given state-feedback control. The observer gains that satisfy the necessary conditions are found using a numerical gradient-type optimization. A control structure where decentralized observers share control-input information is also considered. For this structure, the optimal observers can be computed directly from a set of decoupled algebraic Riccati equations. Centralized control is treated as a special case, resulting in a simple and novel derivation of the known results for computing optimal centralized observers.