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Gallium nitride (GaN) high electron-mobility transistors (HEMTs) offer considerable high-power operation but suffer in reliability due to potentially damaging self-heating. In this study, self-heating in AlGaN/GaN HEMTs on high conductivity substrates is assessed using a high-resolution thermoreflectance (TR) imaging technique, to compare the thermal response between GaN-on-Si, GaN-on-Diamond, and GaN-on-4H-SiC. The TR method accuracy at high-power density is verified using a nonlinear coefficient of TR (CTR) as a function of temperature. The acquired steady-state thermal maps give a thermal resistance of 11.5~mm ⋅ K/W for GaN-on-Si (based on peak channel temperature), compared to 2.7 and 3.3~mm ⋅ K/W for GaN-on-SiC and GaN-on-diamond substrates, respectively. The tested GaN-on-diamond HEMT exhibits similar heating rates to those seen on a SiC substrate, with a slightly higher peak temperature, which indicates a higher thermal boundary resistance that could offset the benefits of using a higher conductivity substrate and lead to faster thermally enhanced degradation. The analysis reveals the importance using high-resolution imaging to detect hotspots and areas of peak temperature that largely affect failure initiation and device reliability and which may not be otherwise observable. [ABSTRACT FROM AUTHOR]

The back-end components of integrated circuits (ICs) are susceptible to self-heating deteriorating effects due to the microscale interconnects carrying large current densities, and thus require innovative passive cooling strategies. This article investigates the cooling effect of the high conductivity metallization (MET) fill that is used in conjunction with the chemical mechanical planarization (CMP) process. Thermal simulation models are developed for a three-level back end of line (BEOL) stack and then validated experimentally using high-resolution thermal imaging. A coupled approach is used to optimize the numerical model and fully characterize the BEOL embedded passive cooling solution. Results indicate that stricter thermal constraints are present for devices higher in the BEOL stack and exhibit the highest cooling potential from the use of CMP fill in the underlying MET layers. As a thermal improvement strategy for such thermally critical interconnects, a CMP fill-based cooling solution is presented by modifying the fill pattern in order to maximize heat dissipation within the BEOL. The resulting heat spreader (HS) design achieved up to 30% reduction in temperature for 10- $\mu \text{m}$ -wide interconnects and can reach 43% for narrower interconnects. The gained cooling makes it possible to extend the activation limits of interconnects by 15% and 25%, respectively. The experimentally validated HS simulation model is used to conduct parametric analysis for a range of interconnect dimensions with an eye on standardizing the HS design within the BEOL stage of ICs. [ABSTRACT FROM AUTHOR]

This article presents an electric-based methodology for thermal characterization of semiconductor technologies. It is shown that for technologies such as gallium nitride (GaN) high electron mobility transistors, which exhibit several field induced electron trapping effects, the thermal characterization has to be performed under specific conditions. The electric field is limited to low levels to avoid activation of trap states. At the same time, the dissipated power needs to be high enough to change the operating temperature of the device. The method is demonstrated on a test structure implemented as a GaN resistor with large contact separation. It is used to evaluate the thermal properties of samples with different silicon carbide suppliers and buffer thickness. [ABSTRACT FROM AUTHOR]

Record DC power has been demonstrated in AlGaN/GaN high electron mobility transistors fabricated using a substrate replacement process in which a thick diamond substrate is grown by chemical vapor deposition following removal of the original Si substrate. Crucial to the process is a ~30 nm thick SiN interlayer that has been optimized for thermal resistance. The reductions obtained in self-heating have been quantified by transient thermoreflectance imaging and interpreted using 3D numerical simulation. With a DC power dissipation level of 56 W/mm, the measured average and maximum temperatures in the gate-drain access region were 176 °C and 205 °C, respectively. [ABSTRACT FROM AUTHOR]

Thermal challenges in next-generation electronic systems, as identified through panel presentations and ensuing discussions at the workshop, Thermal Challenges in Next Generation Electronic Systems, held in Santa Fe, NM, January 7-10, 2007, are summarized in this paper. Diverse topics are covered, including electrothermal and multiphysics codesign of electronics, new and nanostructured materials, high heat flux thermal management, site-specific thermal management, thermal design of next-generation data centers, thermal challenges for military, automotive, and harsh environment electronic systems, progress and challenges in software tools, and advances in measurement and characterization. Barriers to further progress in each area that require the attention of the research community are identified. [ABSTRACT FROM AUTHOR]

This work presents the creation of a coupled analysis engine and experimental system capable of fully characterizing the thermal behavior of complex, 3-D, active, submicron, electronic devices. First, the surface temperature field of an activated device is non-invasively measured with submicron spatial resolution. Next, the thermal conductivity of each thin-film layer composing the device is measured and a numerical model is built using these values. The measured temperature distribution map is then used as input for an ultra-fast inverse computational solution to fully characterize the thermal behavior of the complex 3-D device. By bringing together measurement and computation, it becomes possible for the first time to non-invasively extract the 3-D thermal behavior of nanoscale embedded features that cannot otherwise be accessed. The power of the method was demonstrated by verifying that it can extract details of interest of a representative MOSFET device. [ABSTRACT FROM AUTHOR]

This work presents a demonstration of the applicability and efficacy of an experimental system capable of noninvasively and nondestructively scanning the transient surface temperature of pulsed microelectronic devices with submicron spatial and sub-microsecond temporal resolutions. The article describes the features of the experimental setup, provides details of the calibration process used to map the changes in the measured surface reflectivity to absolute temperature values, and explains the data acquisition procedure used to measure the transient temperature over a given active region. This thermoreflectance thermometry system is shown to be particularly suited for directly measuring the surface temperature field of devices undergoing the fast transients that are typical of next generation microelectronic devices. To illustrate the experimental approach, both quasisteady and transient temperature measurement results are presented for standard MOSFET devices. [ABSTRACT FROM AUTHOR]

The article presents an approach for optimizing the transient thermo-reflectance measurement of thermal properties. As electronic devices become smaller, their thermal design becomes more critical, making the knowledge of thermal properties essential to the overall design process. Additionally, new device structures and materials with superior properties are being developed, but many of these may have unknown thermo-physical properties. Moreover, recent studies have revealed that the thermal properties of thin-film materials used in electronics are dependent on the deposition process.

Focuses on a study which utilized a transient thermo-reflectance system to measure the thermal characteristics of thin-film silicon dioxide layers. Intrinsic thermal conductivity of silicon dioxide; Measurement of the intrinsic value; Thermal interface resistance of thermally grown and ion beam sputtered silicon dioxide.

Presents information on a study that investigated the adaptive modeling of a transient, multiple-grid solution system of submicron integrated circuits. Methodology and validation; Simulation of a complex three-dimensional problem; Conclusions.

A foreword to "IEEE Transactions on Components and Packaging Technologies" is presented.