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Making photonic sintering of metal nanoparticles, a viable nanomanufacturing process for printed electronics requires an understanding of all of the parameters that lead to variability in the photonic sintering process. This article examines the effects of variability in the exact location of nanoparticles within a packing on the thermo-optical properties of the assemblies. Multiple discrete-element method (DEM) simulations for various nanoparticle packing configurations are created, and the absorption, scattering, and extinction cross sections for each of these configurations are calculated. The results of these simulations are then validated using experimental measurements on actual nanoparticle packings and analyzed to determine how uncertainty in the initial nanoparticle packing configuration translates into variances in its calculated thermo-optical properties. Overall, it was found that simulations matched very well with the absorptivity measurements between 400 and 800 nm wavelength light illumination that uncertainty in the initial nanoparticle configuration resulted in about a 15%–25% variance in the thermo-optical properties of the nanoparticle packings for the analyzed cases. [ABSTRACT FROM AUTHOR]

Passive phase-change thermal spreaders, such as vapor chambers have been widely employed to spread the heat from small-scale high-flux heat sources to larger areas. In this paper, a numerical model for ultrathin vapor chambers has been developed, which is suitable for reliable prediction of the operation at high heat fluxes and small scales. The effects of boiling in the wick structure on the thermal performance are modeled, and the model predictions are compared with experiments on custom-fabricated vapor chamber devices. The working fluid for the vapor chamber is water and a condenser side temperature range of 293 K-333 K is considered. The model predictions agree reasonably well with experimental measurements and reveal the input parameters to which thermal resistance and vapor chamber capillary limit are most sensitive. The vapor space in the ultrathin devices offers significant thermal and flow resistances when the vapor core thickness is in the range of 0.2 mm–0.4 mm. The performance of a 1-mm-thick vapor chamber is optimized by studying the variation of thermal resistance and total flow pressure drop as functions of the wick and vapor core thicknesses. The wick thickness is varied from 0.05 to 0.25 mm. Based on the minimization of a performance cost function comprising the device thermal resistance and flow pressure drop, it is concluded that the thinnest wick structures (0.05 mm) are optimal for applications with heat fluxes below 50 W/cm^2, while a moderate wick thickness of 0.1 mm performs best at higher heat flux inputs (>50∼W/cm^2). [ABSTRACT FROM AUTHOR]

The performance of passive phase-change cooling devices, such as vapor chambers or heat pipes, may be significantly enhanced by exploiting the superior thermal properties of carbon nanotube (CNT) arrays. The potential for large reductions in overall package resistance with the use of high-conductivity wick materials enhanced with CNT nanostructures is investigated. While such nanostructured wicks feature very small pore sizes that support high capillary pressures, it is shown that the high fluid flow resistance through these dense arrays prevents their use as the lone fluid transport mechanism. It is proposed that evaporator surfaces comprised of nanostructured wicks fed by interspersed conventional wick materials (such as sintered powders) can provide the required permeability for fluid flow while simultaneously decreasing the effective evaporator thermal resistance. Optimization of wicks with integrated sintered and nanostructured areas requires a study of the trade-offs between the greater permeability of the sintered materials and the greater capillary pressure and thin-film evaporation area offered by the nanostructures. A numerical model is developed to estimate the thermal resistance of the evaporator region compared to that of a homogeneous sintered powder wick. The inputs needed for this model include the permeability and the capillary pressure in the two regions. A parametric study is conducted as a function of the ratio of conduction and evaporative resistances for the nanostructured and sintered regions. For a given heat input, the optimal liquid-feeding geometry that minimizes thermal resistance is obtained. In the best cases, the thermal resistance is reduced by a factor of thirteen through the use of the integrated nanostructured wicks compared to the resistance of a homogeneous sintered powder wick. [ABSTRACT FROM PUBLISHER]

Thermal challenges in next-generation electronic systems, as identified through panel presentations and ensuing discussions at the workshop, Thermal Challenges in Next Generation Electronic Systems, held in Santa Fe, NM, January 7-10, 2007, are summarized in this paper. Diverse topics are covered, including electrothermal and multiphysics codesign of electronics, new and nanostructured materials, high heat flux thermal management, site-specific thermal management, thermal design of next-generation data centers, thermal challenges for military, automotive, and harsh environment electronic systems, progress and challenges in software tools, and advances in measurement and characterization. Barriers to further progress in each area that require the attention of the research community are identified. [ABSTRACT FROM AUTHOR]

Abstract-In this paper, we propose a methodology to solve leakage power self-consistently with temperature to predict thermal runaway. We target 28-nm-technology-node FinFET-based circuits as they are more prone to thermal runaway because of self-heating and less efficient heat dissipation compared to bulk metal-oxide-semiconductor field-effect transistors. We have generated thermal models for logic cells—inverter, NAND, and NOR—to self-consistently determine the temperature map of a circuit block. Our cell-level thermal models account for lateral heat flow (contribution of neighboring cells) along with vertical heat dissipation to the heat sink. We predict positive feedback between subthreshold leakage and temperature for all the cells in a given floor plan. Our proposed condition for thermal runaway shows the design tradeoff between the primary input (PI) activity of a circuit block, subthreshold leakage at the room temperature, and thermal resistance of the package. We show that, in FinFET circuits, thermal runaway can occur at the International Technology Roadmap for Semiconductors-specified subthreshold leakage (of 150 nA/μm for high performance) for a nominal PI activity of 0.5 and typical package thermal resistance. In addition, we show that the maximum temperature rise in an integrated circuit is limited by package limitations. [ABSTRACT FROM AUTHOR]

Flexible, large area electronics--macroelectronics--using amorphous silicon, low-temperature polysilicon, or various organic and inorganic nanocrystalline semiconductor materials is beginning to show great promise. While much of the activity in macroelectronics has been display-centric, a number of applications where macroelectronics is needed to enable solutions that are otherwise not feasible are beginning to attract technical and/or commercial interest. In this paper, we discuss the application drivers and the technology needs and device performance requirements to enable high performance applications to include RF systems. [ABSTRACT FROM AUTHOR]

In this paper, we numerically analyze the possibility of using buoyant flow in the display panel of a laptop for electronics cooling. Three-dimensional (3-D) channels with embedded pin fin arrays are analyzed using an unstructured finite volume method. Studies have been performed with a uniform heat flux boundary condition applied on the inner wall as well as for a constant inner wall temperature condition; the outer wall in all cases is exposed to the ambient. A single periodic module is selected in the lateral direction. In the axial mean flow direction, however, the entire height of the display channel is considered. Buoyancy has been modeled using Boussinesq approximation. A range of Rayleigh numbers, panel inclinations, and pin fin arrangements are considered. Local and global flow and heat transfer results are obtained including Nusselt numbers as well as local temperature and velocity fields. The results are useful in designing augmented cooling schemes in portable electronics. [ABSTRACT FROM AUTHOR]

Presents study that developed a methodology called coefficient-based resistance agglomeration (COBRA) for automatically creating hierarchical compact models of increasing complexity. Basic methodology for deriving network conductances through least-squares optimization; Description of the key point discretization and COBRA procedures; Idealizations made in creating the detailed computational fluid dynamics model from which the compact models are made.