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Hierarchical Compact Models for Simulation of Electronic Chip Packages.

Authors :
Boyalakuntla, Dhanunjay S.
Murthy, Jayathi Y.
Source :
IEEE Transactions on Components & Packaging Technologies. Jun2002, Vol. 25 Issue 2, p192. 12p. 9 Diagrams, 12 Charts.
Publication Year :
2002

Abstract

Presents study that developed a methodology called coefficient-based resistance agglomeration (COBRA) for automatically creating hierarchical compact models of increasing complexity. Basic methodology for deriving network conductances through least-squares optimization; Description of the key point discretization and COBRA procedures; Idealizations made in creating the detailed computational fluid dynamics model from which the compact models are made.

Details

Language :
English
ISSN :
15213331
Volume :
25
Issue :
2
Database :
Academic Search Index
Journal :
IEEE Transactions on Components & Packaging Technologies
Publication Type :
Academic Journal
Accession number :
6874514
Full Text :
https://doi.org/10.1109/TCAPT.2002.1010006