80 results on '"Miyashita, K."'
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2. New method for liquid-medication filling systems
3. Control circuit topology of a time-divided torque and suspension force control type bearingless motor
4. New layout dependency in high-k/Metal Gate MOSFETs
5. Design of a time-divided torque and suspension force control type bearingless motor
6. Competitive and cost effective high-k based 28nm CMOS technology for low power applications
7. A cost-conscious 32nm CMOS platform technology with advanced single exposure lithography and gate-first metal gate/high-k process
8. Impact of tantalum composition in TaC/HfSiON gate stack on device performance of aggressively scaled CMOS devices with SMT and strained CESL
9. Advanced DSS MOSFET technology for ultrahigh performance applications
10. 0.7 V SRAM Technology with Stress-Enhanced Dopant Segregated Schottky (DSS) Source/Drain Transistors for 32 nm Node
11. Study on High Performance (110) PFETs with Embedded SiGe
12. Ultra Low Voltage Operations in Bulk CMOS Logic Circuits with Dopant Segregated Schottky Source/Drain Transistors
13. A plastic packaged Ku-band LNB with very high susceptibility to supply PLL in 0.18um CMOS.
14. A Ku-band down-converter with perfect differential PLL in 0.18um CMOS.
15. Chapter 5: Beam Control: Lens-Coupled Imaging Arrays for the Millimeter-and Submillimeter-Wave Regions.
16. A Map Matching Algorithm for Car Navigation Systems that Predict User Destination.
17. An over-12-Gbps on-chip transmission line interconnect with a pre-emphasis technique in 90 nm CMOS.
18. Coordinating Service Distribution through Cooperative "YuuZuu" Reservations.
19. Doping accuracy requirements of USJ processes for advanced sub-100 nm CMOS devices
20. Advanced CMOS device sensitivity to USJ processes and the required accuracy of doping and activation
21. Advanced CMOS device sensitivity to USJ processes and the required accuracy of doping and activation.
22. RF bipolar transistors in CMOS compatible technologies.
23. In/Sb halo doping and replaced anneal sequence for 80 nm CMOS.
24. A 1.5 V high performance mixed signal integration with indium channel for 130 nm technology node.
25. Optimized halo structure for 80 nm physical gate CMOS technology with indium and antimony highly angled ion implantation.
26. An 80 nm dual-gate CMOS with shallow extensions formed after activation annealing and SALICIDE.
27. Learning control knowledge through cases in schedule optimization problems.
28. Using case-based reasoning to acquire user scheduling preferences that change over time.
29. A framework for constructing animations via declarative mapping rules.
30. Growth and properties of tungsten-bronze ferroelectric potassium lithium niobate single crystals.
31. A novel 0.15 /spl mu/m CMOS technology using W/WNx/polysilicon gate electrode and Ti silicided source/drain diffusions.
32. Coordinated Service Allocation through Flexible Reservation.
33. Non-contact magnetic toroue sensor
34. Electromagnetic properties of bronze processed Nb3Sn superconducting wires and multi-strand...
35. Critical current densities and magnetic hysteresis losses in submicron filament bronze-processed Nb/sub 3/Sn wires.
36. Lens-coupled imaging arrays for the millimeter- and submillimeter-wave regions.
37. Installation of safety parameter display system in Japanese BWR plant.
38. Development of high-performance polycrystalline silicon thin-film transistors (TFTs) using defect control process technologies.
39. Noncontact magnetic torque sensor.
40. Features of a magnetic rotary encoder.
41. Highly uniform heteroepitaxy of cobalt silicide by using Co-Ti alloy for sub-quarter micron devices
42. Evolving bipedal locomotion with genetic programming - a preliminary report
43. Simulation-Based Advanced WIP Management and Control in Semiconductor Manufacturing
44. High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
45. Growth and properties of tungsten-bronze ferroelectric potassium lithium niobate single crystals
46. Constant time interval simulation for semiconductor manufacturing
47. 110 MHz IF-baseband CMOS receiver for J-CDMA/AMPS application
48. MOSFET design of 100 nm node low standby power CMOS technology compatible with embedded trench DRAM and analog devices
49. A 1.5 V high performance mixed signal integration with indium channel for 130 nm technology node
50. A comparison between the powers of the PARBS and the RMBM
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