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Your search keyword '"Masuda, M"' showing total 145 results
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145 results on '"Masuda, M"'

1. 13.1 A 1.33Tb 4-bit/Cell 3D-Flash Memory on a 96-Word-Line-Layer Technology

Author

Shibata, N., primary, Kanda, K., additional, Shimizu, T., additional, Nakai, J., additional, Nagao, O., additional, Kobayashi, N., additional, Miakashi, M., additional, Nagadomi, Y., additional, Nakano, T., additional, Kawabe, T., additional, Shibuya, T., additional, Sako, M., additional, Yanagidaira, K., additional, Hashimoto, T., additional, Date, H., additional, Sato, M., additional, Nakagawa, T., additional, Takamoto, H., additional, Musha, J., additional, Minamoto, T., additional, Uda, M., additional, Nakamura, D., additional, Sakurai, K., additional, Yamashita, T., additional, Zhou, J., additional, Tachibana, R., additional, Takagiwa, T., additional, Sugimoto, T., additional, Ogawa, M., additional, Ochi, Y., additional, Kawaguchi, K., additional, Kojima, M., additional, Ogawa, T., additional, Hashiguchi, T., additional, Fukuda, R., additional, Masuda, M., additional, Kawakami, K., additional, Someya, T., additional, Kajitani, Y., additional, Matsumoto, Y., additional, Morozumi, N., additional, Sato, J., additional, Raghunathan, N., additional, Koh, Y. L., additional, Chen, S., additional, Lee, J., additional, Nasu, H., additional, Sugawara, H., additional, Hosono, K., additional, Hisada, T., additional, Kaneko, T., additional, and Nakamura, H., additional

Published
2019
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46. A Low-Power and Area-Efficient Radiation-Hard Redundant Flip-Flop, DICE ACFF, in a 65 nm Thin-BOX FD-SOI.

Author

Kobayashi, K., Kubota, K., Masuda, M., Manzawa, Y., Furuta, J., Kanda, S., and Onodera, H.

Subjects
SOFT errors, RADIATION hardening (Electronics), ENERGY consumption, HIGH performance computing, NUCLEAR science
Abstract

In this paper, we propose a low-power area-efficient redundant flip-flop for soft errors, called DICE-ACFF. Its structure is based on the reliable DICE (Dual Interlocked storage CEll) and the low-power ACFF (Adaptive-Coupling Flip-Flop). It achieves lower power at lower data-activity. We designed DICE-FF and DICE-ACFF using 65 nm conventional bulk and thin-BOX FD-SOI (Silicon on Thin-BOX, SOTB) processes. Its area is twice as large as the conventional DFF. As for power dissipation, DICE ACFF achieves lower power than the conventional DFF below 20% data activity. When data activity is 0%, its power is half of the DFF. As for soft error rates DICE ACFFs are 1.5× better than conventional DICE FFs based on circuit-level simulations to estimate critical charge. No SEU is observed on the DICE ACFF by \alpha -particle and neutron irradiations on the bulk and SOTB chips. From neutron irradiation results, the soft error rate of the DFF of the SOTB chip is 1/15 compared with that of the bulk chip. [ABSTRACT FROM PUBLISHER]

Published
2014
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