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It is discussed in this paper what resistance increase can be detected by an electrical interconnect test method that occurs after shipping to market at interconnects between ICs and printed circuit boards. The test method is based on a quiescent current made flow through a diode embedded for the tests. Independently of the current variations caused by process variations of ICs, we show by Spice simulations that resistance increase of 0.5 Ω can be detected by the test method with a measurement tool of 0.1mV resolution.

For testing delay faults in 3D IC interconnection, we have proposed a DFT (Design-for- Testability) method for TSVs using a modified boundary scan circuit with embedded Time-to-Digital Converter (TDCBS). A TDCBS cell has a delay element to form a delay line. In this paper, for improving delay resolution, delay gates that have small propagation delay time are investigated and implemented as a delay line. In order to prevent pulse shrinking of transition signal through a delay line, the proposed cell is designed to reduce the difference in transition delay between the delay for rising transition and for falling transition. The measurement results for an experimental chip show the effectiveness of our new design.

Dies in 3D stacked ICs are connected with Through-Silicon-Vias or micro bumps. Resistive open defects may occur at interconnects between the dies in fabrication process. The defects may grow to an open circuit fault in the field after shipping to a market. In this paper, a field test method is proposed so as the defect to be detected after shipping to a market before it becomes an open circuit fault. This test method is based on a quiescent supply current that is made flow through an interconnect between dies only in tests. It is shown by Spice simulation that an increase of 0.01Ω is detected by the test method in field tests.

With the high integration of integrated circuits, small delay faults have occurred as the cause of a circuit failure. We have proposed a method for testing small delay faults using a boundary scan circuit with embedded TDC (TDCBS). In this method, delay faults are detected by using the number of stages in which a transition signal has propagated through a delay line. However, there exists delay variation in a delay line. This paper investigated delay variation by measuring transition delay for different paths in the delay line. In addition, to calibrate delay variation, we investigated a calibration method for considering the variation of wire length and delay in a delay line in TDCBS. Measurement results for an experimental chip show that the method can compensate the variations in the delay line.

In this paper, we propose a stand-by interconnect test method of 3D stacked ICs with IEEE 1149.1 test circuits embedded in dies. Resistive open defects are detected after shipping to a market by the test method that occur at input interconnects of dies operating at a stand-by mode. Feasibility of the stand-by tests is examined by SPICE simulation. It is shown that a resistive open defect of $83 k \Omega$ and above can be detected at a test speed of 20MHz by the test method.

A test method is proposed of resistive open defects in an SoC by means of charge volume injected from the VDD terminal. The charge is injected after providing a test input vector from a charge injector instead of a DC power voltage source. It is shown by Spice simulation that a resistive open defect in four parallel inverter chain circuits of 30 stages whose resistance is larger than 10k$\Omega$ can be detected by the test method.

A boundary scan design with embedded time-to-digital converter (TDCBS) has been proposed for testing small delay faults. In this paper, the TDCBS is applied for testing TSVs in 3D IC. To reduce test application time of the TDCBS, we propose a modified TAP controller that utilizes the bypass mode for reducing unnecessary scan shifts during observation of the captured results. The simulation for an experimental circuit is shown to evaluate the effectiveness of the proposed method.

Non-scan based test generation is required to reduce test cost and improve security. However, sequential test generation consumes a lot of time to identify untestable faults. Therefore, it is important to identify untestable faults in the preprocessing of the test generation. In this paper, an unreachable state identification method, which identifies whether states on a few flip-flops can be justified using SAT, and an untestable fault identification method using the unreachable states are proposed. Experimental results show that our proposed method was effective compared with conventional methods.

We propose a supply current test method with a built-in sensor for detecting open defects on signal lines in CMOS logic circuits. The test method is based on an appearance time of dynamic supply current that flows when a test input vector is provided to a device under test. In addition, we propose a test pattern generation algorithm for the test method. An IC embedding the sensor is prototyped to examine the testability of the test method. We show by SPICE simulation and by some experiments with the IC that open defects that is undetectable by delay tests can be detected by the test method.

We have proposed a power supply circuit and an electrical interconnect test method based on charge volume supplied from the power supply circuit. We optimize the supply circuit so as for small resistive open defects that occur at interconnects among dies in 3D stacked ICs to be detected by the test method. We examine what resistive open defects can be detected with the optimized power supply circuit by Spice simulation. The simulation results show that resistive open defects of 1Ω and above can be detected by the test method with the power supply circuit.

Based on the fault behaviors of conventional fault models, the 1-safe and 0-safe fault types are derived in this paper. We can try to store the safe value of a flash cell such that the fault effects can be masked. To boost the masking probability, both the data inversion (DI) and the page address remapping (PAR) techniques are also proposed. DI tries to complement the data bits to be programmed if their values derivate from the safe values of the corresponding faulty flash cells. PAR manipulates the logical-to-physical mapping of data words and the buffer words such that faulty cells can be programmed with their safe values. Since most of the fault effects are masked, we can reduce the strength of the adopted ECC or the amount of incorporated redundancies. The corresponding hardware architectures are also developed. A simulator is developed to evaluate the hardware overhead, repair rate, and reliability. According to experimental results, these measures can be improved significantly with negligible hardware overhead.

We propose a built-in test circuit to detect resistive open defects occurring at interconnects between dies of 3D ICs. The test circuit consists of an I-V converter and a comparator of offset cancellation type. Feasibility of the tests with the circuit is examined by SPICE simulation. It is shown that resistive open defects of 5Ω and above can be detected per 240nsec under process variations of MOSs in the comparator.

Resistive open defects in 3D ICs may change into hard open ones that cause logical errors after shipping to a market. In this paper, a built-in defective level monitoring circuit is proposed to monitor the changing process of resistive open defects occurring at interconnects among dies of 3D ICs in a market. The defect level of a resistive open defect is monitored by means of quiescent supply current made flow with an IEEE 1149.1 test circuit embedded inside dies in the ICs. The monitoring circuit consists of an I-V converter and a comparator of offset cancellation type. Feasibility of the process monitoring is examined by SPICE simulation in this paper. It is shown that the changing process of a resistive open defect can be monitored at the sensitivity of 5Ω.

Resistive open defects may occur at interconnects among dies in 3D stacked ICs. A defect level monitor is proposed so as for the defects to be detected before they change into a hard open defect that generates logical errors. The changing process of resistive open defects is monitored by means of charge volume injected from the monitor. It is shown by Spice simulation that resistive open defects whose resistance is greater than 2Q can be detected by online tests with the monitor before changing them to hard open defects in the field.

With miniaturization of semiconductor manufacturing process, line spacing becomes narrower and hence the influence of coupling capacitance cannot be ignored. The signal delay on a defective line is affected by the signal transitions on its adjacent lines through the coupling capacitance. In addition, the delay size depends on the timing skew between signal transitions on the defective line and its adjacent lines. In test pattern generation, not all adjacent lines are required to have signal transitions to excite the fault effect if a large relative timing skew exists between the faulty line and the adjacent line. In this paper, we propose a selection method of adjacent lines for assigning signal transitions in test pattern generation. The proposed method can reduce the number of adjacent lines used in test pattern generation without degrading the quality of test pattern that can excite the fault effect.

A power supply circuit and an electrical interconnect test method are proposed to detect open defects at interconnects between dies in 3D ICs. The test method is based on the amount of charge injected from the power supply voltage source. It is shown by Spice simulation that resistive open defects whose resistance is greater than 20Ω can be detected with the power supply circuit by the test method.

A three-dimensional integrated circuit is fabricated by stacking multiple dies. A resistive open defect may occur at interconnects between the dies by a void and a crack during fabrication process. We have proposed an electrical test method for an IC made of dies in which boundary scan flip flops are not embedded. In this paper, testability of the test method for resistive open defects is examined by Spice simulation. The results show that a resistive open defect whose resistance is greater than 150Ω is able to be detected at a test speed of 500kHz.

ECC techniques have been widely used for protecting flash memory endurance and permanent faults. Therefore, the fabrication yield and reliability can be enhanced. However, if the number of faulty bits within a codeword is greater than the protection capability of the adopted ECC techniques, the effectiveness of the protection will decrease rapidly. In this paper, adaptive ECC techniques based on address remapping are proposed to cure this drawback. We can change the logical-to-physical address mapping of the page buffer such that faulty cells can be evenly distributed into different codewords. Based on the production test or on-line BIST results, the fault bitmap can be used for executing the remapping algorithm and evaluating control words. Based on the control words, faulty cells can be evenly distributed into different codewords. To conduct the address remapping, a novel page buffer design is also proposed. A simulator is developed to evaluate the hardware overhead, repair rate, effective yield, and reliability. According to experimental results, repair rate, yield, and reliability can be improved significantly with negligible hardware overhead.

Resistive open defects in 3D ICs may change into hard open ones. In this paper, a built-in test circuit is proposed to monitor the changing process of the resistive open defects occurring at interconnects between dies embedding an IEEE 1149.1 test circuit. Feasibility of the process monitoring is examined experimentally in a PCB circuit made of ICs embedding the test circuit. It is shown that the changing process of a resistive open defect can be monitored at a test speed of 500 kHz.

In this paper, a built-in electrical test circuit is proposed to detect an open defect at an interconnect between a land on a printed circuit board and an IC. The test circuit is made of an integrating circuit, nMOS switches and a switch control circuit. A time-varying signal generated by the integrating circuit is provided to a targeted interconnect as a stimulus signal in the tests. An input buffer gate in an IC is utilized as an open sensor in the tests. The open defect is detected by means of supply current of the sensor. We examine by Spice simulation whether open defects can be detected by using the test circuit. The results reveal us that an open defect can be detected at a test speed of 50 kHz for each input terminal of an IC.

Error correction code (ECC) and hard repair (built-in self-repair) techniques by using redundancies have been widely used for improving the yield and reliability of memories. The target faults of these two schemes are soft errors and permanent faults, respectively. In recent works, there are also some techniques integrating ECC and BISR to deal with soft errors and hard defects simultaneously. However, this will compromise reliability since some of the ECC protection capability is used for repairing hard defects. To cure this dilemma, we propose an ECC-enhanced BISR (EBISR) technique which uses ECC to repair single permanent faults first and spares for the remaining faults in the production/power-on test and repair stage. However, techniques are proposed to maintain the original reliability during the on-line test and repair stage. We also propose the corresponding hardware architecture of the EBISR scheme. A simulator is implemented to evaluate the hardware overhead, repair rate, and reliability. Experimental results show that the proposed EBISR scheme can improve yield and reliability significantly with negligible hardware overhead.

Instead of using hardware redundancy and information redundancy for the repair of permanent faults and soft errors, respectively. We try to use the error detection/correction (EDAC) codes for correcting both faults. However, this is not suitable for a codeword containing multiple faulty bits. Fortunately, we propose the fault scrambling technique to distribute faulty bits into different codewords such that the number of faulty cells in each codeword is below the protection capability of the adopted EDAC code. However, it is inevitable to seek for efficient algorithm for the evaluation of control words to steer the scrambling of faults. Therefore, a heuristic scrambling analysis algorithm suitable for built-in implementation is proposed. A simulator is developed to evaluate the hardware overhead and repair rate. According to experimental results, the repair rate can be improved significantly with negligible hardware overhead.

An electrical interconnect test method and a testable design method are proposed of a 3D stacked ICs made of dies in which boundary scan flip flops are not embedded in this paper. Open defects occurring at interconnects between dies designed by the testable design method are detected by the test method. In order to examine feasibility of the electrical tests, a PCB circuit is tested by the test method made of a prototype IC designed by the testable design method. The experimental results show that a hard open defect and a resistive open one are able to be detected by the test method at a test speed of 500 kHz.

In this paper, an electrical test method and a power supply circuit are proposed for open defects at interconnects between dies in a 3D IC. The test method is based on volume of charge injected from the power supply circuit. Feasibility of the electrical tests is examined by Spice simulation. The simulation results show that a hard open defect, capacitive ones and resistive ones whose resistance is greater than or equal to 100Ω may be detected at a test speed of 0.9MHz.

In 3D IC testing, resistive open defects in TSVs are difficult to test since its delay size is usually very small. In this paper, we propose a new test circuit for detecting delay faults in TSVs considering the coupling effect between adjacent TSVs in a TSV array since a transition signal at the defective TSV is more affected by crosstalk from its adjacent lines compared with a fault-free TSV. In the proposed design-for-testability circuit, TSVs are connected into two rings that can provide opposite transitions for adjacent TSVs to increase the crosstalk induced delay. We estimated the detectability of open defects in a TSV by simulation.

A CMOS image pixel circuit is proposed which is able to be tested by an electrical test method in this paper. The image pixel circuit is tested as an analog circuit without irradiating light to it. A CMOS image sensor is designed to evaluate testability of the pixel circuit. It is shown by SPICE simulation whether 89% of open defects inserted in the image pixel circuit are detected by the electrical test method.

In this paper, an electrical interconnect test method and a built-in test circuit are proposed to detect and locate open defects in a 3D stacked IC made of dies, in which ESD protection circuits are not embedded. The test method is based on quiescent supply current that is made flow through the interconnect to be tested only in the tests. Feasibility of the tests is evaluated by Spice simulation. The simulation results show that open defects in a 3D stacked IC not embedding ESD protection circuits are detected by the test method, like in the tests of ICs embedding ESD protection circuits.

Hybrid scrambling technique is proposed for NROM-based ROMs in order to enhance the fabrication yield and reliability. Besides the traditional hardware redundancy techniques, fault masking features are also exploited to further improve the fabrication yield and reduce the amount of extra spare rows/columns. The hybrid scrambling technique basically consists of the row scrambling and the column scrambling techniques. Therefore, instead of scrambling a memory row/column, a logical memory cell can be scrambled into any of the logical memory cell address. This greatly improves the flexibility of scrambling. A hybrid scrambling control word is used for the control of the scrambling. Since the codes to be programmed into the NROM chips are known before programming, selecting a suitable code for programming a faulty NROM chip is helpful to further mask the faulty effects. Based on the proposed technique, possibilities of fault masking can be maximized. The proposed test and repair techniques can be easily incorporated into the ROM BIST architectures. According to experimental results, the fabrication yield can be improved significantly. Moreover, the incurred hardware overhead is almost negligible.

A testable design method for electrical testing is proposed in this paper to detect open defects occurring at interconnects between dies in a 3D IC and locate the defective interconnects. An IEEE 1149.1 test circuit is utilized to provide a test input vector to a targeted interconnect in the electrical tests. Feasibility of the electrical tests is evaluated by Spice simulation. It is shown by the experiments that a hard open defect and a resistive open defect can be detected at a test speed of 1GHz.

In this paper, a built-in supply current test circuit is proposed to detect open defects occurring at interconnects between dies including an IEEE 1149.1 test circuit and locate the defective interconnects in a 3D IC. Feasibility of interconnect tests with the test circuit is examined by some experiments with a prototyping IC in which the test circuit is embedded and by Spice simulation. The simulation results show that a hard open defect, a capacitive open one of 10nF and a resistive open one of 1kΩ can be detected at a test speed of 1MHz per an interconnect.

Fault scrambling technique is considered a promising way to distribute faulty bits into different code words such that the number of faulty cells in each codeword is below the protection capability of the adopted EDAC coding techniques. However, the effectiveness of the scrambling technique depends on the determination of the row/column scrambling control words. Therefore, we propose a heuristic algorithm suitable for built-in implementation for the evaluation of control words based on the fault bitmap and the specifications of the memory. The corresponding built-in scrambling analysis (BISA) circuit is also proposed. The BISA module can be easily integrated into the conventional built-in self-repair (BISR) module. A simulator is developed to evaluate the hardware overhead and repair rate. According to experimental results, the repair rate can be improved significantly with negligible hardware overhead.

An estimation method of a threshold value for electrical interconnect tests is proposed for detecting open defects at interconnects between dies in a 3D IC. Threshold values of a circuit made of our prototyping IC on a printed circuit board are derived by the estimation method. The results show us that resistive open defects whose resistance is larger than 16.1Ω can be detected with a threshold value estimated by the method.

An electrical test method is proposed for detecting an open defect occurring at a data bus of a 3D SRAM IC. Targeted defects are a hard open defect and a soft one in a data bus. The test method is based on supply current of the IC. There is no need to add a circuit for the test method to an original circuit. Feasibility of the tests is examined by some experiments for a circuit made of an SRAM IC on a printed circuit board. The experimental results show us that resistive open defects whose resistance is greater than 300Ω can be detected by the test method.

In this paper, we propose a test method for detecting pin opens of CMOS logic ICs in assembled PCBs. The test method is based on supply current of a circuit under test which flows when a time-varying signal is provided to a targeted pin with a test probe as a stimulus. Test signal's amplitude is less than VDD. Test vector generations are not needed for the tests. In the test, the test probe also can be checked simultaneously. The test can be used on devices such as BGA ICs which solder parts are hidden from a field of view. We show by some experiments that pin opens of BGA ICs can be detected by the supply current test method.

Three-dimensional integration is considered a promising solution to cure the challenges of performance, power consumption, quality, and reliability issues. The feature of 2.5D ICs is that the dies are stacked on a passive silicon interposer and the dies communicate with each other by means of TSV-based interconnects and re-Distribution layers (RDL) within the silicon interposer. This paper aims to investigate the efficient post-bond test technique for the 2.5D ICs with silicon interposer. In order to efficiently reuse the functional interconnects as the parallel TAM (test access mechanism) for testing dies, a novel macro-die-based interconnect reuse strategy and its corresponding design-for-test (DFT) architecture are proposed in this paper. The proposed strategy merges several dies to form a macro die and then connected to other dies to form a daisy chain for testing. Experimental results show that the proposed techniques have higher success rates for the required TAM width constraints. Moreover, since we can get wider TAMs, the test length then can be reduced significantly.

In this paper, a built-in test circuit of electrical tests is proposed to detect pin opens of CMOS ICs. When a circuit is tested by the test method, current is made to flow through a targeted pin. An open defect is detected by means of the difference between the current of a defect-free circuit and the measured one. Feasibility of tests with the built-in supply current test circuit is examined by Spice simulation. It is shown that a pin open in a CMOS IC can be detected with the test circuit at a speed of 1MHz.

In this paper, a Design-for-Testability method is proposed to detect an open defect occurring at an interconnect between dies in a 3D IC. The open defect is detected by means of a supply current flowing whenever a time-varying voltage signal is provided to the targeted interconnect as a test input stimulus. Feasibility of the test method is examined by targeted experiments and circuit simulations. It is shown that an open defect in a testable designed IC is capable of being detected by measuring the supply current of the IC.

Modern high performance, high density integrated circuits use a very large number of metal layers, necessitating the need to deal with the problem of resistive open defects. Resistive opens often manifest as and are modeled as small delay faults. Furthermore, in deep sub-micron technologies, it is known that the additional delay of a line with resistive open fault is not only a function of the resistant of the faulty line but it is also dependent on the signal transition(s) on its adjacent lines. In this paper, we propose an efficient simulation method to simulate small delay faults and we use this simulator to diagnose resistive open faults. The fault simulator developed by us simulates all delay faults for one signal line simultaneously. This information is then used to deduce the candidate faulty lines in two steps. Experimental results for ISCAS'89 benchmark circuits show that by using the method proposed by us the faulty lines can be identified correctly in most cases.

Instead of merely using redundant rows/columns to replace faulty cells, error-correcting codes are also considered an effective technique to cure permanent faults for the enhancement of fabrication yield and reliability of memories. However, if the number of faulty bits in a codeword is greater than 1, the protection capability of the widely used SEC-DED (single-error correction and double-error detection) codes will be limited. In order to cure this dilemma, efficient fault scrambling techniques are proposed in this paper. Unlike the fixed constituting memory cells of a codeword in the conventional EDAC schemes, we try to reconstruct the memory cells of code words such that each codeword consists of at most one faulty cell. The corresponding scrambling circuits are also proposed and a simulator is developed to evaluate the repair rates and hardware overhead. According to experimental results, the repair rates can be improved significantly with negligible hardware overhead.

A testable design method for electrical testing is proposed in this paper to detect open defects occurring at interconnects between dies in a 3D IC and locate the defective interconnects. An IEEE 1149.1 test circuit is utilized to provide a test input vector to a targeted interconnect in the electrical tests. Feasibility of the electrical tests is evaluated by Spice simulation and some experiments with a prototyping IC. It is shown by the experiments that an open defect can be detected at a test speed of 1MHz.

In this paper, a built-in electrical test circuit is proposed to detect an open defect at an interconnect between a land in a printed circuit board and an IC. An inverter gate is used as an open sensor in the test circuit. An AC voltage signal is provided to a targeted interconnect and the sensor as a test input signal to detect the defect. The defect is detected by means of supply current of the sensor. We examine by Spice simulation whether open defects can be detected with the test circuit. The results reveal us that an open defect can be detected at a test speed of 1 MHz for each interconnect.

In this paper, a built-in test circuit is proposed to detect and locate open defects occurring at interconnects between dies in a 3D IC by means of the quiescent supply current. In the test circuit, IEEE 1149.1 test architecture is used to provide a test vector to a targeted interconnect. Testability of the testing with the test circuit is evaluated by Spice simulation. The simulation results show us that a hard open defect and a soft open one generating additional delay of 0.58nsec can be detected at a test speed of 100MHz.

In this paper, a built-in test circuit is proposed to detect open defects that occur at interconnects between dies inside 3D ICs. An inverter gate is used in the test circuit as an open sensor. Open defects are detected by means of supply current of the inverter gate flowing when an AC voltage signal is provided to targeted interconnects as a stimulus. The interconnect at which an open defect occurs can be located with the test circuit. Feasibility of tests with the test circuit is examined by circuit simulation. The results promise us that open defects can be detected and also defective interconnects can be located with the test circuit.

In this paper, a supply current test method of 3D ICs is proposed to detect open defects occurring at interconnects between two dies in which IEEE 1149.1 architecture is implemented and locate the defective interconnects. Also, a testable design method is proposed for the test method and a testable designed IC is prototyped. Furthermore, testability of the test method is evaluated by some experiments with the prototyped IC and by Spice simulation. The simulation results show that an open defect can be detected within 10nsec which generates only additional delay of 0.7nsec.

This paper presents a design-for-testability method for detecting delay faults. In order to observe the effect of small delay defects, we present modified boundary scan cells in which a time-to-digital converter (TDC) is embedded. In our boundary scan cells, flip-flops are utilized for both making a scan path and capturing circuit response. The architecture of the boundary scan design is proposed to detect delay from the other cores or chips or its interconnects. The basic operation of the design is evaluated by simulation and by experimental ICs. Experimental results show that the measurement of the transition delay can be achieved by the boundary scan design with the time-to-digital converter.

In this paper, we propose a supply current testable resistor string DAC of decoder type whose area overhead is small and a supply current test method. Open defects and short ones in the DAC can be detected by the test method with about 50% of the exhausted test vectors. It is shown by some experiments that most of the targeted defects in our testable DACs of 4 and 8 bits can be detected by the test method.

In this paper, a method for reducing test data volume of BIST-aided scan test (BAST) is proposed. In our BAST method, scan chains are ordered using compatible flip-flops to reduce the conflicting bits between ATPG pattern and random pattern obtained by LFSR. The inverter block in BIST-aided scan architecture is modified for shifting inverter code such that the random pattern produced by LFSR has less conflicting bits with ATPG patterns when providing the test pattern to the scan chains. The experimental results show the method can reduce the test data volume than the previous method.